AD ADG731BSU 16-/32-channel, serially controlled 4 1.8 v to 5.5 v, 2.5 v, analog multiplexer Datasheet

a
16-/32-Channel, Serially Controlled 4 ⍀
1.8 V to 5.5 V, ⴞ2.5 V, Analog Multiplexers
ADG725/ADG731
FEATURES
3-Wire SPI Compatible Serial Interface
1.8 V to 5.5 V Single Supply
ⴞ2.5 V Dual-Supply Operation
4 ⍀ On Resistance
0.5 ⍀ On Resistance Flatness
7 mm x 7 mm 48-Lead Chip Scale Package (LFCSP)
or 48-Lead TQFP Package
Rail-to-Rail Operation
Power-On Reset
42 ns Switching Times
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Parallel
Interface, See ADG726/ADG732
FUNCTIONAL BLOCK DIAGRAM
ADG731
ADG725
S1
S1A
DA
S16A
D
S1B
DB
S32
S16B
INPUT SHIFT
REGISTER
SCLK DIN SYNC
INPUT SHIFT
REGISTER
SCLK DIN SYNC
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTION
The ADG731/ADG725 are monolithic, CMOS, 32-channel/
dual 16-channel analog multiplexers with a serially controlled
3-wire interface. The ADG731 switches one of 32 inputs
(S1–S32) to a common output, D. The ADG725 can be configured as a dual mux switching one of 16 inputs to one output, or a
differential mux switching one of 16 inputs to a differential output.
These mulitplexers utilize a 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and some DSP
interface standards. On power-up, the Internal Shift Register
contains all zeros and all switches are in the OFF state.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switching speed with very low on resistance and leakage currents.
They operate from a single supply of 1.8 V to 5.5 V or a
± 2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms, is
closely matched between switches, and is very flat over the full
signal range.
These parts can operate equally well as either multiplexers or
demultiplexers and have an input signal range that extends to the
supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The ADG731 and ADG725 are serially controlled 32-channel,
and dual/differential 16-channel multiplexers, respectively. They
are available in either a 48-lead LFCSP or TQFP package.
PRODUCT HIGHLIGHTS
1.
3-Wire Serial Interface.
2.
1.8 V to 5.5 V Single-Supply or ± 2.5 V Dual-Supply
Operation. These parts are specified and guaranteed
with 5 V ± 10%, 3 V ± 10% single-supply,
and ± 2.5 V ± 10% dual-supply rails.
3.
On Resistance of 4 W.
4.
Guaranteed Break-Before-Make Switching Action.
5.
7 mm ¥ 7 mm 48-Lead Chip Scale Package (LFCSP) or
48-Lead TQFP Package.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADG725/ADG731–SPECIFICATIONS1 (V
Parameter
+25⬚C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40⬚C to +85⬚C
0 to VDD
4
5.5
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
6
0.3
0.8
0.5
1
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG731
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.25
± 0.05
± 0.5
±1
± 0.05
± 0.5
±1
= 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
± 2.5
±5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.4
0.8
V min
V max
± 0.5
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF; Test Circuit 5
VS1 = 3 V/0 V, VS32 = 0 V/3 V
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 6
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
±1
± 2.5
±5
0.005
CIN, Digital Input Capacitance
DD
5
VD = VS = 1 V or 4.5 V;
Test Circuit 4
2
DYNAMIC CHARACTERISTICS
tTRANSITION
Break-Before-Make Time Delay, tD
42
53
30
Charge Injection
5
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–72
dB typ
34
18
15
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF; Test Circuit 10
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
10
µA typ
µA max
62
1
–3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
20
f = 1 MHz
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
ADG725/ADG731
SPECIFICATIONS1 (V
DD
Parameter
= 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
+25⬚C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40⬚C to +85⬚C
0 to VDD
7
11
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG731
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.25
± 0.05
± 0.5
±1
± 0.05
± 0.5
±1
12
0.35
1
3
V
Ω typ
Ω max
Ω typ
Ω max
Ω max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
± 2.5
±5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
2.0
0.7
V min
V max
± 0.5
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF; Test Circuit 5
VS1 = 2 V/0 V, VS32 = 0 V/2 V
RL = 300 Ω, CL = 35 pF
VS = 2 V; Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
±1
± 2.5
±5
0.005
CIN, Digital Input Capacitance
Unit
5
VS = VD = 1 V or 3 V;
Test Circuit 4
2
DYNAMIC CHARACTERISTICS
tTRANSITION
Break-Before-Make Time Delay, tD
60
80
30
Charge Injection
1
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–72
dB typ
Channel-to-Channel Crosstalk
–72
dB typ
34
18
15
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF; Test Circuit 10
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
5
µA typ
µA max
90
1
–3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
10
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. A
–3–
f = 1 MHz
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG725/ADG731
V 10%, V = –2.5 V 10%, GND = 0 V,
otherwise noted.)
DUAL-SUPPLY SPECIFICATIONS1 (Vunless= +2.5
DD
Parameter
+25⬚C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40⬚C to +85⬚C
VSS to VDD
4
5.5
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
6
0.3
0.8
0.5
1
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG731
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.01
± 0.25
± 0.05
± 0.5
±1
± 0.01
± 0.5
±1
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
VDD = +2.75 V, VSS = –2.75 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 2
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 3
± 2.5
±5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
1.7
0.7
V min
V max
± 0.5
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF; Test Circuit 5
VS1 = 1.5 V/0 V, VS32 = 0 V/1.5 V
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
± 0.5
± 2.5
±5
0.005
CIN, Digital Input Capacitance
SS
5
VS = VD = +2.25 V/–1.25 V; Test Circuit 4
2
DYNAMIC CHARACTERISTICS
tTRANSITION
Break-Before-Make Time Delay, tD
55
75
15
Charge Injection
Off Isolation
1
–72
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
–72
dB typ
34
18
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF; Test Circuit 10
130
260
pF typ
pF typ
f = 1 MHz
f = 1 MHz
150
300
pF typ
pF typ
f = 1 MHz
f = 1 MHz
10
µA typ
µA max
µA typ
µA max
84
1
–3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
20
ISS
10
20
VDD = +2.75 V
Digital Inputs = 0 V or 2.75 V
VSS = –2.75 V
Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. A
ADG725/ADG731
TIMING CHARACTERISTICS1, 2
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
30
33
13
13
13
40
5
4.5
33
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Minimum SYNC Low Time
Data Setup Time
Data Hold Time
Minimum SYNC High Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
Specifications subject to change without notice.
t1
SCLK
t2
t8
t4
t3
t5
SYNC
t7
t6
DB0
DB7
DIN
Figure 1. 3-Wire Serial Interface Timing Diagram
DB0 (LSB)
DB7 (MSB)
EN
CSA CSB
X
A3
A2
A1
EN
DATA BITS
CS
X
A4
A3
A2
A1
A0
DATA BITS
Figure 2. ADG725 Input Shift Register Contents
REV. A
DB0 (LSB)
DB7 (MSB)
A0
Figure 3. ADG731 Input Shift Register Contents
–5–
ADG725/ADG731
ABSOLUTE MAXIMUM RATINGS 1
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Thermal Impedance (4-Layer Board)
48-lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W
48-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
(TA = 25°C, unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at SCLK, SYNC, DIN, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
ORDERING GUIDE
Model
ADG725BCP
ADG725BCP-REEL
ADG725BCP-REEL7
ADG725BSU
ADG725BSU-REEL
ADG731BCP
ADG731BCP-REEL
ADG731BCP-REEL7
ADG731BSU
ADG731BSU-REEL
Temperature Range
o
o
–40 C to +85 C
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
Package Description
Package Option
Lead Frame Chip-Scale Package (LFCSP)
Lead Frame Chip-Scale Package (LFCSP)
Lead Frame Chip-Scale Package (LFCSP)
Thin Plastic Quad Flat Package (TQFP)
Thin Plastic Quad Flat Package (TQFP)
Lead Frame Chip-Scale Package (LFCSP)
Lead Frame Chip-Scale Package (LFCSP)
Lead Frame Chip-Scale Package (LFCSP)
Thin Plastic Quad Flat Package (TQFP)
Thin Plastic Quad Flat Package (TQFP)
CP-48
CP-48
CP-48
SU-48
SU-48
CP-48
CP-48
CP-48
SU-48
SU-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. A
ADG725/ADG731
48 47 46 45 44 43 42 41 40 39 38 37
S12A 1
S29
S30
S31
S32
NC
D
NC
NC
S16
S15
S14
S13
S13B
S14B
S15B
S16B
DB
NC
DA
NC
S16A
S15A
S14A
S13A
PIN CONFIGURATIONS
48-Lead LFCSP and TQFP
48 47 46 45 44 43 42 41 40 39 38 37
36
S12B
S12 1
35
S11B
S11 2
S10A 3
34
S10B
S10 3
34 S26
S9A 4
33
S9B
S9 4
33 S25
S8A 5
32
S8B
S8 5
31
S7B
S7 6
ADG731
TOP VIEW
(Not to Scale)
S11A 2
PIN 1
IDENTIFIER
ADG725
S7A 6
S6A
TOP VIEW
(Not to Scale)
7
36 S28
PIN 1
IDENTIFIER
35 S27
32 S24
31 S23
30
S6B
S6 7
S5A 8
29
S5B
S5 8
29 S21
S4A 9
28
S4B
S4 9
28 S20
S3A 10
27
S3B
S3 10
27 S19
S2A 11
26
S2B
S2 11
26 S18
25
S1B
S1 12
25 S17
VSS
GND
NC
NC
NC
SCLK
SYNC
DIN
NC
VDD
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC = NO CONNECT
VSS
GND
NC
NC
NC
SCLK
SYNC
DIN
NC
NC
VDD
VDD
NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24
VDD
S1A 12
30 S22
PIN FUNCTION DESCRIPTIONS
ADG725
ADG731
Mnemonic Function
1–12, 25–40, 1–12, 25–40, Sxx
45–48
45–48
13, 14
13, 14
VDD
17
17
SYNC
18
18
DIN
19
19
SCLK
23
24
23
24
GND
VSS
41, 43
N/A
N/A
43
DA, DB
D
REV. A
Source. May be an input or output.
Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V
and a dual supply of ± 2.5 V.
Active Low Control Input. This is the frame synchronization signal for the input
data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input
Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the following clocks. After eight falling clock edges, switch conditions
are automatically updated. SYNC may be used to frame the signal or just pulled low
for a short period of time to enable the counter and input buffers.
Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of
the serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
Ground Reference
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications,
connect to GND.
Drain. May be an input or output.
Drain. May be an input or output.
–7–
ADG725/ADG731
Table I. ADG725 Truth Table
A3
A2
A1
A0
EN
CSA
CSB
Switch Condition
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Retains Previous Switch Condition
All Switches OFF
S1A – DA, S1B – DB
S2A – DA, S2B – DB
S3A – DA, S3B – DB
S4A – DA, S4B – DB
S5A – DA, S5B – DB
S6A – DA, S6B – DB
S7A – DA, S7B – DB
S8A – DA, S8B – DB
S9A – DA, S9B – DB
S10A – DA, S10B – DB
S11A – DA, S11B – DB
S12A – DA, S12B – DB
S13A – DA, S13B – DB
S14A – DA, S14B – DB
S15A – DA, S15B – DB
S16A – DA, S16B – DB
X = Don’t Care
Table II. ADG731 Truth Table
A4
A3
A2
A1
A0
EN
CSA
Switch Condition
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Retains Previous Switch Condition
All Switches OFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X = Don’t Care
–8–
REV. A
ADG725/ADG731
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
VD (VS)
RON
⌬RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
VINH
IINL (IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
CIN
tTRANSITION
tD
Charge Injection
OFF Isolation
Crosstalk
On Response
Insertion Loss
REV. A
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.
Positive Supply Current.
Negative Supply Current.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Analog Voltage on Terminals D, S.
Ohmic Resistance between D and S.
On Resistance Match between any Two Channels.
Flatness is defined as the difference between the maximum and minimum value of on resistance,
as measured over the specified analog signal range.
Source Leakage Current with the Switch OFF.
Drain Leakage Current with the Switch OFF.
Channel Leakage Current with the Switch ON.
Maximum Input Voltage for Logic 0.
Minimum Input Voltage for Logic 1.
Input Current of the Digital Input.
OFF Switch Source Capacitance. Measured with reference to ground.
OFF Switch Drain Capacitance. Measured with reference to ground.
ON Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance.
Delay time measured between the 50% points of the eighth clock falling edge and 90% points of the output
when switching from one address state to another.
OFF time measured between the 80% points of both switches when switching from one address state to another.
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
A measure of unwanted signal coupling through an OFF switch.
A measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance.
The Frequency Response of the ON Switch.
The Loss Due to the On Resistance of the Switch.
–9–
ADG725/ADG731–Typical Performance Characteristics
8
7
VDD = 3.0V
VDD = 5.5V
5
VDD = 3.3V
4
8
7
7
6
RESISTANCE – RESISTANCE – 6
8
VSS = 0V
TA = 25C
VSS = 0V
3
VDD = 4.5V
VDD = +2.25V
VSS = –2.25V
5
TA = 25C
VDD = +2.5V
VSS = –2.5V
6
RESISTANCE – VDD = 2.7V
4
VDD = +2.75V
VSS = –2.75V
3
2
5
+85C
4
+25C
3
–40C
2
2
1
1
VDD = 5V
1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VD, VS – V
0
–2.75
–1.75
–0.75
0.25
VD, VS – V
1.25
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VD, VS – V
2.25
TPC 3. On Resistance vs. VD (VS)
for Different Temperatures,
Single Supply
TPC 2. On Resistance vs.
VD (VS), Dual Supply
TPC 1. On Resistance vs.
VD (VS), Single Supply
0.5
8
8
VSS = 0V
7
7
0.3
+85C
6
RESISTANCE – 5
–40C
4
3
5
+85C
4
+25C
3
2
1
1
0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
VD, VS – V
0
–2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
VD, VS – V
80
20
70
VDD = +2.5
VSS = –2.5
15
IS (OFF)
TIME – ns
VDD = +3V
VSS = 0V
0
50
40
VDD = 5V
VDD = +5V
VSS = 0V
20
–10
10
TA = 25C
–2
–1
0
1
2
VD, VS – V
3
4
5
TPC 7. ADG731 Charge Injection
vs. Source Voltage
0
–40
15
25
35
45
55
65
TEMPERATURE – C
75
85
1.8
VDD = 3V
30
–5
5
TPC 6. Leakage Currents vs.
Temperature
60
10
–0.5
TPC 5. On Resistance vs.
VD (VS), Dual Supply
VSS = 0V
QINJ – pC
ID (ON)
–0.4
25
–3
0.0
–0.1
–0.3
TPC 4. On Resistance vs. VD (VS),
Single Supply
–15
0.1
–0.2
–40C
2
5
ID (OFF)
0.2
LOGIC THRESHOLD VOLTAGE – V
RESISTANCE – 6
CURRENT – nA
+25C
VDD = 5V
VSS = 0V
0.4
–20
0
20
40
TEMPERATURE – C
60
TPC 8. Switching Times vs.
Temperature
–10–
80
1.6
1.4
1.2
RISING
1.0
FALLING
0.8
0.6
0.4
0.2
0
TA = 25C
0
1
2
3
4
5
6
VDD – V
TPC 9. Logic Threshold Voltage
vs. Supply Voltage
REV. A
ADG725/ADG731
VDD = 5V
TA = 25C
–10
–20
VDD = 3V, 5V
TA = 25C
ADG725
VDD = 5V
TA = 25C
–2
–30
–40
–50
–60
–70
ATTENUATION – dB
–20
ATTENUATION – dB
ATTENUATION – dB
0
0
0
–10
–30
–40
–50
–60
–70
–80
–80
–90
–90
–4
ADG731
–6
–8
–10
–12
–100
0.03
0.1
1
10
FREQUENCY – MHz
–100
0.003
100
TPC 10. OFF Isolation vs. Frequency
0.1
1
10
FREQUENCY – MHz
–14
0.03
100
TPC 11. Crosstalk vs. Frequency
0.1
1
10
FREQUENCY – MHz
TPC 12. ON Response vs. Frequency
Test Circuits
IDS
VDD
V1
VSS
VSS
VDD
S1
ID (OFF)
D
S2
S
A
A
D
S32
EN
VS
GND
VS
VD
LOGIC 1
RON = V1/IDS
Test Circuit 1. On Resistance
Test Circuit 3. ID (OFF)
VDD
IS (OFF)
A
S1
VDD
VSS
VDD
VSS
VSS
VDD
VSS
D
S1
S32
D
S2
VS
ID (ON)
A
A
VD
S32
VS
EN
GND
LOGIC 1
VS
VD
Test Circuit 2. IS (OFF)
REV. A
GND
Test Circuit 4. ID (ON)
–11–
100
ADG725/ADG731
TEST CIRCUITS (continued)
VDD
VSS
VDD
VSS
8TH FALLING EDGE
SCLK
S1
8TH FALLING EDGE
50%
50%
VS1
S2 TO S31
ADG731*
VS32
S32
VS1
D
90%
VOUT
CL
35pF
RL
300
GND
VOUT
90%
VS32
tTRANSITION
*SIMILAR CONNECTION FOR ADG725
tTRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VDD
VSS
VDD
VSS
8TH FALLING EDGE
SCLK
VS
S1
0V
S2 THRU S31
ADG731*
S32
VS
D
VOUT
RL
300
GND
CL
35pF
80%
80%
VOUT
t OPEN
*SIMILAR CONNECTION FOR ADG725
Test Circuit 6. Break-Before-Make Delay, tOPEN
VDD
VSS
VDD
VSS
8th FALLING EDGE
RS
SCLK
ADG731*
S
D
VOUT
CL
1nF
VS
VOUT
GND
VOUT
QINJ = CL VOUT
*SIMILAR CONNECTION FOR ADG725
Test Circuit 7. Charge Injection
–12–
REV. A
ADG725/ADG731
POWER-ON RESET
VDD
VSS
0.1␮F
On power-up of the device, all switches will be in the OFF
condition. The Internal Shift Register is filled with zeros and
will remain so until a valid write takes place.
0.1␮F
NETWORK
ANALYZER
VSS
VDD
SERIAL INTERFACE
50⍀
S
50⍀
The ADG725 and ADG731 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards and most DSPs.
Figure 1 shows the timing diagram of a typical write sequence.
VS
D
RL
50⍀
ADG731*
GND
VOUT
OFF ISOLATION = 20 LOG
VOUT
VS
*SIMILAR CONNECTION FOR ADG725
Test Circuit 8. OFF Isolation
VDD VSS
S1
VDD VSS
50⍀
NETWORK
ANALYZER
S2
ADG731*
50⍀
S32
VS
D
RL
50⍀
GND
VOUT
Test Circuit 9. Channel-to-Channel Crosstalk
The ADG725 CSA and CSB data bits allow the user the flexibility to change the configuration of either or both banks of the
multiplexer.
Microprocessor interfacing to the ADG725/ADG731 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
interface consisting of a clock signal, a data signal, and a
synchronization signal. The ADG725/ADG731 requires an
8-bit data-word with data valid on the falling edge of SCLK.
Figures 4–7 illustrate simple 3-wire interfaces with popular
microcontrollers and DSPs.
VSS
0.1␮F
When SYNC goes low, the Input Shift Register is enabled. An
8-bit counter is also enabled. Data from DIN is clocked into the
Shift Register on the falling edge of SCLK. Figures 2 and 3
show the contents of the Input Shift Registers for these devices.
When the part has received eight clock cycles after SYNC has
been pulled low, the switches are automatically updated with
the new configuration and the Input Shift Register is disabled.
MICROPROCESSOR INTERFACING
*SIMILAR CONNECTION FOR ADG725
VOUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VS
VDD
Data is written to the 8-bit Shift Register via DIN under the
control of the SYNC and SCLK signals.
0.1␮F
ADSP-21xx to ADG725/ADG731 Interface
VSS
VDD
S
NETWORK
ANALYZER
50⍀
VS
D
ADG731*
GND
INSERTION LOSS = 20 LOG
RL
50⍀
VOUT
The ADSP-21xx family of DSPs are easily interfaced to the
ADG725/ADG731 without the need for extra logic. Figure 4
shows an example of an SPI interface between the ADG725/
ADG731 and the ADSP-2191M. SCK of the ADSP-2191M
drives the SCLK of the mux, while the MOSI output drives the
serial data line, DIN. SYNC is driven from one of the port lines,
in this case SPIxSEL.
VOUT WITH SWITCH
SPIxSEL
VOUT WITHOUT SWITCH
ADSP-2191M*
*SIMILAR CONNECTION FOR ADG725
MOSI
SYNC
ADG725/ADG731
DIN
Test Circuit 10. Bandwidth
SCK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 4. ADSP-2191M to ADG725/ADG731 Interface
REV. A
–13–
ADG725/ADG731
A serial interface between the ADG725/ADG731 and the ADSP2191M SPORT is shown in Figure 5. In this interface example,
SPORT0 is used to transfer data to the switch. Transmission is
initiated by writing a word to the Tx Register after the SPORT
has been enabled. In a write sequence, data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
ADG725/ADG731 on the falling edge of its SCLK. The update
of each switch condition takes place automatically after the eighth
SCLK falling edge, regardless of the frame sync condition.
Communication between two devices at a given clock speed is
possible when the following specs are compatible: frame sync
delay and frame sync setup and hold, data delay and data setup
and hold, and SCLK width. The ADG725/ADG31 expects a
t4 (SYNC falling edge to SCLK falling edge set-up time) of 13 ns
minimum. Consult the ADSP-21xx User Manual for information
on clock and frame sync frequencies for the SPORT Register.
MC68HC11 Interface to ADG725/ADG731
Figure 7 shows an example of a serial interface between the
ADG725/ADG731 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the mux, while the MOSI
output drives the serial data line, DIN. SYNC is driven from
one of the port lines, in this case PC7. The 68HC11 is configured for Master Mode: MSTR = 1, CPOL = 0, and CPHA = 1.
When data is transferred to the part, PC7 is taken low, and data
is transmitted MSB first. Data appearing on the MOSI output is
valid on the falling edge of SCK.
PC7
SCK
APPLICATION CIRCUITS
ADG725/ADG731 in an Optical Network Control Loop
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
The ADG725/ADG731 can be used in optical network applications that have higher port counts and greater multiplexing
requirements. The ADG725/ADG731 are well suited to these
applications because they allow a single control circuit to connect a higher number of channels without increasing board size
and design complexity.
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 0111, 8-Bit Data-Word
SYNC
In the circuit shown in Figure 8, the 0 V to 5 V outputs of the
AD5532HS are amplified to a range of 0 V to 180 V and then
used to control actuators that determine the position of MEMS
mirrors in an optical switch. The exact position of each mirror is
measured using sensors. The sensor readings are muxed using
the ADG731, a 32-channel switch, and fed back to a singlechannel 14-bit ADC (AD7894).
ADG725/ADG731
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 5. ADSP-2191M to ADG725/ADG731 Interface
The control loop is driven by an ADSP-2191L, a 32-bit DSP
with an SPI compatible SPORT interface. It writes data to the
DAC, controls the multiplexer, and reads data from the ADC
via a 3-wire serial interface.
8051 to ADG725/ADG731 Interface
A serial interface between the ADG725/ADG731 and the 8051
is shown in Figure 6. TXD of the 8051 drives SCLK of the
ADG725/ADG731, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
1
32
When data is to be transmitted to the switch, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result, no
glue logic is required between the ADG725/ADG731 and
microcontroller interface.
1
MEMS
MIRROR
ARRAY
.........
AD5532HS
.........
The 8051 provides the LSB of its SBUF Register as the first bit
in the data stream. The user will have to ensure that the data in
the SBUF Register is arranged correctly as the switch expects
MSB first.
32
SENSORS
SCLK
SCLK
Figure 7. MC68HC11 Interface to ADG725/ADG731
INVTFS = 1, Active Low Frame Signal
DT
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
TFSW = 1, Alternate Framing
ADSP-2191M*
ADG725/ADG731
MOSI
The SPORT Control Register should be set up as follows:
TFS
SYNC
MC68HC11*
ADG731
AD7894
ADSP-2191M
Figure 8. Optical Network Control Loop
P3.3
80C51/80L51*
SYNC
ADG725/ADG731
RXD
DIN
TXD
SCLK
Expand the Number of Selectable Serial Devices Using the
ADG725/ADG731
The SYNC pin of the ADG725/ADG731 can be used to select
one of a number of multiplexers. All devices receive the same
serial clock and serial data, but only one device will receive the
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. 8051 to ADG725/ADG731 Interface
–14–
REV. A
ADG725/ADG731
SYNC signal at any one time. The mux addressed will be determined by the decoder. There will be some digital feedthrough
from the digital input lines. Using a burst clock will minimize the
effects of digital feedthrough on the analog signal channels.
Figure 9 shows a typical circuit.
SCLK
SYNC
DIN
DIN
VDD
ENABLE
CODED
ADDRESS
D
SCLK
EN
DECODER
ADG725/
ADG731
SYNC
DIN
ADG725/
ADG731
D
SCLK
DGND
OTHER SPI
DEVICE
SYNC
DIN
D
SCLK
OTHER SPI
DEVICE
SYNC
DIN
D
SCLK
Figure 9. Addressing Multiple ADG725/ADG731s
Using a Decoder
REV. A
–15–
ADG725/ADG731
OUTLINE DIMENSIONS
48-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-48)
7.00
BSC SQ
0.30
0.23
0.18
0.60 MAX
0.60 MAX
37
0.20
REF
12 MAX
5.25
5.10 SQ
4.95
BOTTOM
VIEW
0.50
0.40
0.30
1.00
0.90
0.80
1
6.75
BSC SQ
TOP
VIEW
PIN 1
INDICATOR
48
36
PIN 1
INDICATOR
C02766–0–6/03(A)
Dimensions shown in millimeters
25
24
12
13
5.50
REF
0.80 MAX
0.65 NOM
0.05 MAX
0.02 NOM
0.50 BSC
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
48
36
1
SEATING
PLANE
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.08 MAX
0.15 MAX
0.05 MIN
0
MIN
1.05
1.00
0.95
25
12
13
24
0.50
BSC
0.27
0.22
0.17
0.20
0.09
7
0
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Revision History
Location
Page
6/03—Data Sheet changed from REV. 0 to REV. A.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Test Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
–16–
REV. A