Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 16-pin DIP A merged combination of bipolar and MOS technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. Typical applications include driving multiplexed LED displays or incandescent lamps. The A6821 has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The CMOS inputs are compatible with standard CMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. Package LW 16-pin Wide Body SOIC The A6821SA is furnished in a standard 16-pin plastic DIP. The A6821EA is a 16-pin plastic DIP, capable of operation from -40°C to +85°C. The A6821SLW is a 16-lead wide-body SOIC, for surfacemount applications. These devices are lead (Pb) free, with 100% matte tin plated leadframes. FEATURES ABSOLUTE MAXIMUM RATINGS Output Voltage, VOUT .........................................50 V Logic Supply Voltage, VDD...................................7 V Input Voltage Range, VIN ..............–0.3 V to VDD +0.3 V Continuous Output Current (each output), IOUT ... 500 mA Package Power Dissipation, PD A6821SA/A6821EA..................................2.1 W A6821SLW............................................... 1.5 W Operating Temperature Range Ambient Temperature, TA ............–20°C to +85°C Storage Temperature, TS ..........–55°C to +150°C 3.3 V to 5 V logic supply range Power on reset (POR) Schmitt trigger inputs for improved noise immunity To 10 MHz data input rate Low-power CMOS logic and latches CMOS, TTL compatible High-voltage current-sink outputs –40°C operation available Internal pull-up/pull down resistors APPLICATIONS Multiplexed LED displays Incandescent lamps Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. Use the following complete part numbers when ordering: Part Number A6821SA-T A6821EA-T A6821SLW-T Package 16-pin DIP 16-pin DIP 16-pin wide body SOIC Ambient –20ºC to +85ºC –40ºC to +85ºC –20ºC to +85ºC Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Functional Block Diagram C LOC K LOG IC S UP P LY V DD S E R IAL DAT A IN S E R IAL DAT A OUT S E R IAL-P AR ALLE L S HIF T R E G IS T E R LOG IC G R OUND S T R OB E LAT C HE S OUT P UT E NAB LE (AC T IV E LOW) MOS B IP OLAR P OWE R G R OUND S UB OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 Typical Input Circuits Typical Output Driver VDD OUT STROBE OUTPUT ENABLE 7.2 k Ω 3 kΩ SUB VDD CLOCK SERIAL DATA IN www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Min. Typ. Typ. Max. Units VOUT = 50 V – – 10 – – 10 μA IOUT = 100 mA – – 1.1 – – 1.1 V IOUT = 200 mA – – 1.3 – – 1.3 V IOUT = 350 mA – – 1.6 – – 1.6 V Symbol Output Leakage Current ICEX Collector–Emitter Saturation Voltage VCE(SAT) Input Voltage Input Resistance Test Conditions Maximum Clock Frequency2 2.2 – – 3.3 – – V VIN(0) – – 1.1 – – 1.7 V kΩ 50 – – 50 – – VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V fc 10 – – 10 – – MHz IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA IDD(0) All outputs off, OE = H, ST = H, P1 through P8 = L – – 100 – – 100 μA tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tf VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tr VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs IOUT = ±200 μA – 50 – – 50 – ns Logic Supply Current Output Enable-to-Output Delay Strobe-to-Output Delay Output Fall Time Output Rise Time Clock-to-Serial Data Out Delay Max. Min. VIN(1) RIN Serial Data Output Voltage Vdd = 5 V tp(CH-SQX) 1Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin. 2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. Truth Table Serial Data Clock Input Input Shift Register Contents I1 I2 I3 ... I8 Serial Data Output H H R1 R2 ... R7 R7 L L R1 R2 ... R7 R7 X R1 R2 R3 ... R8 R8 X X X ... P1 P2 P3 ... L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State X X P8 P8 Latch Contents Strobe Input I1 I2 Output Contents I1 I2 I3 ... I8 ... I8 L R1 R2 R3 ... R8 H P1 P2 P3 ... P8 L P 1 P2 P3 ... P8 X X H H X I3 Output Enable Input X ... H H ... H R = Previous State OE = Output Enable ST = Strobe www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% t p(CH-SQX) SERIAL DATA OUT DATA 50% D 50% STROBE OUTPUT ENABLE E LOW = ALL OUTP UTS E NABLE D tp(STH-QH) tp(STH-QL) 90% DATA OUT N 10% HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D) OUTPUT ENABLE 50% t en(BQ) tr tf t dis(BQ) OUT N 10% Key Description A Data Active Time Before Clock Pulse (Data Set-Up Time) B DATA 90% 50% Symbol tsu(D) Time (ns) Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50 NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (POR). Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. 25 Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF). The information stored in the latches or shift register is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Maximum Allowable Duty Cycle, IOUT = 200 mA, VDD = 5 V Number of Outputs ON A mbient T emperature 40 °C 50 °C 60 °C 25 °C 70 °C A6821SA/A6821EA 8 7 6 5 4 3 2 1 90% 100% 100% 100% 100% 100% 100% 100% 79% 90% 100% 100% 100% 100% 100% 100% 72% 82% 96% 100% 100% 100% 100% 100% 65% 74% 86% 100% 100% 100% 100% 100% 57% 65% 76% 91% 100% 100% 100% 100% 67% 77% 90% 100% 100% 100% 100% 100% 59% 68% 79% 95% 100% 100% 100% 100% 54% 62% 72% 86% 100% 100% 100% 100% 49% 56% 65% 78% 98% 100% 100% 100% 43% 49% 57% 68% 86% 100% 100% 100% A6821SLW 8 7 6 5 4 3 2 1 Terminal List Table Name Description Pin CLK Clock 1 VDD Serial Data In 2 Logic Ground* 3 Logic Supply 4 Serial Data Out 5 ST Strobe 6 OE Output Enable (active low) 7 SUB Power Ground* 8 OUT8 Serial Data Output 9 OUT7 Serial Data Output 10 OUT6 Serial Data Output 11 OUT5 Serial Data Output 12 OUT4 Serial Data Output 13 OUT3 Serial Data Output 14 OUT2 Serial Data Output 15 OUT1 Serial Data Output 16 * There is an indeterminate resistance between logic ground and power ground. For proper operation, these terminals must be externally connected together. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 16-pin DIP Package LW 16-pin Wide Body SOIC 16 OUT 1 2 15 OUT 2 LOG IC G R OUND 3 14 OUT 3 OUT 4 LOG IC S UP P LY 4 13 OUT 4 12 OUT 5 S E R IAL DAT A OUT 5 12 OUT 5 ST 11 OUT 6 S T R OB E 6 ST 11 OUT 6 OE 10 OUT 7 OUT P UT E NAB LE 7 OE 10 OUT 7 9 OUT 8 P OWE R G R OUND 8 9 OUT 8 C LOC K 1 2 15 OUT 2 S E R IAL DAT A IN LOGIC GROUND 3 14 OUT 3 LOGIC SUPPLY 4 13 SERIAL DATA OUT 5 STROBE 6 OUTPUT ENABLE 7 POWER GROUND 8 SUB LATCHES VDD SHIFT REGISTER SERIAL DATA IN CLK C LK V DD LAT C HE S OUT 1 1 S HIF T R E G IS TE R 16 CLOCK S UB www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 16-pin DIP Dimensions in Inches (controlling dimensions) 0.014 0.008 9 16 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 0.775 0.735 8 0.005 BSC MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-16A in Dimensions in Millimeters (for reference only) 0.355 0.204 9 16 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 19.68 18.67 8 0.13 BSC MIN 5.33 MAX 0.39 3.81 2.93 MIN 0.558 0.356 Dwg. MA-001-16A mm NOTES: 1. Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor’s option within limits shown. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package LW 16-pin Wide Body SOIC Dimensions in Inches (for reference only) 16 9 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.4133 0.3977 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-16A in Dimensions in Millimeters (controlling dimensions) 16 9 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 10.50 10.10 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-16A mm NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2004, 2005 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9