Hynix GMS82516Q 8-bit single-chip microcontroller Datasheet

HYUNDAI MICRO ELECTRONICS
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS82512
GMS82516
GMS82524
User’s Manual (Ver. 1.00)
MicroElectronics
Semiconductor Group of Hyundai Electronics Industrial Co., Ltd.
Version 1.00
Published by
MCU Application Team
2000 HYUNDAI MicroElectronics All right reserved.
Additional information of this manual may be served by HYUNDAI MicroElectronics offices in Korea or Distributors and
Representatives listed at address directory.
HYUNDAI MicroElectronics reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, HYUNDAI Micro Electronics is
in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HYUNDAI MicroElectronics
GMS82512/16/24
Table of Contents
1. OVERVIEW ...........................................1
12. ANALOG DIGITAL CONVERTER ....43
Description .........................................................1
Features .............................................................1
Development Tools ............................................2
Ordering Information ..........................................2
13. BUZZER FUNCTION ........................45
14. INTERRUPTS ...................................47
3. PIN ASSIGNMENT ...............................4
Interrupt Sequence .......................................... 49
BRK Interrupt .................................................. 50
Multi Interrupt .................................................. 51
External Interrupt ............................................. 51
4. PACKAGE DIAGRAM .............................. 5
15. WATCHDOG TIMER ........................54
5. PIN FUNCTION .....................................6
16. POWER DOWN OPERATION ..........56
6. PORT STRUCTURES ...........................8
STOP Mode .................................................... 56
Minimizing Current Consumption .................... 57
2. BLOCK DIAGRAM ................................3
7. ELECTRICAL CHARACTERISTICS ...10
Absolute Maximum Ratings .............................10
Recommended Operating Conditions ..............10
A/D Converter Characteristics .........................10
DC Electrical Characteristics ...........................11
AC Characteristics ...........................................12
Typical Characteristic Curves ..........................13
8. MEMORY ORGANIZATION ................15
17. OSCILLATOR CIRCUIT ....................59
18. RESET ..............................................60
External Reset Input ........................................ 60
Watchdog Timer Reset ................................... 60
19. POWER FAIL PROCESSOR ............61
20. OTP PROGRAMMING ......................63
How to Program .............................................. 63
Pin Function .................................................... 63
Programming Specification ............................. 65
Registers ..........................................................15
Program Memory .............................................18
Data Memory ...................................................21
Addressing Mode .............................................24
A. CONTROL REGISTER LIST ................. i
9. I/O PORTS ..........................................28
B. SOFTWARE EXAMPLE ....................... ii
10. BASIC INTERVAL TIMER .................31
11. TIMER/EVENT COUNTER ...............33
8-bit Timer / Counter Mode ..............................35
16-bit Timer / Counter Mode ............................39
8-bit Capture Mode ..........................................40
16-bit Capture Mode ........................................41
7-segment LED display .....................................ii
C. INSTRUCTION ................................... vii
Terminology List ............................................... vii
Instruction Map ................................................ viii
Alphabetic order table of instruction ..................ix
Instruction Table by Function .......................... xiv
D. MASK ORDER SHEET ......................... xx
FEB. 2000 Ver 1.00
1
HYUNDAI MicroElectronics
GMS82512/16/24
GMS82512/16/24
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH A/D CONVERTER
1. OVERVIEW
1.1 Description
The GMS82512/16/24 are advanced CMOS 8-bit microcontrollers with 12K/16K/24K bytes of ROM. The device is one of
GMS800 family. This device using the GMS800 family CPU includes several peripheral functions such as Timer, A/D converter, Programmable buzzer driver, etc. The RAM, ROM, and I/O are placed on the same memory map in addition to simple
instruction set.
Device name
ROM Size
RAM Size
OTP
GMS82512
12K bytes
448 bytes
GMS82524T
GMS82516
16K bytes
448 bytes
GMS82524T
GMS82524
24K bytes
448 bytes
GMS82524T
Package
42SDIP, 44QFP
1.2 Features
• 12K/16K/24K Bytes On-chip Program Memory
• 448 Bytes of On-chip Data RAM
(Included stack memory)
• Minimum Instruction Execution Time
0.5µ
µs at 8MHz
• One 8-bit Basic Interval Timer
• Four 8-bit Timer/Event counter
or Two 16-bit Timer/Event counter
• One 6-bit Watchdog timer
• Four channel 8-bit A/D converter
• Four External Interrupt input ports
• Buzzer Driving port
- 500Hz ~ 250kHz@8MHz
• 35 I/O Ports
FEB. 2000 Ver 1.00
• Eleven Interrupt sources
- Basic Interval Timer: 1
- External input: 4
- Timer/Event counter: 4
- ADC: 1
- WDT: 1
• Built in Noise Immunity Circuit
- Noise filter
- Power fail processor
• Power Down Mode
- STOP mode
• 2.2V to 5.5V Wide Operating Range
• 1~10MHz Wide Operating Frequency
• 42SDIP, 44QFP package types
• Available 24K bytes OTP version
1
GMS82512/16/24
HYUNDAI MicroElectronics
1.3 Development Tools
The GMS825xx is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Jr.TM and OTP
programmers. There are third different type programmers
such as emulator add-on board type, single type, gang type.
For mode detail, Refer to “20. OTP PROGRAMMING” on
page 63. Macro assembler operates under the MS-Windows 95/98TM.
Please contact sales part of HYUNDAI MicroElectronics.
1.4 Ordering Information
Device name
ROM Size
RAM size
Package
Mask version
GMS82512 K
GMS82512 Q
GMS82516 K
GMS82516 Q
GMS82524 K
GMS82524 Q
12K bytes
12K bytes
16K bytes
16K bytes
24K bytes
24K bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
42SDIP
44QFP
42SDIP
44QFP
42SDIP
44QFP
OTP version
GMS82524T K
GMS82524T Q
24K bytes OTP
24K bytes OTP
448 bytes
448 bytes
42SDIP
44QFP
2
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
2. BLOCK DIAGRAM
AVDD
ADC Power
Supply
PSW
A
ALU
X
Y
R00~R07
R20~R27
R30~R37
R0
R2
R3
Stack Pointer
PC
Data Memory
(448 bytes)
Program
Memory
Interrupt Controller
Data Table
System controller
System
Clock Controller
Timing generator
8-bit Basic
Interval
Timer
Watchdog
Timer
8-bit
Timer/
Counter
PC
8-bit
ADC
Clock Generator
VDD
VSS
XIN
XOUT
RESET
TEST
R4
Power
Supply
FEB. 2000 Ver 1.00
R40 / INT0
R41 / INT1
R42 / INT2
R43 / INT3
R44 / EC0
Buzzer
Driver
R5
R54 / WDTO
R55 / BUZ
R6
R64 / AN4
R65 / AN5
R66 / AN6
R67 / AN7
3
GMS82512/16/24
HYUNDAI MicroElectronics
3. PIN ASSIGNMENT
42SDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
GMS82512/16/24
AN7
AN6
AN5
AN4
BUZ
WDTO
EC0
INT3
INT2
INT1
INT0
R30
VDD
TEST
AVDD
R67
R66
R65
R64
R55
R54
R44
R43
R42
R41
R40
RESET
XIN
XOUT
VSS
R27
R26
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R31
R32
R33
R34
R35
R36
R37
R00
R01
R02
R03
R04
R05
R06
R07
R20
R21
R22
R23
R24
R25
33
32
31
30
29
28
27
26
25
24
23
R37
R00
R01
R02
R03
R04
R05
R06
R07
N.C.*
R20
44QFP
(Top View)
34
35
36
37
38
39
40
41
42
43
44
GMS82512/16/24
22
21
20
19
18
17
16
15
14
13
12
R21
R22
R23
R24
R25
R26
R27
VSS
XOUT
XIN
RESET
AN6
AN5
AN4
R66
R65
R64
N.C.*
BUZ R55
WDTO R54
EC0 R44
INT3 R43
INT2 R42
INT1 R41
INT0 R40
1
2
3
4
5
6
7
8
9
10
11
R36
R35
R34
R33
R32
R31
R30
VDD
TEST
AVDD
R67
AN7
N .C . * : N o C onnection
4
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
4. PACKAGE DIAGRAM
42SDIP
UNIT: INCH
0.600 Typ.
min. 0.015
0.190 max.
1.465
1.455
0.140
0.120
0.070 Typ.
0.045
0.035
0.022
0.016
0.545
0.535
0.012
0.008
0-15°
44QFP
13.45
12.95
10.10
9.90
0.23
0.13
2.10
1.95
13.45
12.95
10.10
9.90
UNIT: MM
0-7°
0.25
0.10
SEE DETAIL “A”
2.35 max.
0.45
0.30
FEB. 2000 Ver 1.00
0.80 Typ.
1.03
0.73
1.60
Typ.
DETAIL “A”
5
GMS82512/16/24
HYUNDAI MicroElectronics
5. PIN FUNCTION
VSS: Circuit ground.
R54~R55: R5 is an 2-bit CMOS bidirectional I/O port. R5
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
TEST: Used for Test Mode. For normal operation, it
should be connected to VDD.
In addition, R5 serves the functions of the various following special features.
VDD: Supply voltage.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
Port pin
R54
R55
Alternate function
WDTO (Watchdog Timer output)
BUZ (Buzzer driver output)
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register, can be
used as outputs or inputs.
R64~R67: R6 is an 4-bit CMOS bidirectional I/O port. R6
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R20~R27: R2 is an 8-bit CMOS bidirectional I/O port. R2
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
In addition, R6 is shared with the ADC input.
R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R40~R44: R4 is an 5-bit CMOS bidirectional I/O port. R4
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
In addition, R4 serves the functions of the various following special features.
Port pin
R40
R41
R42
R43
R44
6
Port pin
R64
R66
R66
R67
Alternate function
AN4 (Analog Input 4)
AN5 (Analog Input 5)
AN6 (Analog Input 6)
AN7 (Analog Input 7)
AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other
than digital power source.
Alternate function
INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
INT3 (External interrupt 3)
EC0 (Event counter input 0)
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
Function
PIN NAME
In/Out
Basic
Alternate
VDD
-
Supply voltage
VSS
-
Circuit ground
TEST
I
Controls test mode of the chip,
For normal operation, it should be connected at VDD.
RESET
I
Reset signal input
XIN
I
Oscillation input
XOUT
O
Oscillation output
R00~R07
I/O
8-bit general I/O ports
R20~R27
I/O
8-bit general I/O ports
R30~R33
I/O(I)
8-bit general I/O ports
R34~R37
I/O
8-bit general I/O ports
R40 (INT0)
I/O (I)
External interrupt 0 input
R41 (INT1)
I/O (I)
External interrupt 1 input
R42 (INT2)
I/O (I)
R43 (INT3)
I/O (I)
External interrupt 3 input
R44 (EC0)
I/O (I)
Timer/Counter 0 external input
R54 (WDTO)
I/O (O)
R55 (BUZ)
I/O (O)
R64~R67 (AN4~AN7)
I/O (I)
AVDD
-
8-bit general I/O ports
8-bit general I/O ports
8-bit general I/O ports
External interrupt 2 input
Watchdog timer overflow output
Buzzer driving output
Analog voltage input
Supply voltage input pin for ADC
Table 5-1 Port Function Description
FEB. 2000 Ver 1.00
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GMS82512/16/24
HYUNDAI MicroElectronics
6. PORT STRUCTURES
R00~R07, R20~R27, R30~37
R64/AN7 ~ R67/AN7
VDD
VDD
Data Reg.
Pin
Dir.
Reg.
Data Bus
Data Bus
Data Reg.
Direction
Reg.
Pin
VSS
VSS
MUX
MUX
Rd
Rd
Digital enable
Channel Sel.
A/D enable
To A/D converter
R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/
EC0
XIN, XOUT
PMR Selection
VDD
Data Bus
Data Reg.
VDD
Direction
Reg.
Pin
XIN
VSS
MUX
VSS
VSS
XOUT
Rd
EX) INT0
Alternate Function
Stop
R54/WDTO, R55/BUZ
Selection
RESET
VDD
Secondary function
MUX
VDD
Pin
Data Reg.
Data Bus
RESET
Direction
Reg.
VSS
VSS
MUX
Rd
8
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
TEST
VDD
OTP version: disconnected
Mask version: connected
TEST
VSS
FEB. 2000 Ver 1.00
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GMS82512/16/24
HYUNDAI MicroElectronics
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ............................................. -0.3 to +7.0 V
Maximum current (ΣIOL) ...................................... 100 mA
Storage Temperature .................................. -40 to +125 °C
Maximum current (ΣIOH)........................................ 50 mA
Voltage on any pin with respect to Ground (VSS)
..................................................................-0.3 to VDD+0.3
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum current out of VSS pin .......................... 150 mA
Maximum current into V DD pin .............................. 80 mA
Maximum current sunk by (I OL per I/O Pin) .......... 20 mA
Maximum output current sourced by (IOH per I/O Pin)
................................................................................... 8 mA
7.2 Recommended Operating Conditions
Specifications
Parameter
Supply Voltage
Operating Frequency
Operating Temperature
Symbol
Condition
VDD
fXIN=1 ~ 10 MHz
fXIN=1 ~ 8 MHz
fXIN=1 ~ 4 MHz
fXIN
VDD=4.5~5.5V
VDD=2.7~5.5V
VDD=2.2~5.5V
TOPR
Unit
Normal Version
Temperature Extention Version
Min.
Max.
4.5
2.7
2.2
5.5
5.5
5.5
V
1
1
1
10
8
4
MHz
-20
-40
85
85
°C
7.3 A/D Converter Characteristics
(TA=25°C, VSS=0V, VDD=5.12V@fXIN=8MHz, VDD=3.072V@fXIN=4MHz)
Specifications
Parameter
Max.
Symbol
Min.
Typ.1
Unit
fXIN=4MHz
fXIN=8MHz
Analog Input Voltage Range
VAIN
VSS
-
AVDD
AVDD
V
Non-linearity Error
NNLE
-
±1.0
±1.5
±1.5
LSB
Differential Non-linearity Error
NDNLE
-
±1.0
±1.5
±1.5
LSB
Zero Offset Error
NZOE
-
±0.5
±1.5
±1.5
LSB
Full Scale Error
NFSE
-
±0.35
±0.5
±0.5
LSB
Gain Error
NGE
-
±1.0
±1.5
±1.5
LSB
Overall Accuracy
NACC
-
±1.0
±1.5
±1.5
LSB
AVDD Input Current
IREF
-
0.5
1.0
1.0
mA
TCONV
-
-
40
20
µs
Conversion Time
10
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
Specifications
Parameter
Max.
Symbol
AVDD
Analog Power Supply Input Range
Min.
Typ.1
0.9VDD
VDD
fXIN=4MHz
Unit
fXIN=8MHz
1.1VDD
V
1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
7.4 DC Electrical Characteristics
(TA=-20~85°C, VDD=2.7~5.5V, Ta= -20~85°C, fXIN=8MHz, VSS=0V),
Specifications
Parameter
Input High Voltage
Symbol
VIH1
VIH2
Input Low Voltage
VIL1
VIL2
Condition
VDD=4.5
VDD=2.7
VDD=4.5
VDD=2.7
Unit
Min.
Typ.1
Max.
XIN, RESET,
R4, R5, R6
0.8VDD
-
VDD+0.3
R0, R2, R3
0.7VDD
-
VDD+0.3
XIN, RESET,
R4, R5, R6
-
0.2VDD
R0, R2, R3
-
0.3VDD
VDD-1.0
-
-
V
-
-
1.0
V
1.1VPFD
V
V
V
Output High Voltage
VOH
VDD=4.5
R0,R2,R3,R4,R5
VDD=2.7
R6
IOH1=-2mA
Output Low Voltage
VOL
VDD=4.5
VDD=2.7
IOL1=5mA
Power Fail Detect
Voltage
VPFD
VPFD=3.0V
@ TA=25°C
VPFD=2.4V
Input High
Leakage Current
IIH1
VIN=VDD
All input pins
-5.0
-
5.0
µA
Input Low
Leakage Current
IIL
VIN=VSS
All input pins
-5.0
-
5.0
µA
RESET, EC0, SIN,
SCLK, INT0~INT3
0.3
0.8
V
8
20
mA
4
10
mA
1
10
µA
Hysteresis
Power Current
VT+, VTIDD1
f XIN=8M H z
IDD2
f XIN=4M H z
ISTOP
R0,R2,R3,R4,R5
R6
0.9VPFD
All input = V SS
C rystal O scillator,
C L1 =C L2 =30pF@ 8M H z
-
All input = V SS
-
1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FEB. 2000 Ver 1.00
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HYUNDAI MicroElectronics
7.5 AC Characteristics
(TA=-20~+85°C, VDD=5V±10%, VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
Operating Frequency
fXIN
XIN
1.0
-
10.0
MHz
Oscillation Stabilizing
Time
tST
XIN, XOUT
-
-
20
ms
External Clock Pulse
Width
tCPW
XIN
40
-
-
ns
External Clock Transition Time
tRCP,tFCP
XIN
-
-
20
ns
Interrupt Pulse Width
tIW
INT0, INT1, INT2, INT3
2
-
-
tSYS
RESET Input Width
tRST
RESET
8
-
-
tSYS
Event Counter Input
Pulse Width
tECW
EC0
2
-
-
tSYS
tREC,tFEC
EC0
-
-
20
ns
Event Counter Transition Time
tSYS = 1/fXIN
tCPW
tCPW
VDD-0.5V
XIN
0.5V
tRCP
tIW
INT0~INT3
tFCP
tIW
0.8VDD
0.2VDD
tRST
RESET
0.2VDD
tECW
tECW
0.8VDD
EC0
0.2VDD
tREC
tFEC
Figure 7-1 Timing Chart
12
FEB. 2000 Ver 1.00
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GMS82512/16/24
7.6 Typical Characteristic Curves
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
IOH−VOH
IOH
(mA) VDD=4.5V
Ta=25°C
-12
R0~R6 pins
IOH−VOH
-9
-9
-6
-6
-3
-3
0
0
0.3
0.6
0.9
IOL−VOL1
1.2 1.5 (V)
VDD-VOH
R0~R6 pins
IOL
(mA) VDD=4.5V
Ta=25°C
20
0.3
10
10
5
5
0.2
4
0.4
VDD−VIH1
0.6
0.8
VOL
1.0 (V)
0.2
VIH2
(V)
R0~R6 pins
0.4
VDD−VIH2
0.6
0.8
VOL
1.0 (V)
R0, R2, R3 pins
fXIN=8MHz
Ta=25°C
4
3
3
2
2
1
1
0
2
1.2 1.5 (V)
VDD-VOH
0
XIN, RESET,
R4, R5, R6 pins
fXIN=8MHz
Ta=25°C
0.9
IOL−VOL2
15
0
0.6
IOL
(mA) VDD=3.0V
Ta=25°C
20
15
VIH1
(V)
R0~R6 pins
IOH
(mA) VDD=3.0V
Ta=25°C
-12
3
4
FEB. 2000 Ver 1.00
5
VDD
6 (V)
0
1
2
3
4
5
VDD
6 (V)
13
GMS82512/16/24
VIL2
(V)
4
HYUNDAI MicroElectronics
XIN, RESET,
R4, R5, R6 pins
VDD−VIL1
fXIN=8MHz
Ta=25°C
VIL2
(V)
3
2
2
1
1
0
3
IDD−VDD
IDD
(mA)
4
5
VDD
6 (V)
0
1
2
3
4
ISTOP−VDD
Normal Operation
5
VDD
6 (V)
Operating Area
Stop Mode
fXIN
(MHz) Ta= -20~85°C
IDD
(µA)
Ta=25°C
20
0.4
15
0.3
10
0.2
5
R0, R2, R3 pins
fXIN=8MHz
Ta=25°C
4
3
2
VDD−VIL2
fXIN = 8MHz
10
8
0.1
85°C
6
25°C
-20°C
4
2
4MHz
0
2
14
3
4
5
VDD
6 (V)
0
2
3
4
5
VDD
6 (V)
0
2
3
4
5
VDD
6 (V)
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
8. MEMORY ORGANIZATION
The GMS82512/16/24 has separate address spaces for Program memory and Data Memory. Program memory can
only be read, not written to. It can be up to 24K bytes of
Program memory. Data memory can be read and written to
up to 448 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
PCH
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 100H to
1FFH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FEH” is
used.
Bit 15
Stack Address (100H ~ 1FEH)
8 7
Bit 0
01H
SP
00H~FEH
Hardware fixed
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
Y
Y
A
A
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX
#0FEH
TXSP
; SP ← FEH
Address 01FFH can not be used as stack. Don not use
1FFH, or malfunction would be occurred.
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
Generally, SP is automatically updated when a subroutine
FEB. 2000 Ver 1.00
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or not borrow from the ALU of
CPU after an arithmetic operation and is also changed by
the Shift Instruction or Rotate Instruction.
15
GMS82512/16/24
HYUNDAI MicroElectronics
[Zero flag Z]
or data transfer is “0” and is cleared by any other result.
This flag is set when the result of an arithmetic operation
PSW
MSB
N V G B H
NEGATIVE FLAG
OVERFLOW FLAG
SELECT DIRECT PAGE
when G=1, page is selected to “page 1”
BRK FLAG
I
Z
LSB
C RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
16
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is assigned 100 H to 1FF H . It is set by
SETG instruction and cleared by CLRG.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH ) or -128(80H ). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
At execution of
a CALL/TCALL/PCALL
01FE
Push
down
01FE
PCH
01FD
PCL
01FC
01FC
PSW
01FB
01FB
01FD
PCH
PCL
At execution
of RET instruction
At acceptance
of interrupt
Push
down
01FE
PCH
01FD
PCL
At execution
of RET instruction
01FE
PCH
01FD
PCL
01FC
01FC
PSW
01FB
01FB
Pop
up
SP before
execution
01FE
01FE
01FC
01FB
SP after
execution
01FC
01FB
01FE
01FE
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
01FE
A
01FD
Push
down
Pop
up
At execution
of POP instruction
POP A (X,Y,PSW)
01FE
A
01FD
01FC
01FC
01FB
01FB
Pop
up
0100H
Stack
depth
01FEH
SP before
execution
01FE
01FD
SP after
execution
01FD
01FE
Figure 8-4 Stack Operation
FEB. 2000 Ver 1.00
17
GMS82512/16/24
HYUNDAI MicroElectronics
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 24K bytes program memory
space only physically implemented. Accessing a location
above FFFFH will cause a wrap-around to 0000H.
Figure 8-5, shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6.
As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains
the user program.
A000H
TCALL area
Interrupt
Vector Area
GMS82524, 24K ROM
GMS82516, 16K ROM
GMS82512, 12K ROM
FEFFH
FF00H
PCALL area
D000H
FFFFH
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
18
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-7.
Example: Usage of TCALL
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
C000H
FFC0H
FFDFH
FFE0H
it is more useful to save program byte length.
Address
Vector Area Memory
0FFE0H
-
E2
-
E4
-
E6
Basic Interval Timer
E8
Watchdog Timer Interrupt
EA
A/D Converter
-
EC
Timer/Counter
- 3 Interrupt
EE
Timer/Counter
- 2 Interrupt
F0
Timer/Counter 1 Interrupt
F2
Timer/Counter 0 Interrupt
F4
External Interrupt 3
F6
External Interrupt 2
F8
External Interrupt 1
FA
External Interrupt 0
FC
-
FE
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 8-6 Interrupt Vector Area
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
Address
0FF00H
GMS82512/16/24
PCALL Area Memory
Address
PCALL Area
(256 Bytes)
0FFC0H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
0FFFFH
Program Memory
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→
→ rel
TCALL→
→n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
01001010
35
~
~
~
~
~
~
0D125H
➊
~
~
NEXT
Reverse
PC: 11111111 11010110
FH
FH
DH 6H
0FF00H
0FF35H
NEXT
0FFFFH
FEB. 2000 Ver 1.00
➌
0FF00H
0FFD6H
25
0FFD7H
D1
➋
0FFFFH
19
GMS82512/16/24
HYUNDAI MicroElectronics
Example: The usage software example of Vector address for GMS82524.
;
;
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
BIT_TIMER
WD_TIMER
ADC
TIMER3
TIMER2
TIMER1
TIMER0
INT3
INT2
INT1
INT0
NOT_USED
RESET
;
;
;
;
;
;
;
;
;
;
;
;
;
ORG
ORG
ORG
0A000H
0C000H
0D000H
; 24K ROM Start address
; 16K ROM Start address
; 12K ROM Start address
Basic Interval Timer
Watchdog Timer
ADC
Timer-3
Timer-2
Timer-1
Timer-0
Int.3
Int.2
Int.1
Int.0
Reset
;*******************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET: DI
;Disable All Interrupts
CLRG
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX #0C0H
BNE
RAM_CLR
;
LDX
#0FEH
;Stack Pointer Initialize
TXSP
;
LDM
R0, #0
;Normal Port 0
LDM
R0DD,#82H
;Normal Port Direction
:
:
:
LDM
TDR0,#250
;8us x 250 = 2000us
LDM
TM0,#1FH
;Start Timer0, 8us at 8MHz
LDM
IRQH,#0
LDM
IRQL,#0
LDM
IENH,#0C8H ;Enable Timer0, INT0, INT1
LDM
IENL,#0
LDM
IEDS,#55H
;Select falling edge detect on INT pin
LDM
PMR4,#3H
;Set external interrupt pin(INT0, INT1)
EI
;Enable master interrupt
:
:
:
:
:
NOT_USED:NOP
RETI
20
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and LCD memory.
0000H
More detailed informations of each register are explained
in each peripheral section.
User Memory
PAGE0
00BFH
00C0H
00FFH
0100H
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
When “G-flag=0”,
this page is selected
Control
Registers
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”.
Example; To write at CKCTLR
LDM
User Memory
or Stack Area
PAGE1
When “G-flag=1”
01FFH
Figure 8-8 Data Memory Map
User Memory
The GMS825xx has 448 × 8 bits for the user memory
(RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
FEB. 2000 Ver 1.00
CLCTLR,#09H ;Divide ratio(÷32)
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 17.
21
GMS82512/16/24
Address
HYUNDAI MicroElectronics
Register Name
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00C0
R0 port data register
R0
R/W
Undefined
page 28
00C1
R0 port I/O direction register
R0DD
W
00000000
page 28
00C4
R2 port data register
R2
R/W
Undefined
page 28
00C5
R2 port I/O direction register
R2DD
W
00000000
page 28
00C6
R3 port data register
R3
R/W
Undefined
page 28
00C7
R3 port I/O direction register
R3DD
W
00000000
page 28
00C8
R4 port data register
R4
R/W
Undefined
page 29
00C9
R4 port I/O direction register
R4DD
W
- - - 00000
page 29
00CA
R5 port data register
R5
R/W
Undefined
page 30
00CB
R5 port I/O direction register
R5DD
W
- - 00 - - - -
page 30
00CC
R6 port data register
R6
R/W
Undefined
page 30
00CD
R6 port I/O direction register
R6DD
W
0000 - - - -
page 30
00D0
R4 port mode register
PMR4
W
- - - 00000
page 29, page 53
00D1
R5 port mode register
PMR5
W
- - 00 - - - -
page 30, page 45
Basic interval timer mode register
BITR
R
Undefined
page 32
CKCTLR
W
- - 010111
page 32
WDTR
W
- 0111111
page 54
00D3
Clock control register
00E0
Watchdog Timer Register
00E2
Timer mode register 0
TM0
R/W
00000000
page 34
00E3
Timer mode register 2
TM2
R/W
00000000
page 34
Timer 0 data register
TDR0
W
Undefined
page 34
T0
R
Undefined
page 34
TDR1
W
Undefined
page 34
T1
R
Undefined
page 34
TDR2
W
Undefined
page 34
T2
R
Undefined
page 34
TDR3
W
Undefined
page 34
T3
R
Undefined
page 34
00E4
00E5
00E6
00E7
Timer 0 counter register
Timer 1 data register
Timer 1 counter register
Timer 2 data register
Timer 2 counter register
Timer 3 data register
Timer 3 counter register
00E8
A/D converter mode register
ADCM
R/W
- - 000001
page 44
00E9
A/D converter data register
ADR
R
Undefined
page 44
00EC
Buzzer driver register
BUR
W
Undefined
page 45
00F4
Interrupt enable register low
IENL
R/W
000 - - - - -
page 48
00F5
Interrupt request flag register low
IRQL
R/W
000 - - - - -
page 47
00F6
Interrupt enable register high
IENH
R/W
00000000
page 48
00F7
Interrupt request flag register high
IRQH
R/W
00000000
page 47
00F8
External interrupt edge selection register
IEDS
W
00000000
page 53
Table 8-1 Control Registers
22
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
Address
Register Name
GMS82512/16/24
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00F9
Power fail detection register
PFDR
R/W
- - - - 1100
page 61
Table 8-1 Control Registers
W
R/W
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
Registers are controlled by both bit and byte manipulation instruction.
- : this bit location is reserved.
FEB. 2000 Ver 1.00
23
GMS82512/16/24
HYUNDAI MicroElectronics
8.4 Addressing Mode
The GMS800 series MCU uses six addressing modes;
Example: G=1
• Register addressing
E45535
LDM
35H,#55H
• Immediate addressing
• Direct page addressing
• Absolute addressing
data
0135H
• Indexed addressing
➊
• Register-indirect addressing
~
~
0F100H
(1) Register Addressing
data ¨ 55H
~
~
➋
E4
0F101H
55
0F102H
35
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
In this mode, a address is specified within direct page.
Example; G=0
Example:
0435
(3) Direct Page Addressing → dp
ADC
C535
#35H
LDA
;A ←RAM[35H]
35H
MEMORY
35H
04
35
data
➋
A+35H+C → A
~
~
~
~
0E550H
C5
0E551H
35
➊
data → A
When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
24
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
(4) Absolute Addressing → !abs
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
Example; X=15H, G=1
D4
LDA
115H
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
{X}
;ACC←RAM[X].
data
➋
~
~
~
~
Example;
0735F0
ADC
;A ←ROM[0F035H]
!0F035H
data
0F035H
~
~
➋
~
~
0F100H
A+data+C → A
➊
07
0F101H
35
0F102H
F0
address: 0F035
data → A
➊
D4
0E550H
X indexed direct page, auto increment→
→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; G=0, X=35H
DB
LDA
{X}+
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H regardless of G-flag.
983501
INC
;A ←ROM[135H]
!0135H
35H
➋
data
~
~
~
~
data Æ A
➊
36H Æ X
DB
data
135H
~
~
➌
~
~
➋
data+1 → data
0F100H
98
➊
0F101H
35
address: 0135
0F102H
01
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; G=0, X=0F5H
In this mode, a address is specified by the X register.
FEB. 2000 Ver 1.00
25
GMS82512/16/24
C645
LDA
HYUNDAI MicroElectronics
Example; G=0
45H+X
3F35
3AH
data
➌
~
~
➋
~
~
0E550H
C6
0E551H
45
JMP
[35H]
35H
0A
36H
E3
data → A
~
~
~
~
➋
➊
0E30AH
➊
NEXT
jump to
address 0E30AH
45H+0F5H=13AH
~
~
~
~
0FA00H
3F
35
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
Y indexed absolute → !abs+Y
Sets the value of 16-bit absolute address plus Y-register
data as Memory.This addressing mode can specify memory in whole area.
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusX-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10H
1625
ADC
[25H+X]
Example; Y=55H
D500FA
LDA
!0FA00H+Y
35H
05
36H
E0
0E005H
~
~ ➋
~
~
0F100H
D5
0F101H
00
0F102H
FA
~
~
➊
0E005H
0FA00H+55H=0FA55H
~
~
➋
~
~
0FA00H
➊ 25 + X(10) = 35H
data
~
~
16
25
0FA55H
data
➌
data → A
➌ A + data + C → A
Y indexed indirect → [dp]+Y
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, Y=10H
JMP, CALL
26
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
1725
ADC
GMS82512/16/24
Example; G=0
[25H]+Y
1F25E0
25H
05
26H
E0
~
~
0E015H
~
~
0FA00H
➊
0E005H + Y(10)
= 0E015H
0E025H
25
0E026H
E7
~
~
~
~
17
25
[!0C025H]
PROGRAM MEMORY
➋
data
~
~
JMP
➊
0E725H
➌
NEXT
~
~
A + data + C → A
0FA00H
Absolute indirect → [!abs]
~
~
➋
jump to
address 0E30AH
~
~
1F
25
E0
The program jumps to address specified by 16-bit absolute
address.
JMP
FEB. 2000 Ver 1.00
27
GMS82512/16/24
HYUNDAI MicroElectronics
9. I/O PORTS
The GMS825xx has six ports (R0, R2, R3, R4, R5, and
R6).These ports pins may be multiplexed with an alternate
function for the peripheral features on the device.
All pins have data direction registers which can define
these ports as output or input. A “1” in the port direction
register configure the corresponding port pin as output.
Conversely, write “0” to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write “55H” to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1.
All the port direction registers in the GMS825xx have 0
written to them by reset function. On the other hand, its initial status is input.
R2 and R2DD register: R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently
used as an input or an output through the R2DD register
(address 0C5H).
R2 Data Register
R2
R27 R26 R25 R24 R23 R22 R21 R20
Input / Output data
R2 Direction Register
0C0H
R0 data
R0 direction
0C2H
R1 data
0C3H
R1 direction
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
BIT
I O I O I O I O PORT
7 6 5 4 3 2 1 0
I: INPUT PORT
O: OUTPUT PORT
Port Direction
0: Input
1: Output
R3 and R3DD register: R3 is an 8-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can independently
used as an input or an output through the R3DD register
(address 0C7H).
R3 Data Register
R3
R0 Data Register
R0
ADDRESS: 0C0H
RESET VALUE: Undefined
ADDRESS: 0C6H
RESET VALUE: Undefined
R37 R36 R35 R34 R33 R32 R31 R30
Figure 9-1 Example of port I/O assignment
R0 and R0DD register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently
used as an input or an output through the R0DD register
(address 0C1H).
ADDRESS: 0C5H
RESET VALUE: 00H
R2DD
WRITE “55H” TO PORT R0 DIRECTION REGISTER
0C1H
ADDRESS: 0C4H
RESET VALUE: Undefined
Input / Output data
R3 Direction Register
ADDRESS: 0C7H
RESET VALUE: 00H
R3DD
Port Direction
0: Input
1: Output
R07 R06 R05 R04 R03 R02 R01 R00
Input / Output data
R0 Direction Register
ADDRESS: 0C1H
RESET VALUE: 00H
R0DD
Port Direction
0: Input
1: Output
28
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
R4 and R4DD register: R4 is an 5-bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently
used as an input or an output through the R4DD register
(address 0C9H).
ADDRESS: 0C8H
RESET VALUE: Undefined
R4 Data Register
R4
-
-
-
R44 R43 R42 R41 R40
Port Pin
Input / Output data
ADDRESS: 0C9H
RESET VALUE: 00H
R4 Direction Register
-
R4DD
-
-
-
-
4
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
INT3 (External Interrupt 3)
EC0 (External count input to Timer/
Counter 0)
ADDRESS: 0D0H
RESET VALUE: 00H
R4 Port Mode Register
-
R40
R41
R42
R43
R44
Alternate Function
Regardless of the direction register R4DD, PMR4 is selected to use as alternate functions, port pin can be used as a
corresponding alternate features.
Port Direction
0: Input
1: Output
PMR4
In addition, Port R4 is multiplexed with various special
features. The control register PMR4 (address 0D0H) controls the selection of alternate function. After reset, this
value is “0”, port may be used as normal I/O port.
To use alternate function such as external interrupt or external counter input, write “1” in the corresponding bit of
PMR4.
3
2
1
0
0: R40
1: INT0
0: R41
1: INT1
0: R42
1: INT2
0: R43
1: INT3
0: R44
1: EC0
ADDRESS: 0F8H
RESET VALUE: 00H
Edge Selection Register
IEDS
7
6
INT3
5
4
INT2
3
2
1
INT1
0
INT0
External Interrupt Edge Select
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
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HYUNDAI MicroElectronics
R5 and R5DD register: R5 is an 2-bit CMOS bidirectional I/O port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5DD register
(address 0CBH).
ADDRESS: 0CAH
RESET VALUE: Undefined
R5 Data Register
R5
-
-
R55 R54
-
-
-
-
R6 and R6DD register: R6 is an 4-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6DD register
(address 0CDH).
ADDRESS: 0CCH
RESET VALUE: Undefined
R6 Data Register
R6
R67 R66 R65 R64
-
R5DD
-
-
-
-
-
R6DD
PMR5
-
-
ADDRESS: 0D1H
RESET VALUE: --00----B
BUZ W DTO
-
-
-
-
-
-
-
Port Direction
0: Input
1: Output
Port Direction
0: Input
1: Output
R5 Port Mode Register
-
ADDRESS: 0CDH
RESET VALUE: 0000----B
R6 Direction Register
R5 Direction Register
-
Input / Output data
Input / Output data
ADDRESS: 0CBH
RESET VALUE: 00H
-
-
R54/WDTO Selection
0: R54
1: WDTO (Output)
R55/BUZ Selection
0: R55
1: BUZ (Output)
R6DD (address CDH) controls the direction of the R6 pins,
even when they are being used as analog inputs. The user
must make sure to keep the pins configured as inputs when
using them as analog inputs.
Port Pin
R64
R65
R66
R67
Alternate Function
AN4 (ADC input 4)
AN5 (ADC input 5)
AN6 (ADC input 6)
AN7 (ADC input 7)
The control register PMR5 (address D1H) controls the selection alternate function. After reset, this value is “0”, port
may be used as general I/O ports. To use buzzer function,
write “1” to the PMR5 and the pin R55 must be defined as
output mode (the bit 5 of R5DD=1)
Port Pin
R54
R55
30
Alternate Function
WDTO (Watchdog timer output)
BUZ (Square-wave output for buzzer)
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
10. BASIC INTERVAL TIMER
The GMS825xx has one 8-bit Basic Interval Timer that is
free-run and can not stop. Block diagram is shown in Figure 10-1.
In addition, the Basic Interval Timer generates the time
base for watchdog timer counting. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FFH to 00H, this overflow causes the interrupt to be
generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 10-2.
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and address 0D3H is read as a BITR, and written to CKCTLR.
÷16
÷32
XIN PIN
Prescaler
÷64
÷128
÷256
MUX
8-bit up-counter
source
clock
overflow
BITR
BITIF
Basic Interval Timer Interrupt
÷512
[0F9H]
÷1024
÷2048
To Watchdog timer (WDTCK)
clear
Select Input clock 3
BTS[2:0]
BTCL
CKCTLR
[0D3H]
Read
Basic Interval Timer
clock control register
Internal bus line
Figure 10-1 Block Diagram of Basic Interval Timer
CKCTLR
[2:0]
000
001
010
011
100
101
110
111
Source clock
fXIN÷16
fXIN÷32
fXIN÷64
fXIN÷128
fXIN÷256
fXIN÷512
fXIN÷1024
fXIN÷ 2048
Interrupt (overflow) Period (ms)
@ fXIN = 8MHz
0.512
1.024
2.048
4.096
8.192
16.384
32.768
65.536
Table 10-1 Basic Interval Timer Interrupt Time
FEB. 2000 Ver 1.00
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GMS82512/16/24
CKCTLR
HYUNDAI MicroElectronics
7
-
6
-
5
4
WDTON
ENPCK
3
2
1
0
BTCL
BTCL BTS2 BTS1 BTS0
ADDRESS: 0D3H
INITIAL VALUE: --01 0111B
Basic Interval Timer source clock select
000: fXIN ÷ 16
001: fXIN ÷ 32
010: fXIN ÷ 64
011: fXIN ÷ 128
100: fXIN ÷ 256
101: fXIN ÷ 512
110: fXIN ÷ 1024
111: fXIN ÷ 2048
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically
after one machine cycle, and starts counting.
Enable Peripheral clock
If this bit is 0, all peripherals are disabled such as Timer, ADC, PWM, etc.
0: Operate as a 6-bit general timer
1: Enable Watchdog Timer operation
See the section “Watchdog Timer”.
7
6
5
BITR
4
3
BTCL
2
1
0
ADDRESS: 0D3H
INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 10-2 BITR: Basic Interval Timer Mode Register
Example 1:
Interrupt request flag is generated every 8.192ms at 4MHz.
:
LDM
SET1
EI
:
CKCTLR,#1BH
BITE
Example 2:
Interrupt request flag is generated every 8.192ms at 8MHz.
:
LDM
SET1
EI
:
32
CKCTLR,#1CH
BITE
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
11. TIMER/EVENT COUNTER
The GMS825xx has four Timer/Counter registers. Each
module can generate an interrupt to indicate that an event
has occurred (i.e. timer match).
Timer 0 and Timer 1 are can be used either two 8-bit Timer/Counter or one 16-bit Timer/Counter with combine
them. And Timer 2 and Timer 3 are can be used either two
8-bit Timer or one 16-bit Timer with combine them.
In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 4 and
most clock consists of 64 oscillator periods, the count rate
is 1/4 to 1/64 of the oscillator frequency.
In the “counter” function, the register is incremented in response to a 1-to-0 (falling edge) transition at its corre-
sponding external input pin, EC0 .
In addition the “capture” function, the register is incremented in response external or internal clock sources same
with timer or counter function. When external clock edge
input, the count register is captured into Timer data register
correspondingly.
It has four operating modes: “8-bit timer/counter”, “16-bit
timer/counter”, “8-bit capture”, “16-bit capture” which are
selected by bit in Timer mode register TM0 and TM2 as
shown in Table 11-1.
In operation of Timer 2, Timer 3, their operations are same
with Timer 0, Timer 1, respectively as shown in Table 112.
TM0
CAP
0
T1ST
0
X
T1SL
[1:0]
TIMER 0
T0ST T0CN
01 or
10 or
11
X
X
01 or 10 or 11
8-bit Timer
8-bit Timer
X
X
00
8-bit Event counter
8-bit Timer
X
X
01 or 10 or 11
8-bit Capture (internal clock)
8-bit Timer
8-bit Capture (external clock)
8-bit Timer
0
X
1
X
1
X
X
X
00
0
X
X
X
01 or 10 or 11
0
X
X
X
00
1
X
X
X
01 or 10 or 11
16-bit Capture (internal clock)
1
X
X
X
00
16-bit Capture (external clock)
00
TIMER 1
T0SL[1:0]
16-bit Timer
16-bit Event counter
Table 11-1 TM0 Timer Mode Register
TM2
CAP
2
T3ST
0
X
T3SL
[1:0]
TIMER 2
T2ST T2CN
01 or
10 or
11
X
X
01 or 10 or 11
8-bit Timer
8-bit Timer
X
X
00
reserved
8-bit Timer
X
X
01 or 10 or 11
8-bit Capture (internal clock)
8-bit Timer
8-bit Capture (external clock)
8-bit Timer
0
X
1
X
1
X
X
X
00
0
X
X
X
01 or 10 or 11
0
X
X
X
00
1
X
X
X
01 or 10 or 11
16-bit Capture (internal clock)
1
X
X
X
00
16-bit Capture (external clock)
00
TIMER 3
T2SL[1:0]
16-bit Timer
16-bit Event counter
Table 11-2 TM2 Timer Mode Register
FEB. 2000 Ver 1.00
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GMS82512/16/24
TM0
TIMER 1
TIMER 0
R/W
7
R/W
6
CAP0
T1S T
R/W
5
R/W
4
R/W
3
T1 S L1 T1S L0 BT0S
TC TL
R/W
2
R/W
1
R/W
0
T 0C N T0S L 1 T0S L0
Bit Position
Description
CAP0
TM0.7
0: Timer/Counter mode
1: Capture mode selection flag
T1ST
TM0.6
0: When cleared, stop the counting.
1: When set, Timer 1 count register is cleared and start again.
T1SL1
T1SL0
TM0.5
TM0.4
00: 16-bit mode (Clock source is selected by T0SL1, T0SL0)
01: 8-bit mode, Clock source is fXIN ÷ 4
10: 8-bit mode, Clock source is fXIN ÷ 16
11: 8-bit mode, Clock source is fXIN ÷ 64
T0ST
TM0.3
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
T0CN
TM0.2
0: Stop the timer
1: A logic 1 starts the timer.
T0SL1
T0SL0
TM0.1
TM0.0
00: EC0 (External clock)
01: 8-bit Timer, Clock source is fXIN ÷ 4
10: 8-bit Timer, Clock source is fXIN ÷ 16
11: 8-bit Timer, Clock source is fXIN ÷ 64
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
CAP2 T3ST T3SL1 T3SL0 BTCL
T2ST T2CN T2SL1 T2SL0
TIMER 3
A D D R E S S : 0E 2 H
IN ITIA L V A LU E : 00 H
Bit Name
R/W
7
TM2
HYUNDAI MicroElectronics
ADDRESS: 0E3H
INITIAL VALUE: 00H
Bit Name
Bit Position
CAP2
TM2.7
0: Timer/Counter mode
1: Capture mode selection flag
T3ST
TM2.6
0: When cleared, stop the counting.
1: When set, Timer 3 count register is cleared and start again.
T3SL1
T3SL0
TM2.5
TM2.4
00: 16-bit mode (Clock source is selected by T2SL1, T2SL0)
01: 8-bit mode, Clock source is fXIN ÷ 4
10: 8-bit mode, Clock source is fXIN ÷ 16
11: 8-bit mode, Clock source is fXIN ÷ 64
T2ST
TM2.3
0: When cleared, stop the counting.
1: When set, Timer 2 Count Register is cleared and start again.
T2CN
TM2.2
0: Stop the timer
1: A logic 1 starts the timer.
T2SL1
T2SL0
TM2.1
TM2.0
00: Reserved
01: 8-bit Timer, Clock source is fXIN ÷ 4
10: 8-bit Timer, Clock source is fXIN ÷ 16
11: 8-bit Timer, Clock source is fXIN ÷ 64
TIMER 2
Description
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
TDR0~TDR3
ADDRESS: 0E4H ~ 0E7H
INITIAL VALUE: Undefined
Read: Count value read
Write: Compare data write
Figure 11-1 TM0, TM2 Registers
34
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
11.1 8-bit Timer / Counter Mode
The GMS825xx has four 8-bit Timer/Counters, Timer 0,
Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are
shown in Figure .
T3SL1, T3SL0 of TM2 should not set to zero. These timers
have each 8-bit count register and data register. The count
register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option
of 4, 16, 64 (selected by control bits TxSL1, TxSL0 of register TMx).
The “timer” or “counter” function is selected by control
registers TM0, TM2 as shown in Table 11-1 and Table 112. To use as an 8-bit timer/counter mode, bit CAP0 of TM0
is cleared to “0” and bits T1SL1, T1SL0 of TM0 or bits
7
TM0
6
5
4
3
2
1
0
CAP0 T1ST T1SL1 T1SL0 BTCL
T0ST T0CN T0SL1 T0SL0
0
X
X
X
X
ADDRESS: 0E2H
INITIAL VALUE: 00H
X
01 or 10 or 11
X means don’t care
T0SL[1:0]
T0ST
EC0 PIN
Prescaler
XIN PIN
00
÷4
÷ 16
÷ 64
0: Stop
1: Clear and start
01
T0 (8-bit)
clear
10
11
MUX
T0CN
TIMER 0
INTERRUPT
T0IF
Comparator
TIMER 0
TDR0 (8-bit)
T1SL[1:0]
T1ST
÷4
÷ 16
÷ 64
0: Stop
1: Clear and start
01
T1 (8-bit)
10
clear
11
MUX
T1IF
Comparator
TIMER 1
INTERRUPT
TIMER 1
TDR1 (8-bit)
F/F
T1O PIN
Figure 11-2 8-bit Timer/Counter 0, 1
Example 1:
Example 2:
Timer0 = 4ms 8-bit timer mode at 4MHz
Timer1 = 1ms 8-bit timer mode at 4MHz
Timer0 = 8-bit event counter mode
Timer1 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
SET1
SET1
EI
TDR0,#250
TDR1,#250
TM0,#0110_1111B
T0E
T1E
FEB. 2000 Ver 1.00
LDM
LDM
LDM
SET1
SET1
EI
TDR0,#250
TDR1,#250
TM0,#0110_1100B
T0E
T1E
35
GMS82512/16/24
HYUNDAI MicroElectronics
As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx.
Note: The contents of Timer data register TDRx should be
initialized 1H~FFH, not 0H, because it is undefined after reset.
In counter function, the counter is increased every 1-to-0
(falling edge) transition of EC0 pin. In order to use counter
function, the bit 4 of the Port mode register PMR4 are set
to “1”. The Timer 0 can be used as a counter by pin EC0
input, but Timer 1 can input by internal clock.
In the Timer 0, timer register T0 increments from 00 H until
it matches TDR0 and then reset to 00H. The match output
of Timer 0 generates Timer 0 interrupt (latched in T0IF bit)
7
TM2
6
5
4
3
2
1
0
ADDRESS: 0E3H
INITIAL VALUE: 00H
CAP2 T3ST T3SL1 T3SL0 BTCL
T2ST T2CN T2SL1 T2SL0
0
X
X
X
X
X
01 or 10 or 11
X means don’t care
T2SL[1:0]
T2ST
XIN PIN
Prescaler
Reserved
00
÷4
÷ 16
÷ 64
0: Stop
1: Clear and start
01
T2 (8-bit)
clear
10
11
MUX
T2CN
TIMER 2
INTERRUPT
T2IF
Comparator
TIMER 2
TDR2 (8-bit)
T3SL[1:0]
T3ST
÷4
÷ 16
÷ 64
0: Stop
1: Clear and start
01
T3 (8-bit)
10
clear
11
MUX
T3IF
Comparator
TIMER 3
INTERRUPT
TIMER 3
TDR3 (8-bit)
T3O PIN
F/F
Figure 11-3 8-bit Timer/Counter 2, 3
Example 3:
Example 4:
Timer2 = 8-bit timer mode, 2ms interval at 8MHz
Timer3 = 8-bit timer mode, 500us interval at 8MHz
Timer2 = 8-bit event counter mode
Timer3 = 500us 8-bit timer mode at 8MHz
LDM
LDM
LDM
SET1
SET1
EI
36
TDR2,#250
TDR3,#250
TM2,#0110_1111B
T2E
T3E
LDM
LDM
LDM
SET1
SET1
EI
TDR2,#250
TDR3,#250
TM2,#0110_1100B
T2E
T3E
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
8-bit Timer Mode
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents
of up-counter, Tn. If match is found, a timer 1 interrupt
(T1IF) is generated and the up-counter is cleared to 0.
Counting up is resumed after the up-counter is cleared.
Value of
TM[1:0]
Clock
Source
00
01
10
11
fEC1
fXIN ÷ 4
fXIN ÷ 16
fXIN ÷ 64
As the value of TDRn is changeable by software, time interval is set as you want
Maximum Time
Setting
(At fXIN=8 M Hz)
Resolution
(At fXIN=8 M Hz)
1/fEC1 × 256 sec
128 us
512 us
2048 us
1/fEC1 sec
0.5 us
2 us
8 us
Table 11-1 Timer Source clock Interrupt Time
Start count
~
~
Source clock
~
~
Up-counter
0
2
1
n-2
3
n-1
n
0
2
1
3
4
~
~
TDR1
n
~
~
Match
Detect
Counter
Clear
~
~
T1IF interrupt
Figure 11-4 Timer Mode Timing Chart
Example: Make 1msinterrupt using by Timer0 at 8MHz
LDM
LDM
SET1
EI
TM0,#1FH
TDR0,#125
T0E
;
;
;
;
divide by 64
8us x 125= 1ms
Enable Timer 0 Interrupt
Enable Master Interrupt
When
TM0 = 0001 1111B (8-bit Timer mode, Prescaler divide ratio = 64)
TDR0 = 125D = 7DH
fXIN = 8 MHz
1
INTERRUPT PERIOD =
× 64 × 125 = 1 ms
8 × 106 Hz
TDR1
MATCH
(TDR0 = T0)
8 µs
~~
~~
up
-c
ou
nt
~~
7B
7A
6
Count Pulse
Period
7D
7C
7D
5
4
3
2
1
0
0
TIME
Interrupt period
= 8 µs x 125
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 11-5 Timer Count Example
FEB. 2000 Ver 1.00
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HYUNDAI MicroElectronics
8-bit Event Counter Mode
In order to use event counter function, the bit 4 of the Port
Mode Register PMR4(address 0D0H) is required to be set
to “1”.
In this mode, counting up is started by an external trigger.
This trigger means falling edge of the EC0 pin input.
Source clock is used as an internal clock selected with timer mode register TM0. The contents of timer data register
TDRn (n = 0,1) are compared with the contents of the upcounter Tn. If a match is found, an timer interrupt request
flag TnIF is generated, and the counter is cleared to “0”.
The counter is restart and count up continuously by every
falling edge of the EC0 pin input.
After reset, the value of timer data register TDRn is undefined, it should be initialized to between 1H~FFHnot to
"0"The interval period of Timer is calculated as below
equation.
1
Period (sec) = ----------- × 2 × Divide Ratio × TDRn
f XIN
The maximum frequency applied to the EC0 pin is fXIN/2
[Hz].
Start count
~
~
EC0 pin input
~
~
1
0
2
~
~
Up-counter
n-1
n
1
0
2
~
~
n
~
~
TDR1
~
~
T1IF interrupt
Figure 11-6 Event Counter Mode Timing Chart
TDR1
disable
~~
clear & start
enable
up
-c
ou
nt
stop
~~
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
T1ST
Start & Stop
T1ST = 1
T1ST = 0
T1CN
Control count
T1CN = 1
T1CN = 0
Figure 11-7 Count Operation of Timer / Event counter
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11.2 16-bit Timer / Counter Mode
Even if the Timer 0 (including the Timer 1) is used as a 16bit timer, the Timer 2 and Timer 3 can still be used as either
two 8-bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including the Timer 3) is used
as a 16-bit timer, the Timer 0 and Timer 1 can still be used
as 8-bit timer independently.
The Timer register is being run with all 16 bits. A 16-bit
timer/counter register T0, T1 are incremented from 0000 H
until it matches TDR0, TDR1 and then resets to 0000H.
The match output generates Timer 0 interrupt.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0SL1, T0SL0.
7
TM0
6
5
4
3
2
1
0
CAP0 T1ST T1SL1 T1SL0 BTCL
T0ST T0CN T0SL1 T0SL0
0
X
0
0
X
X
X
ADDRESS: 0E2H
INITIAL VALUE: 00H
X
X means don’t care
T0SL[1:0]
EDGE DETECTOR
EC0 PIN
T0ST
0: Stop
1: Clear and start
Prescaler
“00”
XIN PIN
0
÷4
T1 + T0
(16-bit)
“01”
÷ 16
1
clear
“10”
÷ 64
“11”
MUX
T0CN
TIMER 0
INTERRUPT
T0IF
Comparator
(Not Timer 1 interrupt)
TDR1 + TDR0
(16-bit)
TIMER 0 + TIMER 1 → TIMER 0 (16-bit)
Higher byte Lower byte
COMPARE DATA
7
TM2
6
5
4
0
X
0
0
2
1
0
Prescaler
Reserved
÷ 16
÷ 64
X
X
X
T2ST
0: Stop
1: Clear and start
“00”
÷4
X
ADDRESS: 0E3H
INITIAL VALUE: 00H
X means don’t care
T2SL[1:0]
XIN PIN
3
CAP2 T3ST T3SL1 T3SL0 BTCL
T2ST T2CN T2SL1 T2SL0
0
“01”
1
T3 + T2
(16-bit)
clear
“10”
“11”
MUX
T2CN
T2IF
Comparator
TIMER 2
INTERRUPT
(Not Timer 3 interrupt)
TIMER 2 + TIMER 3 → TIMER 2 (16-bit)
TDR3 + TDR2
(16-bit)
Higher byte Lower byte
COMPARE DATA
Figure 11-8 16-bit Timer/Counter
FEB. 2000 Ver 1.00
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HYUNDAI MicroElectronics
11.3 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP2 of timer mode register TM2
for Timer 2) as shown in Figure 21. In this mode, Timer 1
still operates as an 8-bit timer/counter.
causes the current value in the Timer counter register
(T0,T2), to be captured into registers CDRn (CDR0,
CDR2), respectively. After captured, Timer counter register is cleared and restarts by hardware.
As mentioned above, not only Timer 0 but Timer 2 can also
be used as a capture mode.
Note: The CDRn and TDRn are in same address.In the
capture mode, reading operation is read the CDRn, not
TDRn because path is opened to the CDRn.
In 8-bit capture mode, Timer 1 and Timer 3 are can not be
used as a capture mode.
It has three transition modes: "falling edge", "rising edge",
"both edge" which are selected by interrupt edge selection
register IEDS. Refer to “14.4 External Interrupt” on page
51. In addition, the transition at INTn pin generate an interrupt.
The Timer/Counter register is incremented in response internal or external input. This counting function is same
with normal timer mode, but Timer interrupt is not generated. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTn pin
7
TM0
6
5
4
3
2
1
0
CAP0 T1ST T1SL1 T1SL0 BTCL
T0ST T0CN T0SL1 T0SL0
1
X
X
X
X
ADDRESS: 0E2H
INITIAL VALUE: 00H
X
01 or 10 or 11
X means don’t care
T0SL[1:0]
Edge Detector
T0ST
EC0 PIN
Prescaler
XIN PIN
“00”
÷4
÷ 16
÷ 64
0: Stop
1: Clear and start
“01”
T0 (8-bit)
“10”
“11”
T0CN
MUX
Capture
To TIMER1
IEDS[1:0]
CDR0 (8-bit)
TIMER 0
“01”
INT0 PIN
“10”
INT0IF
INT0
INTERRUPT
“11”
This figure is a example of using the Timer0.
In the Timer2, operation is same like Timer0, each registers and
flags may be changed with for Timer2.
Figure 11-9 8-bit Capture Mode
40
FEB. 2000 Ver 1.00
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GMS82512/16/24
11.4 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
7
TM0
6
5
4
3
2
1
0
CAP0 T1ST T1SL1 T1SL0 BTCL
T0ST T0CN T0SL1 T0SL0
1
0
X
0
X
X
X
ADDRESS: 0E2H
INITIAL VALUE: 00H
X
X means don’t care
T0SL[1:0]
Edge Detector
T0ST
EC0 PIN
Prescaler
XIN PIN
“00”
÷4
÷ 16
÷ 64
T1 + T0
(16-bit)
“01”
“10”
“11”
MUX
IEDS[1:0]
T0CN
Capture
CDR1 + CDR0
(16-bit)
“01”
INT0 PIN
0: Stop
1: Clear and start
“10”
Higher byte Lower byte
CAPTURE DATA
INT0IF
INT0
INTERRUPT
“11”
TIMER 0 + TIMER 1 → TIMER 0 (16-bit)
This figure is a example of using the Timer0, 1.
In the Timer2, 3, operation is same like Timer0,1, each registers and
flags may be changed with for Timer2,3.
Figure 11-10 16-bit Capture Mode
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Example 1:
Timer0 = 16-bit timer mode, 0.5s at 8MHz
Timer2 = 2ms 8-bit timer mode at 8MHz
Timer3 = 250us 8-bit timer mode at 8MHz
LDM
LDM
LDM
LDM
LDM
LDM
SET1
SET1
SET1
EI
:
:
TDR0,#23H
TDR1,#0F4H
TM0,#0FH
TDR2,#249
TDR3,#124
TM2,#0110_1111B
T0E
T2E
T3E
LDM
LDM
SET1
LDM
LDM
LDM
SET1
LDM
LDM
SET1
EI
:
:
TDR0,#250
TM0,#0111_1111B
T0E
TDR2,#40H
TDR3,#2AH
TM2,#1111_1111B
T2E
IEDS,#XX11_XXXXB
PMR4,#XXXX_X1XXB
INT2E
X: don’t care.
Example 4:
Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 16-bit capture mode
Example 2:
Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 16-bit event counter mode
LDM
LDM
LDM
LDM
LDM
SET1
SET1
EI
:
:
HYUNDAI MicroElectronics
TDR0,#249
TM0,#0111_1111B
TDR2,#3FH
TDR3,#2AH
TM2,#0100_1100B
T0E
T2E
Example 3:
LDM
LDM
SET1
LDM
LDM
LDM
SET1
LDM
LDM
SET1
EI
:
:
TDR0,#249
TM0,#0111_1111B
T0E
TDR2,#40H
TDR3,#2AH
TM2,#1100_1111B
T2E
IEDS,#XX11_XXXXB
PMR4,#XXXX_X1XXB
INT2E
X: don’t care.
Timer0 = 8-bit timer mode, 2ms interval at 8MHz
Timer2 = 8-bit capture mode
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12. ANALOG DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which generates the result via successive approximation. The analog
supply voltage is connected to AVDD of ladder resistance
of A/D module.
The A/D module has two registers which are the control
register ADCM and A/D result register ADR. The register
ADCM, shown in Figure 12-2, controls the operation of
the A/D converter module. The port pins can be configured
as analog inputs or digital I/O. To use analog inputs, I/O is
selected input mode by R3DD or R6DD direction register.
How to Use A/D Converter
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag AIF is set.
The block diagram of the A/D module is shown in Figure
12-1. The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20
uS (at fXIN=8 MHz).
“0”
AVDD
ADS[2:0]
000
R30/AN0
8-bit DAC
ADEN
LADDER RESISTOR
“1”
001
R31/AN1
R32/AN2
R33/AN3
010
011
100
R64/AN4
S/H
SUCCESSIVE
APPROXIMATION
CIRCUIT
ADIF
A/D
INTERRUPT
101
R65/AN5
R66/AN6
R67/AN7
Sample & Hold
110
111
ADR
ADDRESS: E9H
RESET VALUE: Undefined
A/D result register
Figure 12-1 A/D Block Diagram
FEB. 2000 Ver 1.00
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ADCM
HYUNDAI MicroElectronics
7
-
6
-
R/W
5
R/W
4
R/W R/W R/W R
3
2
1
0
ADEN ADS2 BTCL
ADS1 ADS0 ADST ADSF
ADDRESS: 0E8H
INITIAL VALUE: --00 0001B
A/D status bit
0: A/D conversion is in progress
1: A/D conversion is completed
A/D start bit
Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to “0” by hardware.
Analog input channel select
000: Channel 0 (AN0)
001: Channel 1 (AN1)
010: Channel 2 (AN2)
011: Channel 3 (AN3)
100: Channel 4 (AN4)
101: Channel 5 (AN5)
110: Channel 6 (AN6)
111: Channel 7 (AN7)
A/D converter Enable bit
0: A/D converter module turn off and
current is not flow.
1: Enable A/D converter
R
7
ADR
R
6
R
5
R
4
R
3
BTCL
R
2
R
1
R
0
ADDRESS: 0E9H
INITIAL VALUE: Undefined
A/D Conversion Data
Figure 12-2 A/D Converter Control Register
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13. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter,
buzzer register, and clock source selector. It generates
square-wave which has very wide range frequency (500Hz
~ 250kHz at fXIN= 8MHz) by user software.
The bit 0 to 5 of BUR determines output frequency for
buzzer driving.
A 50% duty pulse can be output to R55/BUZ pin to use for
piezo-electric buzzer drive. Pin R55 is assigned for output port
f XIN
f BUZ = ------------------------------------------------------------2 × DivideRatio × BUR
Equation of frequency calculation is shown below.
of Buzzer driver by setting the bit 5 of PMR5 (address D1H) to
“1”. At this time, the pin R55 must be defined as output
fBUZ: Buzzer frequency
mode (the bit 5 of R5DD=1).
fXIN: Oscillator frequency
Example: 2.4kHz output at 8MHz.
Divide Ratio: Prescaler divide ratio by BUCK[1:0]
BUR: Lower 6-bit value of BUR. Buzzer period value.
LDM
LDM
R5DD,#XX1X_XXXXB
BUR,#9AH
LDM
PMR5,#XX1X_XXXXB
The frequency of output signal is controlled by the buzzer
control register BUR.The bit 0 to bit 5 of BUR determine
output frequency for buzzer driving.
X means don’t care
R55 port data
6-bit binary
Prescaler
÷16
XIN PIN
00
÷32
6-BIT COUNTER
01
÷64
÷128
0
÷2
10
R55/BUZ PIN
1
F/F
11
Comparator
MUX
2
Compare data
6
PMR5
BUR
Port selection
[0D1H]
[0ECH]
Internal bus line
Figure 13-1 Block Diagram of Buzzer Driver
ADDRESS: 0D1H
RESET VALUE: --00 ----B
W
PMR5
-
-
ADDRESS: 0ECH
RESET VALUE: Undefined
W
W
-
-
-
-
BUR
W
W
W
W
W
W
W
BUCK1 BUCK0
R54/WDTO Selection
0: R54
1: WDTO (Output)
R55/BUZ Selection
0: R55 port (Turn off buzzer)
1: BUZ port (Turn on buzzer)
BUR[5:0]
Buzzer Period Data
Source clock select
00: ÷16
01: ÷ 32
10: ÷ 64
11: ÷128
Figure 13-2 PMR5 and Buzzer Register
FEB. 2000 Ver 1.00
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HYUNDAI MicroElectronics
Note: BUR is undefined after reset, so it must be initialized
to between 1H and 3FH by software.
Note that BUR is a write-only register.
The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00H until
it matches 6-bit BUR value.
When main-frequency is 8MHz, buzzer frequency is
shown as below table.
[kHz]
BUR
[5:0]
BUR[7:6]
00
01
10
11
BUR
[5:0]
BUR[7:6]
00
01
10
11
00
01
02
03
04
05
06
07
250.000
125.000
83.333
62.500
50.000
41.667
35.714
125.000
62.500
41.667
31.250
25.000
20.833
17.857
62.500
31.250
20.833
15.625
12.500
10.417
8.929
31.250
15.625
10.417
7.813
6.250
5.208
4.464
20
21
22
23
24
25
26
27
7.813
7.576
7.353
7.143
6.944
6.757
6.579
6.410
3.906
3.788
3.676
3.571
3.472
3.378
3.289
3.205
1.953
1.894
1.838
1.786
1.736
1.689
1.645
1.603
0.977
0.947
0.919
0.893
0.868
0.845
0.822
0.801
08
09
0A
0B
0C
0D
0E
0F
31.250
27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625
13.889
12.500
11.364
10.417
9.615
8.929
8.333
7.813
6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906
3.472
3.125
2.841
2.604
2.404
2.232
2.083
28
29
2A
2B
2C
2D
2E
2F
6.250
6.098
5.952
5.814
5.682
5.556
5.435
5.319
3.125
3.049
2.976
2.907
2.841
2.778
2.717
2.660
1.563
1.524
1.488
1.453
1.420
1.389
1.359
1.330
0.781
0.762
0.744
0.727
0.710
0.694
0.679
0.665
10
11
12
13
14
15
16
17
15.625
14.706
13.889
13.158
12.500
11.905
11.364
10.870
7.813
7.353
6.944
6.579
6.250
5.952
5.682
5.435
3.906
3.676
3.472
3.289
3.125
2.976
2.841
2.717
1.953
1.838
1.736
1.645
1.563
1.488
1.420
1.359
30
31
32
33
34
35
36
37
5.208
5.102
5.000
4.902
4.808
4.717
4.630
4.545
2.604
2.551
2.500
2.451
2.404
2.358
2.315
2.273
1.302
1.276
1.250
1.225
1.202
1.179
1.157
1.136
0.651
0.638
0.625
0.613
0.601
0.590
0.579
0.568
18
19
1A
1B
1C
1D
1E
1F
10.417
10.000
9.615
9.259
8.929
8.621
8.333
8.065
5.208
5.000
4.808
4.630
4.464
4.310
4.167
4.032
2.604
2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.302
1.250
1.202
1.157
1.116
1.078
1.042
1.008
38
39
3A
3B
3C
3D
3E
3F
4.464
4.386
4.310
4.237
4.167
4.098
4.032
3.968
2.232
2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.116
1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.558
0.548
0.539
0.530
0.521
0.512
0.504
0.496
Table 13-1 Buzzer Frequency
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14. INTERRUPTS
The GMS825xx interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit, and Master enable flag (“I”
flag of PSW). Thirteen interrupt sources are provided. The
configuration of interrupt circuit is shown in Figure 14-2.
register (IENH, IENL), and the interrupt request flags (in
IRQH and IRQL) except Power-on reset and software
BRK interrupt. Below table shows the Interrupt priority.
Reset/Interrupt
The External Interrupts INT0 ~ INT3 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection
IEDS.
The flags that actually generate these interrupts are bit
INT0F, INT1F, INT2F and INT3F in register IRQH. When
an external interrupt is generated, the flag that generated it
is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated.
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Basic Interval Timer
Watchdog Timer
The Timer 0 ~ Timer 3 Interrupts are generated by TxIF
which is set by a match in their respective timer/counter
register. The Basic Interval Timer Interrupt is generated by
BITIF which is set by an overflow in the timer register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on page 16), the interrupt enable
R/W
R/W
R/W
R/W
INT0IF INT1IF INT2IF INT3IF
Priority
RESET
INT0
INT1
INT2
INT3
Timer 0
Timer 1
Timer 2
Timer 3
ADC
BIT
WDT
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses are shown in Figure 8-6 on page 18. Interrupt enable registers are shown in Figure 14-3. These
registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
The AD converter Interrupt is generated by ADIF which is
set by finishing the analog to digital conversion.
The Watchdog timer Interrupt is generated by WDTIF
which set by a match in Watchdog timer register.
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer counter register.
IRQH
Symbol
R/W
R/W
R/W
R/W
T0IF
T1IF
T2IF
T3IF
MSB
ADDRESS: 0F7H
INITIAL VALUE: 0000 0000B
LSB
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
Timer/Counter 0 interrupt request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
R/W
IRQL
ADIF
MSB
R/W
R/W
WDTIF BITIF
-
-
-
-
ADDRESS: 0F5H
INITIAL VALUE: 000- ----B
LSB
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Figure 14-1 Interrupt Request Flag
FEB. 2000 Ver 1.00
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HYUNDAI MicroElectronics
.
Internal bus line
[0F6H]
Interrupt Enable
Register (Higher byte)
IENH
IRQH
[0F7H]
INT0IF
INT1
INT1IF
INT2
INT2IF
INT3
INT3IF
Timer 0
T0IF
Timer 1
T1IF
Timer 2
T2IF
Timer 3
T3IF
Release STOP
Priority Control
INT0
To CPU
I-flag
Interrupt Master
Enable Flag
IRQL
[0F5H]
A/D Converter
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
ADIF
Watchdog Timer
Interrupt
Vector
Address
Generator
WDTIF
BIT
BITIF
[0F4H]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 14-2 Block Diagram of Interrupt
R/W
IENH
INT0E
R/W
R/W
R/W
INT1E INT2E INT3E
R/W
R/W
R/W
R/W
T0E
T1E
T2E
T3E
MSB
ADDRESS: 0F6H
INITIAL VALUE: 0000 0000B
LSB
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag
External interrupt 3 enable flag
External interrupt 2 enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
IENL
R/W
R/W
R/W
ADE
WDTE
BITE
MSB
-
-
-
-
VALUE
0: Disable
1: Enable
ADDRESS: 0F4H
INITIAL VALUE: 000- ----B
LSB
Basic Interval Timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
Figure 14-3 Interrupt Enable Flag
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14.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 fXIN (2
µs at fMAIN=4.19MHz) after the completion of the current
instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction
[RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
V.L.
V.L.
ADL
V.H.
ADH
New PC
OP code
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
0FFE6H
0FFE7H
012H
0E3H
Entry Address
0E312H
0E313H
When nested interrupt service is required, the I-flag should
be set to “1” by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
0EH
2EH
Saving/Restoring General-purpose Register
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to
“1” even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
FEB. 2000 Ver 1.00
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
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area for saving registers.
14.2 BRK Interrupt
The following method is used to save/restore the generalpurpose registers.
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Example: Register save using push and pop instructions
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
Each processing step is determined by B-flag as shown in
Figure 14-5.
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
B-FLAG
General-purpose register save/restore using push and pop
instructions;
main task
acceptance of
interrupt
BRK or
TCALL0
=0
=1
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
interrupt
service task
saving
registers
restoring
registers
Figure 14-5 Execution of BRK/TCALL0
interrupt return
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14.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence determines by hardware which request is serviced.
Main Program
service
Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER 1
service
enable INT0
disable other
INT0
service
EI
Occur
TIMER1 interrupt
However, multiple processing through software for special
features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Occur
INT0
enable INT0
enable other
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
:
:
:
LDM
LDM
POP
POP
POP
RETI
A
X
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
IENH,#0FFH ;Enable all interrupts
IENL,#0F0H
Y
X
A
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Figure 14-6 Execution of Multi Interrupt
14.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0F8H) as shown in Figure 14-7.
FEB. 2000 Ver 1.00
The edge detection of external interrupt has three transition
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activated mode: rising edge, falling edge, and both edge.
spondingly.
Example: To use as an INT0 and INT2
INT0 pin
INT0IF
INT0 INTERRUPT
INT1 pin
INT1IF
INT1 INTERRUPT
INT2 pin
INT2IF
:
:
;**** Set port as an input port R40,R42
LDM
R4DD,#1111_1010B
;
;**** Set port as an external interrupt port
LDM
PMR4,#05H
;
;**** Set Falling-edge Detection
LDM
IEDS,#0001_0001B
:
:
:
INT2 INTERRUPT
INT3 pin
Response Time
INT3IF
INT3 INTERRUPT
2
2
IEDS
2
2
Edge selection
Register
[0F8H]
Figure 14-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports
(R40~R43). To use as an external interrupt pin, the bit of
R4 port mode register PMR4 should be set to “1” corre-
max. 12 fXIN
Interrupt Interrupt
goes
latched
active
The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
Figure 14-8shows interrupt response timings.
8 fXIN
Interrupt
processing
Interrupt
routine
Figure 14-8 Interrupt Response Timing Diagram
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W
PMR4
-
-
-
W
W
W
W
ADDRESS: 0D0H
INITIAL VALUE: 00H
EC0S INT3S
BTCL INT2S INT1S INT0S
MSB
LSB
0: R40
1: INT0
0: R41
1: INT1
0: R42
1: INT2
0: R43
1: INT3
0: R44
1: EC0
MSB
W
IEDS
W
W
W
W
W
W
LSB
W
IED3H IED3L IED2H IED2L IED1H
BTCL IED1L IED0H IED0L
INT3
INT2
INT1
ADDRESS: 0F8H
INITIAL VALUE: 00H
INT0
Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
Figure 14-9 PMR4 and IEDS Registers
FEB. 2000 Ver 1.00
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15. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and resumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
clear
BASIC INTERVAL TIMER
OVERFLOW
Watchdog
Counter (8-bit)
Count source
clear
“0”
to reset CPU
“1”
enable
comparator
WDTON in CKCTLR [0D3H]
6-bit compare data
WDTCL
WDTIF
6
Watchdog Timer interrupt
Watchdog Timer
Register
WDTR
[0E0H]
Internal bus line
Figure 15-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
Figure 15-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).
If the malfunction occurs for any cause, the watchdog timW
7
WDTR
-
W
6
W
5
W
4
W
3
W
2
W
1
W
0
W DTCL
ADDRESS: 0E0H
INITIAL VALUE: -011_1111B
6-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
NOTE:
The WDTON bit is in register CKCTLR.
Figure 15-2 WDTR: Watchdog Timer Data Register
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Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
Within WDT
detection time
Within WDT
detection time
LDM
LDM
CKCTLR,#3FH
WDTR,#04FH
;Select 1/2048 clock source, WDTON ← 1, Clear Counter
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#04FH
;Clear counter
WDTR,#04FH
;Clear counter
WDTR,#04FH
;Clear counter
Enable and Disable Watchdog
Watchdog Timer Interrupt
Watchdog timer is enabled by setting WDTON (bit 5 in
CKCTLR) to “1”. WDTON is initialized to “0” during reset and it should be set to “1” to operate after reset is released.
The watchdog timer can be also used as a simple 6-bit timer by clearing bit5 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.
Example: Enables watchdog timer for Reset
:
LDM
:
:
T = WDTR × Interval of BIT
CKCTLR,#xx1x_xxxxB;WDTON ← 1
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 6-bit timer interrupt set up.
The watchdog timer is disabled by clearing bit 5 (WDTON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is released.
LDM
LDM
CKCTLR,#xx0xxxxxB;WDTON ←0
WDTR,#7FH
;WDTCL ←1
:
Source clock
BIT overflow
Binary-counter
2
1
3
0
1
2
3
0
Counter
Clear
WDTR
3
n
Match
Detect
WDTIF interrupt
WDTR ← “0100_0011B”
WDT reset
reset
Figure 15-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware.
FEB. 2000 Ver 1.00
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
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16. POWER DOWN OPERATION
GMS825xx has a power-down mode. In power-down
mode, power consumption is reduced considerably that in
battery operation. Battery life can be extended a lot.
STOP Mode is entered by STOP instruction.
16.1 STOP Mode
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Note: Since the XIN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
Start The Stop Operation
An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD
is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level before the
Stop mode is terminated.
CPU
All CPU operations are disabled
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP instruction should be written as shown in example below.
RAM
Retain
Example:
XIN PIN
Low
XOUT PIN
High
Oscillation
Stop
I/O ports
Retain
Control Registers
Retain
Release method
by RESET, by External interrupt
Peripheral
STOP Mode
LDM
STOP
NOP
NOP
:
The Interval Timer Register CKCTLR should be initialized (0FH or 0EH) by software in order that oscillation stabilization time should be longer than 20ms before STOP
mode.
~ ~
~
~
~
~
Oscillator
(XIN pin)
CKCTLR,#0000_1110B
~
~
~
~
Internal Clock
~
~
STOP Instruction
Executed
n+1 n+2
n+3
0
1
~
~
~ ~
n
~ ~
~
~
BIT Counter
~
~
External Interrupt
FE
FF
0
1
2
Clear
Normal Operation
Stop Operation
tST > 20ms
by software
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 16-1 STOP Mode Release Timing by External Interrupt
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Release the STOP mode
The exit from STOP mode is using hardware reset or external interrupt.
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.
Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all
stopped.
Chip function after event
Event
MCU Status before event
PC
Oscillator Circuit
Don’t care
Vector
on
STOP instruction
Normal operation
N +1
off
External Interrupt
Normal operation
Vector
on
External Interrupt Wake up
STOP, I flag = 1
STOP, I flag = 0
Vector
N+1
on
on
RESET
Table 16-1 Wake-up and Reset Function Table
16.2 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(VDD/VSS); however, when the input level becomes higher
than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
FEB. 2000 Ver 1.00
It should be set properly in order that current flow through
port doesn't exist.
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if unfirmed voltage level
(not VSSor VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there
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is external pull-down register, it is set to low.
VDD
INPUT PIN
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i=0
O
OPEN
O
i
i
GND
Very weak current flows
VDD
X
X
i=0
O
OPEN
Weak pull-up current flows
GND
O
When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 16-2 Application Example of Unused Input Port
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
O
OFF
VDD
GND
X
ON
i
ON
OFF
L
OFF
ON
i
GND
X
O
VDD
L
i=0
GND
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.
In the left case, much current flows from port to GND.
Figure 16-3 Application Example of Unused Output Port
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17. OSCILLATOR CIRCUIT
The GMS825xx has two oscillation circuits internally. XIN
and XOUT are input and output for frequency, respectively,
inverting amplifier which can be configured for being used
as an on-chip oscillator, as shown in Figure 17-1.
C1
XOUT
Open
C2
8MHz
XOUT
XIN
External Clock
VSS
XIN
Recommend
Crystal Oscillator
External Oscillator
C1,C2 = 30pF±10pF
Crystal or Ceramic Oscillator
Figure 17-1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
XOUT
XIN
In addition, see Figure 17-2 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
FEB. 2000 Ver 1.00
Figure 17-2 Layout of Oscillator PCB circuit
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18. RESET
The GMS825xx have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware
Program counter
G-flag
Initial Value
(PC)
dog timer reset. Table 18-1 shows on-chip hardware initialization by reset action.
On-chip Hardware
Initial Value
(FFFFH) - (FFFEH)
Watchdog timer
Disable
0
Control registers
Refer to Table 8-1 on page 22
(G)
Peripheral clock
Off
Power fail detector
Disable
Table 18-1 Initializing Internal Status by Reset Action
18.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start execution as shown in Figure 18-2.
A connection for simple power-on-reset is shown in Figure
18-1.
VCC
10kΩ
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
+
10uF
When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH.
Figure 18-1 Simple Power-on-Reset Circuit
1
3
?
?
4
5
6
7
~
~
RESET
~
~
?
?
FFFE FFFF Start
~
~ ~
~
?
?
?
?
FE
ADL
ADH
OP
~
~
DATA
BUS
2
~
~
Oscillator
(XIN pin)
ADDRESS
BUS
to the RESET pin
7036P
Stabilization Time
tST = 62.5mS at 4.19MHz
RESET Process Step
tST =
1
fMAIN ÷1024
MAIN PROGRAM
x 256
Figure 18-2 Timing Diagram after RESET
18.2 Watchdog Timer Reset
Refer to “15. WATCHDOG TIMER” on page 54.
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19. POWER FAIL PROCESSOR
The GMS825xx has an on-chip power fail detection circuitry to immunize against power noise. A configuration
register, PFDR, can enable or disable the power fail detect
circuitry. Whenever VDD falls close to or below power fail
voltage for 100ns, the power fail situation may reset or
freeze MCU according to PFR bit of PFDR. Refer to “7.4
DC Electrical Characteristics” on page 11.
Note: If power fail voltage is selected to 3.0V on 3V operation, MCU is freezed at all the times.
Power FailFunction
OTP
MASK
Enable/Disable
by PFD flag
by PFD flag
Level Selection
by PFV flag
by mask option
In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may
be experimented or evaluated.
Table 19-1 Power fail processor
Note: User can select power fail voltage level according to
PFV bit of PFDR at the OTP(GMS82524T) but must select
the power fail voltage level to define PFD option of “Mask
Order & Verification Sheet” at the mask chip(GMS825xx).
Because the power fail voltage level of mask chip
(GMS825xx) is determined according to mask option regardless of PFV bit of PFDR
7
PFDR
6
5
4
R/W
3
PFV
R/W
2
R/W
1
R/W
0
PFD
PFR
PFS
ADDRESS: 0F9H
INITIAL VALUE: ---- 1100B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
Operation Mode
0: Normal operation regardless of power fail
1: MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Power Fail Voltage Selection Flag
0: 2.4V
1: 3.0V
Figure 19-1 Power Fail Voltage Detector Register
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RESET VECTOR
YES
PFS =1
NO
RAM CLEAR
INITIALIZE RAM DATA
PFS = 0
Skip the
initial routine
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
Figure 19-2 Example S/W of RESET flow by Power fail
VDD
VPFDMAX
VPFDMIN
64mS
Internal
RESET
VDD
When PFR = 1
Internal
RESET
64mS
t <64mS
VDD
Internal
RESET
VPFDMAX
VPFDMIN
64mS
VPFDMAX
VPFDMIN
Figure 19-3 Power Fail Processor Situations
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20. OTP PROGRAMMING
The GMS82524T is OTP (One Time Programmable) microcontroller. Its internal user memory is constructed with
EPROM (Electrically Programmable Read Only Memory).
The OTP micorcontroller is generally used for chip evaluation, first production, small amount production, fast mass
production, etc.
Programming Procedure
1. Select device GMS82524T.
2. Load the *.OTP file to the programmer. The file is composed of Motorola-S1 format.
3. Set the programming address range as below table.
GMS82524T
Blank OTP’s internal EPROM is filled by 00H, not FFH.
Note: In any case, you have to use *.OTP file, not *.HEX
file. After assemble, both OTP and HEX file are generated
by automatically. The HEX file is used during porgram emulation on emulator.
20.1 How to Program
Address
Set Value
Bufferstart address
2000H
Buffer end address
7FFFH
Device start address
A000H
4. Mount the socket adapter on the programmer.
5. Start program/verify.
To program the OTP devices, user can use HME own programmer or third party universal programmer shown as
listed below.
20.2 Pin Function
HME own programmer list
VPP (Program Voltage)
VPP is the input for the program voltage for programming
the EPROM.
Manufacturer: Hyundai MicroElectronics
Programmer: Choice-Dr Writer
Choice-Sigma, Choice-Gang4
The Choice-Dr Writer is single writer and physically addon adapter board type, it should be used with Choice-Dr
emulator. However, the Choice-Sigma is stand alone HME
universal single programmer for any HME OTP devices,
also the Choice-Gang4 can program four OTPs at once.
Ask to HME sales part which is listed on appendix of this
manual.
Third party programmer list
CE (Chip Enable)
CE is the input for programming and verifying internal
EPROM.
OE (Output Enable)
OE is the input of data output control signal for verify.
A0~A15 (Address Bus)
A0~A15 are address input pins for internal EPROM.
D0~D7 (EPROM Data Bus)
These are data bus for internal EPROM.
N.C. (No Connection)
Manufacturer: Hi-Lo Systems
Programmer: ALL-11, ALL-07
Website : http: //www.hilosystems.com.tw
Socket adapters are supported by third party programmer’s
manufacturer. The other third party will be registered and
being under development.
FEB. 2000 Ver 1.00
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42SDIP
(Top View)
CE
OE
N.C.*
A15
A14
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
A8
A9
A10
A11
A12
A13
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GMS82524T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A0
VDD
VPP
GND
33
32
31
30
29
28
27
26
25
24
23
A7
D0
D1
D2
D3
D4
D5
D6
D7
N.C.
A8
44QFP
(Top View)
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
GMS82524T
A9
A10
A11
A12
A13
A14
A15
N.C.*
OE
CE
VDD
N.C.*
1
2
3
4
5
6
7
8
9
10
11
A6
A5
A4
A3
A2
A1
A0
VDD
VPP
N.C.*: No Connection
64
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
20.3 Programming Specification
DEVICE OPERATION MODE
(TA = 25°C ± 5°C)
Mode
CE
OE
A0~A15
VPP
VDD
O0~O7
X1
VDD2
5.0V
DOUT
Read Mode
X1
Output Disable Mode
VIH
VIH
X1
VDD2
5.0V
Hi-Z
Programming Mode
VIL
VIH
X1
VPP2
VDD2
DIN
Program Verify
X1
X1
VPP2
VDD2
DOUT
1. X = Either VIL or VIH.
2. See DC Characteristics Table for VDD and VPP voltage during programming.
DEVICE CHARACTERISTICS
(VSS=0V, TA = 25°C ± 5°C)
Symbol
Item
Min
Typ
Max
Unit
VPP
Quick Pulse Programming
11.50
11.75
12.0
V
VDD1
Quick Pulse Programming
5.75
6.0
6.25
V
IPP2
VPP supply current
50
mA
IDD2
VDD supply current
30
mA
VIH
Input high voltage
VIL
Input low voltage
VOH
Output high voltage
VOL
Output low voltage
IIL
Input leakage current
0.8VDD
Test condition
CE=VIL
V
0.2VDD
VDD-0.1
V
V
IOH= -2.5mA
0.4
V
IOL= 2.1mA
5
µA
1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. The maximum current value is with outputs O0 to O7 unloaded.
FEB. 2000 Ver 1.00
65
GMS82512/16/24
HYUNDAI MicroElectronics
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from H to L
Will be changing
from H to L
May change
from L to H
Will be changing
from L to H
Do not care any
change permitted
Changing state
unknown
Does not apply
Center line is
high impedance “Off” state
READING WAVEFORMS
VIH
Addresses
Addresses Valid
VIL
See note (2)
VIH
OE
VIL
tAS
tOE
tDH
VIH
High-Z
Output
Valid Output
VIL
1. The input timing reference level is 1.0V for a VIL and 4.0V for a VIH at VDD=5.0V.
2. To read the output data, transition requires on the OE form the high to the low after address setup time tAS.
66
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
PROGRAMMING ALGORITHM WAVEFORMS
Program
Verify
Program
VIH
Addresses
Addresses Valid
VIL
tAS
tAH
VIH
Data In/Out
High-Z
Data in Stable
Data out valid
VIL
tDH
tDS
tDFP
12.75V
VPP
VDD
tVPS
6.25V
VDD
5.0V
tVDS
VIH
CE
VIL
tPW
tOES
tOE
VIH
OE
VIL
1. The input timing reference level is 1.0V for a VIL and 4.0V for a VIH at VDD=5.0V.
FEB. 2000 Ver 1.00
67
GMS82512/16/24
HYUNDAI MicroElectronics
AC READING CHARACTERISTICS
(VSS=0V, TA = 25°C ± 5°C)
Symbol
Item
tAS
Address setup time
tOE
Quick Pulse Programming
tDH
VPP supply current
Min
Typ
Max
Unit
Test condition
µs
2
0
200
ns
50
ns
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
AC PROGRAMMING CHARACTERISTICS
(VSS=0V, TA = 25°C ± 5°C)
Symbol
Item
Min
Typ
Max
Unit
Address setup time
2
µs
tOES
OE setup time
2
µs
tDS
Data setup time
2
µs
tAH
Address hold time
0
µs
tDH
Data hold time
2
µs
tDFP
Output delay disable time
0
tVPS
VPP setup time
2
µs
tVDS
VDD setup time
2
µs
tPW
Program pulse width
95
tOE
Data output delay time
tAS
130
100
Test condition*
ns
105
µs
150
ns
* AC CONDITION OF TEST
Input Rise and Fall Times (10% to 90%) ........................... 20ns
Input Pulse Levels ............................................................. 0.45V to 4.55V
Input Timing Reference Level............................................ 1.0V to 4.0V
Output Timing Reference Level ......................................... 1.0V to 4.0V
VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
68
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
START
ADDRESS=FIRST LOCATION
5V
5V
VCC=6.0V
VPP=11.75
X=0
PROGRAM ONE 100µs PULSE
INCREMENT X
X=25?
YES
NO
FAIL
VERIFY
BYTE
VERIFY
ONE BYTE
FAIL
PASS
PASS
INCREMENT
ADDRESS
NO
LAST
ADDRESS?
YES
VCC=VPP=5.0V
COMPARE
ALL BYTES TO
ORIGINAL
DATA
FAIL
PASS
DEVICE
PASSED
DEVICE
FAILED
Table 20-1 Programming Algorithm
FEB. 2000 Ver 1.00
69
APPENDIX
GMS82512/16/24
HYUNDAI MicroElectronics
A. CONTROL REGISTER LIST
Address
Register Name
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00C0
R0 port data register
R0
R/W
Undefined
page 28
00C1
R0 port I/O direction register
R0DD
W
00000000
page 28
00C4
R2 port data register
R2
R/W
Undefined
page 28
00C5
R2 port I/O direction register
R2DD
W
00000000
page 28
00C6
R3 port data register
R3
R/W
Undefined
page 28
00C7
R3 port I/O direction register
R3DD
W
00000000
page 28
00C8
R4 port data register
R4
R/W
Undefined
page 29
00C9
R4 port I/O direction register
R4DD
W
- - - 00000
page 29
00CA
R5 port data register
R5
R/W
Undefined
page 30
00CB
R5 port I/O direction register
R5DD
W
- - 00 - - - -
page 30
00CC
R6 port data register
R6
R/W
Undefined
page 30
00CD
R6 port I/O direction register
R6DD
W
0000 - - - -
page 30
00D0
R4 port mode register
PMR4
W
- - - 0 0 0 0 0 page 29, page 53
00D1
R5 port mode register
PMR5
W
- - 0 0 - - - - page 30, page 45
Basic interval timer mode register
BITR
R
Undefined
page 32
CKCTLR
W
- - 010111
page 32
WDTR
W
- 0111111
page 54
00D3
00E0
Watchdog Timer Register
00E2
Timer mode register 0
TM0
R/W
00000000
page 34
00E3
Timer mode register 2
TM2
R/W
00000000
page 34
Timer 0 data register
TDR0
W
Undefined
page 34
T0
R
Undefined
page 34
TDR1
W
Undefined
page 34
T1
R
Undefined
page 34
TDR2
W
Undefined
page 34
T2
R
Undefined
page 34
TDR3
W
Undefined
page 34
T3
R
Undefined
page 34
00E4
00E5
00E6
00E7
i
Clock control register
Timer 0 counter register
Timer 1 data register
Timer 1 counter register
Timer 2 data register
Timer 2 counter register
Timer 3 data register
Timer 3 counter register
00E8
A/D converter mode register
ADCM
R/W
- - 000001
page 44
00E9
A/D converter data register
ADR
R
Undefined
page 44
00EC
Buzzer driver register
BUR
W
Undefined
page 45
00F4
Interrupt enable register low
IENL
R/W
000 - - - - -
page 48
00F5
Interrupt request flag register low
IRQL
R/W
000 - - - - -
page 47
00F6
Interrupt enable register high
IENH
R/W
00000000
page 48
00F7
Interrupt request flag register high
IRQH
R/W
00000000
page 47
00F8
External interrupt edge selection register
IEDS
W
00000000
page 53
00F9
Power fail detection register
PFDR
R/W
- - - - 1100
page 61
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
B. SOFTWARE EXAMPLE
B.1 7-segment LED display
5V
VDD
TEST
330Ω × 7
5V
UP/DOWN S/W
R20/INT0
CLEAR S/W
R21/INT1
R00
R01
R02
R03
R04
R05
R06
LED Display
a
b
c
d
e
f
g
4.7kΩ
R23
2N2222
4.7kΩ
GND
R22
2N2222
VSS
GND
GMS82512/16/24
;*****************************************************************************
; Title:
GMS82516 (GMS800 Series) Demonstration Program
*
; Company:
HYUNDAI Micro Electronics
*
; Contents:
Decimal Up/Down Counter
*
; Programmer:
HME MCU application team
*
;*****************************************************************************
;
;******** DEFINE
I/O PORT & FUNCTION REGISTER ADDRESS *********
;
R0
EQU
0C0H
;port R0 register
R0DD
EQU
0C1H
;port R0 data I/O direction register
;
R2
EQU
0C4H
;port R2 register
R2DD
EQU
0C5H
;port R2 data I/O direction register
;
R3
EQU
0C6H
;port R3 register
R3DD
EQU
0C7H
;port R3 data I/O direction register
;
R4
EQU
0C8H
;port R4 register
R4DD
EQU
0C9H
;port R4 data I/O direction register
;
R5
EQU
0CAH
;port R5 register
R5DD
EQU
0CBH
;port R5 data I/O direction register
;
R6
EQU
0CCH
;port R6 register
R6DD
EQU
0CDH
;port R6 data I/O direction register
;
PMR4
EQU
0D0H
;port R4 mode register
EC0S
EQU
4,0D0H
;event counter 0 selection
INT3S
EQU
3,0D0H
;external int.3 selection
INT2S
EQU
2,0D0H
;external int.2 selection
INT1S
EQU
1,0D0H
;external int.1 selection
FEB. 2000 Ver 1.00
ii
GMS82512/16/24
INT0S
EQU
;
PMR5
EQU
BUZS
EQU
WDTS
EQU
;
CKCTLR
EQU
BITR
EQU
;
WDTR
EQU
;
TM0
EQU
TM2
EQU
;
TDR0
EQU
TDR1
EQU
TDR2
EQU
TDR3
EQU
;
ADCM
EQU
ADR
EQU
;
BUR
EQU
;
IENL
EQU
AE
EQU
WDTE
EQU
BITE
EQU
;
IRQL
EQU
AR
EQU
WDTRF
EQU
BITRF
EQU
;
IENH
EQU
INT0E
EQU
INT1E
EQU
INT2E
EQU
INT3E
EQU
T0E
EQU
T1E
EQU
T2E
EQU
T3E
EQU
;
IRQH
EQU
INT0R
EQU
INT1R
EQU
INT2R
EQU
INT3R
EQU
T0R
EQU
T1R
EQU
T2R
EQU
T3R
EQU
;
IEDS
EQU
PFDR
EQU
;
;*********** MACRO
;
REG_SAVE
MACRO
PUSH
PUSH
PUSH
ENDM
;
REG_RESTORE
MACRO
POP
POP
POP
ENDM
HYUNDAI MicroElectronics
0,0D0H
;external int.0 selection
0D1H
5,0D1H
4,0D1H
;port R5 mode register
;buzzer selection
;watch dog timer selection
0D3H
0D3H
;clock control register
;basic interval timer register
0E0H
;watch dog timer register
0E2H
0E3H
;timer0 mode register
;timer2 mode register
0E4H
0E5H
0E6H
0E7H
;tomer0
;tomer1
;tomer2
;tomer3
0E8H
0E9H
;A/D Converter mode register
;A/D con. register
0ECH
;buzzer data register
0F4H
7,0F4H
6,0F4H
5,0F4H
;int. enable register low
;A/D con. int. enable
;W.D.T. int. enable
;B.I.T. int. enable
0F5H
7,0F5H
6,0F5H
5,0F5H
;int. request flag register low
;A/D con. int. request flag
;W.D.T. int. request flag
;B.I.T. int. request flag
0F6H
7,0F6H
6,0F6H
5,0F6H
4,0F6H
3,0F6H
2,0F6H
1,0F6H
0,0F6H
;int. enable register high
;external int.0 enable
;external int.1 enable
;external int.2 enable
;external int.3 enable
;timer0 int. enable
;timer1 int. enable
;timer2 int. enable
;timer3 int. enable
0F7H
7,0F7H
6,0F7H
5,0F7H
4,0F7H
3,0F7H
2,0F7H
1,0F7H
0,0F7H
;int. request flag register high
;external int.0 request flag
;external int.1 request flag
;external int.2 request flag
;external int.3 request flag
;timer0 int. request flag
;timer1 int. request flag
;timer2 int. request flag
;timer3 int. request flag
0F8H
0F9H
;external int. edge selection
;power fail detection register
data
data
data
data
register
register
register
register
DEFINITION ************
;Save Registers to Stacks
A
X
Y
;Restore Register from Stacks
Y
X
A
;
;*********** CONSTANT DEFINITION ***********
;
SEG_PORT
EQU
R0
;7-Segment Output Port
STROBE_PORT
EQU
R2
;Strobe Signal Port
;
;**************************************************************************
;
RAM
ALLOCATION
*
;**************************************************************************
iii
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
DIGIT10
DS
1
;DIG10 Display Data
DIGIT1
DS
1
;Seg1 Display Data
STROBE
DS
1
;Strobe Signal Data
TMR_500mS
DS
1
;500ms Time Counter
FLAGS
DS
1
;Function Flags
UP_F
EQU
0,FLAGS
;1=Down,0=Up
F_500ms
EQU
1,FLAGS
;
;
;**************************************************************************
;
INTERRUPT
VECTOR
TABLE *
;**************************************************************************
;
ORG0FFE4H
DW
NOT_USED
; Serial I/O
DW
NOT_USED
; Basic Interval Timer
DW
NOT_USED
; Watch Dog Timer
DW
NOT_USED
; A/D CON.
DW
NOT_USED
; Timer-3
DW
NOT_USED
; Timer-2
DW
NOT_USED
; Timer-1
DW
TMR0_INT
; Timer-0
DW
NOT_USED
; Int.3
DW
NOT_USED
; Int.2
DW
INT_1
; Int.1
DW
INT_0
; Int.0
DW
NOT_USED
;
DW
RESET
; Reset
;
;**************************************************************************
;
MAIN
PROGRAM
*
;**************************************************************************
;
ORG
0C000H
;Program Start Address
;
RESET:
DI
;Disable All Interrupts
LDX
#0
RAM_CLR:
LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
;M(X) <- A, then X <- X+1
CMPX
#0C0H
;X = #0C0H ?
BNE
RAM_CLR
;
LDX
#0FEH
;Stack Pointer Initial
TXSP
;SP. <- #0FEH
Loop:
LDM
LDM
R0,#0
R2,#0
;I/O Port Data Clear
LDM
LDM
R0DD,#0FFH
R2DD,#00FH
;7-Seg. Data Output Mode
;7-Seg. Strobe Output Mode
LDM
STROBE,#0000_1011B
LDM
TDR0,#250
LDM
TM0,#0001_1111B
LDM
IRQH,#0
LDM
IRQL,#0
LDM
IENH,#1100_1000B
LDM
IENL,#00H
LDM
IEDS,#0101_0101B
LDM
PMR4,#03H
SET1
UP_F
EI
;
nop
IF
F_500ms == 1
clr1
F_500ms
call
INC_DEC
ENDIF
jmp
Loop
;8us x 250 = 2000us
;Timer0(8bit),8us,Start Count-up
;Clear All Interrupts Requeat Flags
;EnableT0,Int0,Int1,Interrupt
;External Int. Falling edge select
;General port OR Int?
;Enable Interrupts
;
;***********************************************
; Subject:
Inc. or Dec. two digits
*
;***********************************************
; Entry:
UP_F
*
; Return:
UP_F=1, Increment two digits
*
;
UP_F=0, Decrement two digits
*
;***********************************************
;
INC_DEC:
BBC
UP_F,DOWN
;Check Down mode or Up mode
;
FEB. 2000 Ver 1.00
iv
GMS82512/16/24
DOWN:
;**************************
;*
Up Count
*
;**************************
;
SETC
LDA
#0
ADC
DIGIT1
IF
A == #0AH
setc
lda
#0
ENDIF
STA
DIGIT1
;
LDA
#0
ADC
DIGIT10
IF
A == #10
lda
#0
ENDIF
STA
DIGIT10
RET
;
;**************************
;*
Down Count
*
;**************************
;
clrc
lda
DIGIT1
sbc
#0
IF
A == #0FFH
lda
#9
clrc
ELSE
setc
ENDIF
sta
DIGIT1
;
lda
DIGIT10
sbc
#0
IF
A == #0FFH
lda
#9
ENDIF
STA
DIGIT10
RET
HYUNDAI MicroElectronics
; DIGIT1 <- DIGIT1 + 1
; Store result into DIGIT1
; When Overflow is set,
; DIGIT10 <- DIGIT10 + 1
; DIGIT1 <- DIGIT1 - 1
; Store result into DIGIT1
; When Overflow is set,
; DIGIT10 <- DIGIT10 - 1
;
;**************************************************************************
;
TIMER0,INTERRUPT ROUTINE(2ms)& INT0,INT1
*
;**************************************************************************
;
TMR0_INT:
REG_SAVE
;Save Registers to Stacks
CALL
DSPLY
;Segments Data Port Output
CALL
Make_500msFalg
;250ms mesurement
REG_RESTORE
;Restore Registers from Stacks
RETI
;
;**************************************************************************
;
EXTERNAL INTERRUPT 0 (UP/DOWN KEY)
*
;**************************************************************************
;
INT_0:
NOT1
UP_F
;INT0 Service routine
RETI
;Toggle the Up/Down mode
;
;**************************************************************************
;
EXTERNAL INTERRUPT 1 (CLEAR KEY)
*
;**************************************************************************
;
INT_1:
LDM
DIGIT1,#0
;INT1 Service routine
LDM
DIGIT10,#0
LDM
TMR_500MS,#0
;0.5Sec Restart
RETI
;
;***********************************************************************
; Subject:
Seven Segment Display (DSPLY)
*
;***********************************************************************
; Entry:
DIGIT10 or DIGIT1
*
; Return:
Output SEG_PORT (R00~R07),
*
;
Strobe_port (R22,R23)
*
; Scratch:
STROBE
*
;***********************************************************************
; Description: After read internal RAM data, output data to the port *
v
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
;***********************************************************************
;
DSPLY:
LDM
STROBE_PORT,#03H
;Segment All Turn Off
NOT1
STROBE.2
;Toggle strobe0
NOT1
STROBE.3
;Toggle strobe1
IF
ldy
ELSE
ldy
ENDIF
STROBE.3 = 1
DIGIT1
LDA
STA
LDA
STA
RET
;Test if R23 is high.
DIGIT10
!FONT+Y
SEG_PORT
STROBE
STROBE_PORT
;Segment Data output
;Current Digit Turn On
;Quit
;
;***********************************************
; Subject:
Set falg at every 500ms
*
;***********************************************
; Entry:
None
*
; Return:
500ms flag (F_500ms)
*
;***********************************************
;
Make_500msFalg:
INC
TMR_500MS
;count up every 2ms
LDA
TMR_500MS
IF
A == #250
;Compare 0.5S
ldm
TMR_500MS,#0
;clear 0.5sec. counter
set1
F_500ms
;set 0.5sec. flag
ENDIF
RET
;
;**************************************************************************
;
7-SEGMENT PATTERN DATA
*
;
_a_
*
;
f | g |b
*
;
|---|
*
;
e |___|c
*
;
d
.h
*
;**************************************************************************
;
FONT
Segment:
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
hgfe dcba
0011_1111B
0000_0110B
0101_1011B
0100_1111B
0110_0110B
0110_1101B
0111_1100B
0000_0111B
0111_1111B
0110_0111B
To be displayed Digit Number
;
;
;
;
;
;
;
;
;
;
0
1
2
3
4
5
6
7
8
9
;
;**************************************************************************
;
NOT_USED:
nop
;Discard Unexpected Interrupts
reti
;
END
;Notice Program End
FEB. 2000 Ver 1.00
vi
GMS82512/16/24
HYUNDAI MicroElectronics
C. INSTRUCTION
C.1 Terminology List
Terminology
A
X
Y
PSW
C
V
N
I
Z
H
B
G
PC
SP
#imm
dp
!abs
[ ]
{ }
{ }+
.bit
A.bit
dp.bit
M.bit
rel
upage
n
x
y
H,h
B,b
+
x
=
⊕
vii
Description
A - Register
X - Register
Y - Register
Program Status Word
Carry Flag of PSW
Overflow Flag of PSW
Negative Flag of PSW
Master Interrupt Enable Flag of PSW
Zero Flag of PSW
Half Carry Flag of PSW
Break Flag of PSW (software interrupt)
G flag of PSW(Direct Page)
Program Counter
Stack Pointer
8-Bit Immediate Data
Direct Page Offset Address
Absolute Address
Indirect Address
Register Indirect Address
Register Indirect Address, Register Auto-Increment
Bit Position
Bit Position of A-Register
Bit Position of Direct Page Memory
Bit Position of Memory (000H ~ 0FFFH)
Relative Addressing Data
U - Page(0FF00H ~ 0FFFFH) Offset Address
Table CALL Number (0 ~ 15)
Indicate Upper Nibble of OP code
0
Bit Position
1
Bit Position
Indicate Upper Nibble of OP code
Assignment / Transfer / Shift Left
Shift Right
Exchange
Hexadecimal
Binary
Addition
Multiplication
Equal
Logical AND
Exclusive OR
D,d
( )
/
v
(overline)
Decimal
Contents of
Subtraction
Division
Not Equal
Logical OR
Logical NOT
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
C.2 Instruction Map
LOW
00000
00
00001
01
00010
02
00011
03
00100
04
00101
05
00110
06
00111
07
01000
08
01001
09
01010
0A
01011
0B
01100
0C
01101
0D
01110
0E
000
-
SET1
dp.bit
BBS
A.bit,rel
BBS
dp.bit,rel
001
CLRC
//
//
//
010
CLRG
//
//
//
011
DI
//
//
//
CLRV
//
//
//
101
SETC
//
//
//
SETG
//
//
//
111
EI
//
//
//
ADC
dp+X
SBC
dp+X
CMP
dp+X
OR
dp+X
AND
dp+X
EOR
dp+X
LDA
dp+X
STA
dp+X
ADC
!abs
SBC
!abs
CMP
!abs
OR
!abs
AND
!abs
EOR
!abs
LDA
!abs
STA
!abs
ASL
A
ROL
A
LSR
A
ROR
A
INC
A
DEC
A
110
ADC
dp
SBC
dp
CMP
dp
OR
dp
AND
dp
EOR
dp
LDA
dp
STA
dp
ASL
dp
ROL
dp
LSR
dp
ROR
dp
INC
dp
DEC
dp
LDY
dp
STY
dp
TCALL
0
TCALL
2
TCALL
4
TCALL
6
TCALL
8
TCALL
10
TCALL
12
TCALL
14
SETA1
.bit
CLRA1
.bit
NOT1
M.bit
OR1
OR1B
AND1
AND1B
EOR1
EOR1B
LDC
LDCB
STC
M.bit
BIT
dp
COM
dp
TST
dp
CMPX
dp
CMPY
dp
DBNE
dp
LDX
dp
STX
dp
POP
A
POP
X
POP
Y
POP
PSW
CBNE
dp+X
XMA
dp+X
LDX
dp+Y
STX
dp+Y
PUSH
A
PUSH
X
PUSH
Y
PUSH
PSW
100
ADC
#imm
SBC
#imm
CMP
#imm
OR
#imm
AND
#imm
EOR
#imm
LDA
#imm
LDM
dp,#imm
10000
10
10001
11
10010
12
10011
13
10100
14
10101
15
10110
16
10111
17
11000
18
11001
19
11010
1A
11011
1B
11100
1C
11101
1D
11110
1E
BPL
rel
BVC
rel
BCC
rel
BNE
rel
BMI
rel
BVS
rel
BCS
rel
BEQ
rel
CLR1
dp.bit
BBC
A.bit,rel
BBC
dp.bit,rel
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
ASL
dp+X
ROL
dp+X
LSR
dp+X
ROR
dp+X
INC
dp+X
DEC
dp+X
LDY
dp+X
STY
dp+X
TCALL
1
TCALL
3
TCALL
5
TCALL
7
TCALL
9
TCALL
11
TCALL
13
TCALL
15
BIT
!abs
TEST
!abs
TCLR1
!abs
CMPX
!abs
CMPY
!abs
XMA
dp
LDX
!abs
STX
!abs
ADDW
dp
SUBW
dp
CMPW
dp
LDYA
dp
INCW
dp
DECW
dp
STYA
dp
CBNE
dp
DAA
//
ASL
!abs
ROL
!abs
LSR
!abs
ROR
!abs
INC
!abs
DEC
!abs
LDY
!abs
STY
!abs
XAY
//
ADC
[dp]+Y
SBC
[dp]+Y
CMP
[dp]+Y
OR
[dp]+Y
AND
[dp]+Y
EOR
[dp]+Y
LDA
[dp]+Y
STA
[dp]+Y
LDX
#imm
LDY
#imm
CMPX
#imm
CMPY
#imm
INC
Y
DEC
Y
//
ADC
[dp+X]
SBC
[dp+X]
CMP
[dp+X]
OR
[dp+X]
AND
[dp+X]
EOR
[dp+X]
LDA
[dp+X]
STA
[dp+X]
JMP
[!abs]
JMP
[dp]
CALL
[dp]
//
ADC
!abs+Y
SBC
!abs+Y
CMP
!abs+Y
OR
!abs+Y
AND
!abs+Y
EOR
!abs+Y
LDA
!abs+Y
STA
!abs+Y
JMP
!abs
CALL
!abs
//
ADC
{X}
SBC
{X}
CMP
{X}
OR
{X}
AND
{X}
EOR
{X}
LDA
{X}
STA
{X}
XYX
NOP
HIGH
LOW
HIGH
000
001
010
011
100
101
110
111
FEB. 2000 Ver 1.00
TXA
TAX
MUL
DBNE
Y
DIV
XMA
{X}
LDA
{X}+
STA
{X}+
TXSP
TSPX
01111
0F
BRK
BRA
rel
PCALL
Upage
RET
INC
X
DEC
X
XCN
DAS
XAS
STOP
11111
1F
RETI
TAY
TYA
viii
GMS82512/16/24
HYUNDAI MicroElectronics
C.3 Alphabetic order table of instruction
OP
CODE
04
05
06
07
15
16
17
14
1D
84
85
86
87
95
96
97
94
8B
8B
08
09
19
18
y2
y3
x2
x3
BYTE
NO.
2
2
2
3
3
2
2
1
2
2
2
2
3
3
2
2
1
3
3
1
2
2
3
2
3
2
3
CYCLE
NO
2
3
4
4
5
6
6
3
5
2
3
4
4
5
6
6
3
4
4
2
4
5
5
4/6
5/7
4/6
5/7
BCC rel
50
2
2/4
29
30
31
32
BCS rel
BEQ rel
BIT dp
BIT !abs
D0
F0
0C
1C
2
2
2
3
2/4
2/4
4
5
33
34
35
36
37
BMI
BNE
BPL
BRA
BRK
90
70
10
2F
0F
2
2
2
2
1
2/4
2/4
2/4
4
8
NO.
MNENONIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
ADC #imm
ADC dp
ADC dp + X
ADC !abs
ADC !abs+Y
ADC [dp+X]
ADC [dp]+Y
ADC {X}
ADDW dp
AND #imm
AND dp
AND dp + X
AND !abs
AND !abs+Y
AND [dp+X]
AND [dp] + Y
AND {X}
AND1 M.bit
AND1B M.bit
ASL A
ASL dp
ASL dp + X
ASL !abs
BBC A.bit,rel
BBC dp.bit,rel
BBS A.bit,rel
BBS dp.bit,rel
28
rel
rel
rel
rel
FLAG
NVGBHIZC
OPERATION
Add with carry.
A A + (M) + C
NV - - H - ZC
16-bits add without carry : YA YA + (dp+1)(dp)
Logical AND
A A (M)
N-----Z-
Bit AND C-flag : C C (M.bit)
Bit AND C-flag and NOT : C C (M.bit)
Arithmetic shift left
C
-------C
-------C
7 6 5 4 3 2 1 0
N - - - - - ZC
"0"
Branch if bit clear :
if(bit) = 0, then PC PC + rel
Branch if bit clear :
if(bit) = 1, then PC PC + rel
Branch if carry bit clear :
if(C) = 0, then PC PC + rel
Branch if carry bit set : If (C) =1, then PC PC + rel
Branch if equal : if (Z) = 1, then PC PC + rel
Bit test A with memory :
Z A M, N (M7), V (M6)
Branch if munus : if (N) = 1, then PC PC + rel
Branch if not equal : if (Z) = 0, then PC PC + rel
Branch if not minus : if (N) = 0, then PC PC + rel
Branch always : PC PC + rel
Software interrupt:
B “1”, M(SP) (PCH), SP SP - 1,
M(s) (PCL), SP S - 1, M(SP) PSW,
38
BVC rel
30
2
2/4
39
BVS rel
B0
2
2/4
ix
NV - - H - ZC
SP SP - 1, PCL (0FFDEH), PCH (0FFDFH)
Branch if overflow bit clear :
If (V) = 0, then PC PC + rel
Branch if overflow bit set :
If (V) = 1, then PC PC + rel
--------------MM - - - - Z --------------MM - - - - Z -----------------------------
---1-0--
---------------
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
NO.
MNENONIC
GMS82512/16/24
OP
CODE
3B
5F
BYTE
NO.
3
2
CYCLE
NO
8
8
Subroutine call
M(SP)(PCH), SPSP-1, M(SP)(PCL), SPSP-1
OPERATION
FLAG
NVGBHIZC
40
41
CALL !abs
CALL [dp]
42
FD
3
5/7
if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1)
Compare and branch if not equal ;
8D
3
6/8
If A ≠ (M), then PC PC + rel.
--------
44
45
46
47
48
49
50
51
52
53
54
55
56
57
CBNE dp,rel
CBNE dp + X,
rel
CLR1 dp.bit
CLR1A A.bit
CLRC
CLRG
CLRV
CMP #imm
CMP dp
CMP dp + X
CMP !abs
CMP !abs + Y
CMP [dp + X]
CMP [dp] + Y
CMP {X}
CMPW dp
y1
2B
20
40
80
44
45
46
47
55
56
57
54
5D
2
2
1
1
1
2
2
2
3
3
2
2
1
2
4
2
2
2
2
2
3
4
4
5
6
6
3
4
Clear bit : (M.bit) “0”
Clear A.bit : (A.bit) “0”
Clear C-flag : C “0”
Clear G-flag : G “0”
Clear V-flag : V “0”
Compare accumulator contents with memory contents
A - (M)
---------------------0
--0-----0--0---
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
CMPX #imm
CMPX dp
CMPX !abs
CMPY #imm
CMPY dp
CMPY !abs
COM dp
DAA
DAS
DBNE dp,rel
DBNE Y,rel
DEC A
DEC dp
DEC dp + X
DEC !abs
DEC X
DEC Y
DECW dp
DI
DIV
EI
5E
6C
7C
7E
8C
9C
2C
DF
CF
AC
7B
A8
A9
B9
B8
AF
BE
BD
60
9B
E0
2
2
3
2
2
3
2
1
1
3
2
1
2
2
3
1
1
2
1
1
1
2
3
4
2
3
4
4
3
3
5/7
4/6
2
4
5
5
2
2
6
3
12
3
43
FEB. 2000 Ver 1.00
--------
N - - - - - ZC
Compare YA contents with memory pair contents :
YA - (dp+1)(dp)
Compare X contents with memory contents
X - (M)
Compare Y contents with memory contents
Y - (M)
1’s complement : (dp) (dp)
Decimal adjust for addition
Decimal adjust for substraction
Decrement and branch if not equal :
if (M) ≠ 0, then PC PC + rel.
Decrement
MM-1
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC
N-----ZN - - - - - ZC
N - - - - - ZC
--------
N-----Z-
Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1
Disable interrupts : I “0”
Divide : YA A Q:A, R:Y
Enable interrupts : I “1”
N-----Z-----0-NV - - H - Z -----1--
x
GMS82512/16/24
NO.
MNENONIC
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
EOR #imm
EOR dp
EOR dp + X
EOR !abs
EOR !abs + Y
EOR [ dp + X]
EOR [dp] + Y
EOR {X}
EOR1 M.bit
EOR1B M.bit
INC A
INC dp
INC dp + X
INC !abs
INC X
INC Y
INCW dp
JMP !abs
JMP [!abs]
JMP [dp]
LDA #imm
LDA dp
LDA dp + X
LDA !abs
LDA !abs + Y
LDA [dp + X]
LDA [dp]+Y
LDA {X}
LDA {X}+
LDC M.bit
LDCB M.bit
LDM dp,#imm
LDX #imm
LDX dp
LDX dp + Y
LDX !abs
LDY #imm
LDY dp
LDY dp + Y
LDY !abs
LDYA dp
LSR A
LSR dp
LSR dp + X
LSR !abs
MUL
NOP
NOT1 M.bit
xi
HYUNDAI MicroElectronics
OP
CODE
A4
A5
A6
A7
B5
96
97
94
AB
AB
88
89
99
98
8F
9E
9D
1B
1F
3F
C4
C5
C6
C7
D5
D6
D7
D4
DB
CB
CB
E4
1E
CC
CD
DC
3E
C9
D9
D8
7D
48
49
59
58
5B
FF
4B
BYTE
NO.
2
2
2
3
3
2
2
1
3
3
1
2
2
3
1
1
2
3
3
2
2
2
2
3
3
2
2
1
1
3
3
3
2
2
2
3
2
2
2
3
2
1
2
2
3
1
1
3
CYCLE
NO
2
3
4
4
5
6
6
3
5
5
2
4
5
5
2
2
6
3
5
4
2
3
4
4
5
6
6
3
4
4
4
5
2
3
4
4
2
3
4
4
5
2
4
5
5
9
2
5
FLAG
NVGBHIZC
OPERATION
Exclusive OR
A A ⊕ (M)
N-----Z-
Bit exclusive-OR C-flag : C C ⊕ (M.bit)
Bit exclusive-OR C-flag and NOT : C C ⊕ (M.bit)
Increment
(M) (M) + 1
-------C
-------C
N - - - - - ZC
N-----Z-
Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 N - - - - - Z Unconditional jump
-------PC jump address
Load accumulator
A (M)
N-----Z-
X-register auto-increment : A (M), X X + 1
Load C-flag : C (M.bit)
Load C-flag with NOT : C (M.bit)
Load memory with immediate data : (M) imm
Load X-register
X (M)
N-----Z-
Load X-register
Y (M)
N-----Z-
Load YA : YA (dp+1)(dp)
Logical shift right
7 6 5 4 3 2 1 0 C
"0" Multiply : YA Y x A
No operation
Bit complement : (M.bit) (M.bit)
-------C
-------C
--------
N-----ZN - - - - - ZC
N-----Z---------------
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
NO.
MNENONIC
127
128
129
130
131
132
133
134
135
136
OR #imm
OR dp
OR dp + X
OR !abs
OR !abs + Y
OR [dp +X}
OR [dp] + Y
OR {X}
OR1 M.bit
OR1B M.bit
137
PCALL
GMS82512/16/24
OP
CODE
64
65
66
67
75
76
77
74
6B
6B
BYTE
NO.
2
2
2
3
3
2
2
1
3
3
CYCLE
NO
2
3
4
4
5
6
6
3
5
5
4F
2
6
138
139
140
141
142
143
144
145
146
POP A
POP X
POP Y
POP PSW
PUSH A
PUSH X
PUSH Y
PUSH PSW
RET
0D
2D
4D
6D
0E
2E
4E
6E
6F
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
5
147
RETI
7F
1
6
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
ROL A
ROL dp
ROL dp + X
ROL !abs
ROR A
ROR dp
ROR dp + X
ROR !abs
SBC #imm
SBC dp
SBC dp + X
SBC !abs
SBC !abs + Y
SBC [dp + X]
SBC [dp] + Y
SBC {X}
SET1 dp.bit
SETA1 A.bit
SETC
SETG
FEB. 2000 Ver 1.00
28
29
39
38
68
69
79
78
24
25
26
27
35
36
37
34
x1
0B
A0
C0
1
2
2
3
1
2
2
3
2
2
2
3
3
2
2
1
2
2
1
1
2
4
5
5
2
4
5
5
2
3
4
4
5
6
6
3
4
2
2
2
OPERATION
FLAG
NVGBHIZC
Logical OR
A A V (M)
N-----Z-
Bit OR C-flag : C C V (M.bit)
Bit OR C-flag and NOT : C C V (M.bit)
U-page call : M(SP) (PCH), SP SP -1,
-------C
-------C
M(SP) (PCL), SP SP -1,
--------
PCL (upage), PCH "OFFH"
Pop from stack
SP SP + 1, Reg. M(SP)
-------(restored)
Push to stack
M(SP) Reg.
SP SP - 1
Return from subroutine :
SP SP+1, PCL M(SP), SP SP+1, PCH M(SP)
Return from interrupt :
SP SP+1, PSW M(SP), SP SP+1,PCL M(SP),
--------
--------
(restored)
SP SP+1, PCH M(SP)
Rotate left through carry
C
7 6 5 4 3 2 1 0
N - - - - - ZC
Rotate right through carry
7 6 5 4 3 2 1 0
C
N - - - - - ZC
Substract with carry
A A - (M) - (C)
NV - - HZC
Set bit : (M.bit) “1”
Set A.bit : (A.bit) “1”
Set C-flag : C “1”
Set G-flag : G “1”
---------------------1
--1-----
xii
GMS82512/16/24
HYUNDAI MicroElectronics
STA dp
STA dp + X
STA !abs
STA !abs + Y
STA [dp + X]
STA [dp] + Y
STA {X}
STA {X}+
STC M.bit
STOP
STX dp
STX dp + Y
STX !abs
STY dp
STY dp + X
STY !abs
STYA dp
SUBW dp
TAX
TAY
TCALL n
OP
CODE
E5
E6
E7
F5
F6
F7
F4
FB
EB
00
EC
ED
FC
E9
F9
F8
DD
3D
E8
9F
nA
BYTE
NO.
2
2
3
3
2
2
1
1
3
1
2
2
3
2
2
3
2
2
1
1
1
CYCLE
NO
3
4
4
5
6
6
3
4
6
3
4
5
5
4
5
5
5
5
2
2
8
189
190
191
TCLR1 !abs
TSET1 !abs
TSPX
5C
3C
AE
3
3
1
6
6
2
192
TST dp
4C
2
3
193
194
195
TXA
TXSP
TYA
C8
8E
BF
1
1
1
2
2
2
196
XAX
EE
1
4
197
198
XAY
XCN
DE
CE
1
1
4
5
199
200
201
202
XMA dp
XMA dp + X
XMA {X}
XYX
BC
AD
BB
FE
2
2
1
1
5
6
5
4
NO.
MNENONIC
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
FLAG
NVGBHIZC
OPERATION
Store accumulator contents in memory
(M) A
--------
X-register auto-increment : (M) A, X X + 1
Store C-flag : (M.bit) C
Stop mode (halt CPU, stop oscillator)
Store X-register contents in memory
(M) X
Store Y-register contents in memory
(M) Y
----------------------
--------
-------Store YA : (dp+1)(dp) YA
16-bits substract without carry : YA YA - (dp+1)(dp) NV - - H - ZC
N-----ZTransfer accumulator contents to X-register : X A
N-----ZTransfer accumulator contents to Y-register : Y A
Table call :
M(SP) (PCH), SP SP -1,
-------M(SP) (PCL), SP SP -1
PCL (Table vector L), PCH (Table vector H)
xiii
Test and clear bits with A :A - (M), (M) (M) (A)
Test and set bits with A :A - (M), (M) (M) V (A)
Transfer stack-pointer contents to X-register : X SP
Test memory contents for negative or zero : (dp) 00H
N-----ZN-----ZN-----Z-
Transfer X-register contents to accumulator : A X
Transfer X-register contents to stack-pointer : SP X
Transfer Y-register contents to accumulator : A Y
Exchange X-register contents with accumulator : X A
Exchange Y-register contents with accumulator : YA
Exchange nibbles within the accumulator:
A7 ~ A4 A3 ~ A0
Exchange memory contents with accumulator
(M) A
N-----ZN-----ZN-----Z-
Exchange X-register contents with Y-register : X Y
N-----Z-
--------------N-----Z-
N-----Z--------
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
C.4 Instruction Table by Function
Arithmetic/Logic Operation
NO.
MNENONIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ADC #imm
ADC dp
ADC dp + X
ADC !abs
ADC !abs+Y
ADC [dp+X]
ADC [dp]+Y
ADC {X}
AND #imm
AND dp
AND dp + X
AND !abs
AND !abs+Y
AND [dp+X]
AND [dp] + Y
AND {X}
ASL A
ASL dp
ASL dp + X
ASL !abs
CMP #imm
CMP dp
CMP dp + X
CMP !abs
CMP !abs + Y
CMP [dp + X]
CMP [dp] + Y
CMP {X}
CMPX #imm
CMPX dp
CMPX !abs
CMPY #imm
CMPY dp
CMPY !abs
COM dp
DAA
DAS
DEC A
DEC dp
DEC dp + X
DEC !abs
DEC X
DEC Y
DIV
FEB. 2000 Ver 1.00
OP
CODE
04
05
06
07
15
16
17
14
84
85
86
87
95
96
97
94
08
09
19
18
44
45
46
47
55
56
57
54
5E
6C
7C
7E
8C
9C
2C
DF
CF
A8
A9
B9
B8
AF
BE
9B
BYTE
NO.
2
2
2
3
3
2
2
1
2
2
2
3
3
2
2
1
1
2
2
3
2
2
2
3
3
2
2
1
2
2
3
2
2
3
2
1
1
1
2
2
3
1
1
1
CYCLE
NO
2
3
4
4
5
6
6
3
2
3
4
4
5
6
6
3
2
4
5
5
2
3
4
4
5
6
6
3
2
3
4
2
3
4
4
3
3
2
4
5
5
2
2
12
OPERATION
FLAG
NVGBHIZC
Add with carry.
A A + (M) + C
NV - - H - ZC
Logical AND
A A (M)
N-----Z-
Arithmetic shift left
C
7 6 5 4 3 2 1 0
"0"
N - - - - - ZC
Compare accumulator contents with memory contents
A - (M)
N - - - - - ZC
Compare X contents with memory contents
X - (M)
N - - - - - ZC
Compare Y contents with memory contents
Y - (M)
N - - - - - ZC
1’s complement : (dp) (dp)
Decimal adjust for addition
Decimal adjust for substraction
Decrement
MM-1
N-----ZN - - - - - ZC
N - - - - - ZC
N-----Z-
Divide : YA A Q:A, R:Y
NV - - H - Z -
xiv
GMS82512/16/24
OP
CODE
A4
A5
A6
A7
B5
96
97
94
88
89
99
98
8F
9E
48
49
59
58
5B
64
65
66
67
75
76
77
74
28
29
39
38
68
69
79
78
24
25
26
27
35
36
37
34
BYTE
NO.
2
2
2
3
3
2
2
1
1
2
2
3
1
1
1
2
2
3
1
2
2
2
3
3
2
2
1
1
2
2
3
1
2
2
3
2
2
2
3
3
2
2
1
CYCLE
NO
2
3
4
4
5
6
6
3
2
4
5
5
2
2
2
4
5
5
9
2
3
4
4
5
6
6
3
2
4
5
5
2
4
5
5
2
3
4
4
5
6
6
3
TST dp
4C
2
3
XCN
CE
1
5
NO.
MNENONIC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
EOR #imm
EOR dp
EOR dp + X
EOR !abs
EOR !abs + Y
EOR [ dp + X]
EOR [dp] + Y
EOR {X}
INC A
INC dp
INC dp + X
INC !abs
INC X
INC Y
LSR A
LSR dp
LSR dp + X
LSR !abs
MUL
OR #imm
OR dp
OR dp + X
OR !abs
OR !abs + Y
OR [dp +X}
OR [dp] + Y
OR {X}
ROL A
ROL dp
ROL dp + X
ROL !abs
ROR A
ROR dp
ROR dp + X
ROR !abs
SBC #imm
SBC dp
SBC dp + X
SBC !abs
SBC !abs + Y
SBC [dp + X]
SBC [dp] + Y
SBC {X}
88
89
xv
HYUNDAI MicroElectronics
FLAG
NVGBHIZC
OPERATION
Exclusive OR
A A ⊕ (M)
N-----Z-
Increment
(M) (M) + 1
N - - - - - ZC
N-----Z-
Logical shift right
7 6 5 4 3 2 1 0 C
"0" N - - - - - ZC
Multiply : YA Y x A
Logical OR
A A V (M)
N-----Z-
N-----Z-
Rotate left through carry
C
N - - - - - ZC
7 6 5 4 3 2 1 0
Rotate right through carry
N - - - - - ZC
7 6 5 4 3 2 1 0
C
Substract with carry
A A - (M) - (C)
NV - - HZC
Test memory contents for negative or zero : (dp) 00H
Exchange nibbles within the accumulator:
A7 ~ A4 A3 ~ A0
N-----ZN-----Z-
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
Register / Memory Operation
OP
CODE
C4
C5
C6
C7
D5
D6
D7
D4
DB
E4
1E
CC
CD
DC
3E
C9
D9
D8
E5
E6
E7
F5
F6
F7
F4
FB
EC
ED
FC
E9
F9
F8
E8
9F
AE
C8
8E
BF
BYTE
NO.
2
2
2
3
3
2
2
1
1
3
2
2
2
3
2
2
2
3
2
2
3
3
2
2
1
1
2
2
3
2
2
3
1
1
1
1
1
1
CYCLE
NO
2
3
4
4
5
6
6
3
4
5
2
3
4
4
2
3
4
4
3
4
4
5
6
6
3
4
4
5
5
4
5
5
2
2
2
2
2
2
XAX
EE
1
4
XAY
XMA dp
XMA dp + X
XMA {X}
XYX
DE
BC
AD
BB
FE
1
2
2
1
1
4
5
6
5
4
NO.
MNENONIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LDA #imm
LDA dp
LDA dp + X
LDA !abs
LDA !abs + Y
LDA [dp + X]
LDA [dp]+Y
LDA {X}
LDA {X}+
LDM dp,#imm
LDX #imm
LDX dp
LDX dp + Y
LDX !abs
LDY #imm
LDY dp
LDY dp + Y
LDY !abs
STA dp
STA dp + X
STA !abs
STA !abs + Y
STA [dp + X]
STA [dp] + Y
STA {X}
STA {X}+
STX dp
STX dp + Y
STX !abs
STY dp
STY dp + X
STY !abs
TAX
TAY
TSPX
TXA
TXSP
TYA
39
40
41
42
43
44
FEB. 2000 Ver 1.00
OPERATION
FLAG
NVGBHIZC
Load accumulator
A (M)
N-----Z-
X-register auto-increment : A (M), X X + 1
Load memory with immediate data : (M) imm
Load X-register
X (M)
N-----Z-
Load X-register
Y (M)
N-----Z-
--------
Store accumulator contents in memory
(M) A
--------
X-register auto-increment : (M) A, X X + 1
Store X-register contents in memory
(M) X
--------
Store Y-register contents in memory
(M) Y
--------
Transfer accumulator contents to X-register : X A
Transfer accumulator contents to Y-register : Y A
Transfer stack-pointer contents to X-register : X SP
Transfer X-register contents to accumulator : A X
Transfer X-register contents to stack-pointer : SP X
Transfer Y-register contents to accumulator : A Y
Exchange X-register contents with accumulator : X A
Exchange Y-register contents with accumulator : YA
Exchange memory contents with accumulator
(M) A
Exchange X-register contents with Y-register : X Y
N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------N-----Z--------
xvi
GMS82512/16/24
HYUNDAI MicroElectronics
16-Bit Operation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
1
2
ADDW dp
CMPW dp
1D
5D
2
2
5
4
3
4
5
6
7
DECW
INCW
LDYA
STYA
SUBW
BD
9D
7D
DD
3D
2
2
2
2
2
6
6
5
5
5
dp
dp
dp
dp
dp
FLAG
NVGBHIZC
OPERATION
16-bits add without carry : YA YA + (dp+1)(dp)
Compare YA contents with memory pair contents :
YA - (dp+1)(dp)
Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1
Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1
Load YA : YA (dp+1)(dp)
Store YA : (dp+1)(dp) YA
16-bits substract without carry : YA YA - (dp+1)(dp)
NV - - H - ZC
N - - - - - ZC
N-----ZN-----ZN-----Z-------NV - - H - ZC
Bit Manipulation
NO.
MNENONIC
OP
CODE
BYTE
NO.
CYCLE
NO
1
2
3
4
AND1 M.bit
AND1B M.bit
BIT dp
BIT !abs
8B
8B
0C
1C
3
3
2
3
4
4
4
5
Bit AND C-flag : C C (M.bit)
Bit AND C-flag and NOT : C C (M.bit)
Bit test A with memory :
Z A M, N (M7), V (M6)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLR1 dp.bit
CLR1A A.bit
CLRC
CLRG
CLRV
EOR1 M.bit
EOR1B M.bit
LDC M.bit
LDCB M.bit
NOT1 M.bit
OR1 M.bit
OR1B M.bit
SET1 dp.bit
SETA1 A.bit
SETC
SETG
STC M.bit
TCLR1 !abs
TSET1 !abs
y1
2B
20
40
80
AB
AB
CB
CB
4B
6B
6B
x1
0B
A0
C0
EB
5C
3C
2
2
1
1
1
3
3
3
3
3
3
3
2
2
1
1
3
3
3
4
2
2
2
2
5
5
4
4
5
5
5
4
2
2
2
6
6
6
Clear bit : (M.bit) “0”
Clear A.bit : (A.bit) “0”
Clear C-flag : C “0”
Clear G-flag : G “0”
Clear V-flag : V “0”
Bit exclusive-OR C-flag : C C ⊕ (M.bit)
Bit exclusive-OR C-flag and NOT : C C ⊕ (M.bit)
Load C-flag : C (M.bit)
Load C-flag with NOT : C (M.bit)
Bit complement : (M.bit) (M.bit)
Bit OR C-flag : C C V (M.bit)
Bit OR C-flag and NOT : C C V (M.bit)
Set bit : (M.bit) “1”
Set A.bit : (A.bit) “1”
Set C-flag : C “1”
Set G-flag : G “1”
Store C-flag : (M.bit) C
Test and clear bits with A :A - (M), (M) (M) (A)
Test and set bits with A :A - (M), (M) (M) V (A)
xvii
FLAG
NVGBHIZC
OPERATION
-------C
-------C
MM - - - - Z ---------------------0
--0-----0--0---------C
-------C
-------C
-------C
--------------C
-------C
---------------------1
--1-----------N-----ZN-----Z-
FEB. 2000 Ver 1.00
HYUNDAI MicroElectronics
GMS82512/16/24
Branch / Jump Operation
NO.
MNENONIC
BYTE
NO.
2
3
2
3
CYCLE
NO
4/6
5/7
4/6
5/7
1
2
3
4
BBC
BBC
BBS
BBS
5
BCC rel
50
2
2/4
6
7
8
9
10
11
12
BCS
BEQ
BMI
BNE
BPL
BRA
BVC
rel
rel
rel
rel
rel
rel
rel
D0
F0
90
70
10
2F
30
2
2
2
2
2
2
2
2/4
2/4
2/4
2/4
2/4
4
2/4
13
BVS rel
B0
2
2/4
14
15
CALL !abs
CALL [dp]
3B
5F
3
2
8
8
16
CBNE dp,rel
CBNE dp + X,
rel
DBNE dp,rel
DBNE Y,rel
JMP !abs
JMP [!abs]
JMP [dp]
PCALL
FD
3
5/7
8D
3
6/8
AC
7B
1B
1F
3F
4F
3
2
3
3
2
2
5/7
4/6
3
5
4
6
17
18
19
20
21
22
23
A.bit,rel
dp.bit,rel
A.bit,rel
dp.bit,rel
OP
CODE
y2
y3
x2
x3
OPERATION
Branch if bit clear :
-------if(bit) = 0, then PC PC + rel
Branch if bit clear :
-------if(bit) = 1, then PC PC + rel
Branch if carry bit clear :
MM - - - - Z if(C) = 0, then PC PC + rel
-------Branch if carry bit set : If (C) =1, then PC PC + rel
-------Branch if equal : if (Z) = 1, then PC PC + rel
-------Branch if munus : if (N) = 1, then PC PC + rel
-------Branch if not equal : if (Z) = 0, then PC PC + rel
-------Branch if not minus : if (N) = 0, then PC PC + rel
-------Branch always : PC PC + rel
Branch if overflow bit clear :
-------If (V) = 0, then PC PC + rel
Branch if overflow bit set :
-------If (V) = 1, then PC PC + rel
Subroutine call
M(SP)(PCH), SPSP-1, M(SP)(PCL), SPSP-1 - - - - - - - if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1)
Compare and branch if not equal ;
-------If A ≠ (M), then PC PC + rel.
Decrement and branch if not equal :
if (M) ≠ 0, then PC PC + rel.
Unconditional jump
PC jump address
TCALL n
nA
1
8
--------
--------
U-page call : M(SP) (PCH), SP SP -1,
M(SP) (PCL), SP SP -1,
24
FLAG
NVGBHIZC
PCL (upage), PCH "OFFH"
Table call :
M(SP) (PCH), SP SP -1,
M(SP) (PCL), SP SP -1
--------
--------
PCL (Table vector L), PCH (Table vector H)
Control Operation & etc.
NO.
1
MNENONIC
BRK
OP
CODE
0F
BYTE
NO.
1
CYCLE
NO
8
OPERATION
Software interrupt:
B “1”, M(SP) (PCH), SP SP - 1,
M(s) (PCL), SP S - 1, M(SP) PSW,
2
3
4
DI
EI
NOP
FEB. 2000 Ver 1.00
60
E0
FF
1
1
1
3
3
2
SP SP - 1, PCL (0FFDEH), PCH (0FFDFH)
Disable interrupts : I “0”
Enable interrupts : I “1”
No operation
FLAG
NVGBHIZC
---1-0--
-----0------1---------
xviii
GMS82512/16/24
NO.
MNENONIC
5
6
7
8
9
10
11
12
13
POP A
POP X
POP Y
POP PSW
PUSH A
PUSH X
PUSH Y
PUSH PSW
RET
14
RETI
15
xix
STOP
HYUNDAI MicroElectronics
OP
CODE
0D
2D
4D
6D
0E
2E
4E
6E
6F
BYTE
NO.
1
1
1
1
1
1
1
1
1
CYCLE
NO
4
4
4
4
4
4
4
4
5
7F
1
6
00
1
3
FLAG
NVGBHIZC
OPERATION
Pop from stack
SP SP + 1, Reg. M(SP)
-------(restored)
Push to stack
M(SP) Reg.
SP SP - 1
--------
Return from subroutine :
SP SP+1, PCL M(SP), SP SP+1, PCH M(SP)
Return from interrupt :
SP SP+1, PSW M(SP), SP SP+1,PCL M(SP),
SP SP+1, PCH M(SP)
Stop mode (halt CPU, stop oscillator)
--------
(restored)
--------
FEB. 2000 Ver 1.00
D. MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
GMS82512
GMS82516
GMS82524
-HH
Customer should write inside thick line box.
2. Device Information
1. Customer Information
Company Name
Package
YYYY
Order Date
Tel:
MM
Mask Data
Application
DD
Fax:
42SDIP
44MQFP
Internet
Hitel
(
File Name
ROM Size (bytes)
Check Sum
PFD Option
16K
(
24K
)
(2 4K ) 20 00 H
(1 6K ) 40 00 H
(1 2K ) 50 00 H
3.0V
.O TP file data
2.4V
S et “F F H” in blanke d area
Not use
7F F F H
(Please check mark√ into
3. Marking Specification
08 or 16 or 24
HME
GMS825XX-HH
YYWW
) .OTP
12K
E-mail address:
Name &
Signature:
Chollian
Customer’s logo
GMS825XX-HH
YYWW
KOREA
KOREA
Customer logo is not required.
If the customer logo must be used in the special mark, please submit a clean original of the logo.
Customer’s part number
4. Delivery Schedule
Date
Customer sample
Risk order
Quantity
YYYY
MM
DD
YYYY
MM
DD
HME Confirmation
pcs
pcs
5. ROM Code Verification
Please confirm out verification data.
YYYY
Verification date:
Check sum:
Tel:
E-mail address:
Name &
Signature:
FEB., 03. 2000
MM
DD
YYYY
Approval date:
MM
DD
I agree with your verification data and confirm you to
make mask set.
Fax:
Tel:
Fax:
E-mail address:
Name &
Signature:
Semiconductor Group of Hyundai Electronics Industries Co., Ltd.
)