Cypress CY14C101Q 1-mbit (128 k x 8) serial (spi) nvsram data retention: 20 years at 85 â°c Datasheet

CY14C101Q
CY14B101Q, CY14E101Q
1-Mbit (128 K × 8) Serial (SPI) nvSRAM
1-Mbit (128 K × 8) Serial (SPI) nvSRAM
Features
■
■
1-Mbit nonvolatile static random access memory (nvSRAM)
internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Support automatic STORE on power-down with a small
capacitor (except for CY14X101Q1A)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ 40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
❐ 40-MHz clock rate SPI write and read with zero cycle delay
❐ 104-MHz clock rate SPI write and SPI read (with special fast
read instructions)
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ SPI access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Low power consumption
❐ Average active current of 3 mA at 40 MHz operation
❐ Average standby mode current of 150 A
❐ Sleep mode current of 8 A
Industry standard configurations
❐ Operating voltages:
• CY14C101Q: VCC = 2.4 V to 2.6 V
• CY14B101Q: VCC = 2.7 V to 3.6 V
• CY14E101Q: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8- and 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X101Q combines a 1-Mbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X101Q1A). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). You can also initiate the STORE and RECALL
operations through SPI instruction.
Configuration
Feature
CY14X101Q1A CY14X101Q2A CY14X101Q3A
AutoStore
No
Yes
Yes
Software
STORE
Yes
Yes
Yes
Hardware
STORE
No
No
Yes
Logic Block Diagram
Serial Number
8x8
Manufacture ID/
Product ID
Status Register
Quantrum Trap
128 K x 8
WRSR/RDSR/WREN
SI
RDSN/WRSN/RDID
CS
READ/WRITE
SCK
SPI Control Logic
Write Protection
Instruction decoder
STORE/RECALL/ASENB/ASDISB
Memory
Data & Address
Control
SRAM
128 K x 8
STORE
RECALL
WP
SO
VCC
VCAP
Power Control Block
Cypress Semiconductor Corporation
Document #: 001-54393 Rev. *F
•
SLEEP
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 5, 2011
CY14C101Q
CY14B101Q, CY14E101Q
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 5
AutoStore Operation .................................................... 5
Software STORE Operation ........................................ 5
Hardware STORE and HSB pin Operation ................. 5
RECALL Operation ...................................................... 6
Hardware RECALL (Power-Up) .................................. 6
Software RECALL ....................................................... 6
Disabling and Enabling AutoStore ............................... 6
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power On Reset .......................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Fast Read Status Register (FAST_RDSR)
Instruction ......................................................................... 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 12
Write Enable (WREN) Instruction .............................. 12
Write Disable (WRDI) Instruction .............................. 12
Block Protection ........................................................ 12
Hardware Write Protection (WP) ............................... 12
Memory Access .............................................................. 13
Read Sequence (READ) Instruction .......................... 13
Fast Read Sequence (FAST_READ) Instruction ...... 13
Write Sequence (WRITE) Instruction ........................ 13
Document #: 001-54393 Rev. *F
nvSRAM Special Instructions ........................................ 15
Software STORE (STORE) Instruction ..................... 15
Software RECALL (RECALL) Instruction .................. 15
AutoStore Enable (ASENB) Instruction ..................... 15
AutoStore Disable (ASDISB) Instruction ................... 15
Special Instructions ....................................................... 16
SLEEP Instruction ..................................................... 16
Serial Number ................................................................. 16
WRSN (Serial Number Write) Instruction .................. 16
RDSN (Serial Number Read) Instruction ................... 17
FAST_RDSN (Fast Serial Number Read)
Instruction ......................................................................... 17
Device ID ......................................................................... 18
RDID (Device ID Read) Instruction ........................... 18
FAST_RDID (Fast Device ID Read) Instruction ........ 19
HOLD Pin Operation ................................................. 19
Best Practices ................................................................. 20
Maximum Ratings ........................................................... 21
DC Electrical Characteristics ........................................ 21
Data Retention and Endurance ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Conditions ........................................................ 23
AC Switching Characteristics ....................................... 24
AutoStore or Power-Up RECALL .................................. 25
Software Controlled STORE and RECALL Cycles ...... 26
Switching Waveforms .................................................... 26
Hardware STORE Cycle ................................................. 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Page 2 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Pinouts
Figure 1. Pin Diagram - 8-pin SOIC[1, 2, 3]
CS
1
8
SO
2
WP
3
CY14X101Q1A 7
Top View
6
not to scale
VSS
4
5
VCC
CS
1
8
HOLD
SO
2
VCAP
3
CY14X101Q2A 7
Top View
6
not to scale
VSS
4
SCK
SI
5
VCC
HOLD
SCK
SI
Figure 2. Pin Diagram - 16-pin SOIC
NC
1
16
VCC
NC
2
15
NC
NC
3
NC
4
CY14X101Q3A 14
Top View
13
not to scale
WP
5
12
SI
HOLD
6
11
SCK
7
10
8
9
NC
VSS
VCAP
SO
CS
HSB
Pin Definitions
Pin Name[1, 2, 3]
I/O Type
Description
CS
Input
Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial Clock. Runs at speeds up to a maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
SI
Input
Serial Input. Pin for input of all SPI instructions and data.
SO
Output
WP
Input
Write Protect. Implements hardware write protection in SPI.
HOLD
Input
HOLD Pin. Suspends Serial Operation.
Serial Output. Pin for output of data through SPI.
HSB
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then
a weak internal pull up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
NC
No connect
No Connect: This pin is not connected to the die.
VSS
Power supply Ground
VCC
Power supply Power supply
Notes
1. HSB pin is not available in 8-pin SOIC packages.
2. CY14X101Q1A part does not have VCAP pin and does not support AutoStore.
3. CY14X101Q2A part does not have WP pin
Document #: 001-54393 Rev. *F
Page 3 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Device Operation
CY14X101Q is a 1-Mbit serial (SPI) nvSRAM memory with a
nonvolatile element in each memory cell. All the reads and writes
to nvSRAM happen to the SRAM, which gives nvSRAM the
unique capability to handle infinite writes to the memory. The
data in SRAM is secured by a STORE sequence which transfers
the data in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (VCAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
The 1-Mbit memory array is organized as 128 K words × 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This nvSRAM chip also supports
104 MHz SPI access speed with a special instruction for read
operation. This device supports SPI modes 0 and 3 (CPOL,
CPHA = 0, 0 and 1, 1) and operates as SPI slave. The device is
enabled using the Chip Select (CS) pin and accessed through
Serial Input (SI), Serial Output (SO), and Serial Clock (SCK)
pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the Status Register. Further,
the HOLD pin is used to suspend any serial communication
without resetting the serial sequence.
CY14X101Q uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, it provides four special instructions that allow access to
four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable you to choose a part which fits in best in their application.
The feature summary is given in Table 1.
Table 1. Feature Summary
Feature
CY14X101Q1A CY14X101Q2A CY14X101Q3A
WP
Yes
No
Yes
VCAP
No
Yes
Yes
HSB
No
No
Yes
AutoStore
No
Yes
Yes
Power-Up
RECALL
Yes
Yes
Yes
Hardware
STORE
No
No
Yes
Software
STORE
Yes
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x00000 and the device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and three bytes of address. The
data is read out on the SO pin.
A speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, three bytes of address, and one dummy
byte. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x00000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
Document #: 001-54393 Rev. *F
Page 4 of 34
CY14C101Q
CY14B101Q, CY14E101Q
STORE Operation
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore Disable (ASDISB) Instruction on page 15). If
AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 21 for the size of the VCAP.
Note CY14X101Q1A does not support AutoStore operation. You
must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
VCC
0.1 uF
10 kOhm
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X101Q is inhibited until the cycle is
completed.
Figure 3. AutoStore Mode
VCC
CS
VCAP
VCAP
VSS
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14X101Q3A is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. A STORE
cycle starts only if a write to the SRAM has been performed since
the last STORE or RECALL cycle. Reads and Writes to the
memory are inhibited for tSTORE duration or as long as HSB pin
is LOW. The HSB pin also acts as an open drain driver (internal
100 k weak pull up resistor) that is internally driven LOW to
indicate a busy condition when the STORE (initiated by any
means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 k pull up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Note CY14X101Q1A/CY14X101Q2A do not have HSB pin. RDY
bit of the SPI Status Register may be probed to determine the
Ready or Busy status of nvSRAM.
Document #: 001-54393 Rev. *F
Page 5 of 34
CY14C101Q
CY14B101Q, CY14E101Q
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the ready status of the device.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. A
Software RECALL is issued by using the SPI instruction for
RECALL.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X101Q2A/CY14X101Q3A has AutoStore enabled
from the factory. In CY14X101Q1A, VCAP pin is not present and
AutoStore option is not available. The AutoStore Enable and
Disable instructions to CY14X101Q1A are ignored.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X101Q operates as a SPI slave and may share the SPI bus
with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Serial Clock (SCK)
Serial Peripheral Interface
CY14X101Q enables SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
SPI Overview
The SPI is a four- pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X101Q provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X101Q can run at speeds up to
104 MHz except READ instruction.
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
Data Transmission - SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
Document #: 001-54393 Rev. *F
Page 6 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Serial Opcode
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X101Q uses the standard opcodes for memory accesses.
In addition to the memory accesses, it provides additional
opcodes for the nvSRAM specific functions: STORE, RECALL,
AutoStore Enable, and AutoStore Disable. Refer to Table 2 on
page 9 for details.
CY14X101Q has two separate pins for SI and SO, which can be
connected with the master as shown in Figure 4 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
Invalid Opcode
The 1-Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the address is only 17 bits, it
implies that the first seven bits which are fed in are ignored by
the device. Although these seven bits are ‘don’t care’, Cypress
recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Status Register
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tri-stated.
CY14X101Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Figure 4. System Configuration Using SPI nvSRAM
SCK
M OSI
M IS O
SCK
SI
SO
SCK
SI
SO
u C o n tro lle r
C Y 1 4 X 1 01Q
CS
C Y14X 101Q
HO LD
CS
HO LD
CS1
HO LD 1
CS2
HO LD 2
SPI Modes
CY14X101Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■
SPI Mode 0 (CPOL=0, CPHA=0)
■
SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles, is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
■
SCK remains at 0 for Mode 0
■
SCK remains at 1 for Mode 3
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
Figure 5. SPI Mode 0
CS
0
1
2
3
4
5
6
7
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when the device is selected, SPI
Document #: 001-54393 Rev. *F
Page 7 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Figure 6. SPI Mode 3
CS
0
1
2
3
4
5
6
7
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
■
Standby power mode
■
Not in the HOLD condition
■
Status Register state:
❐ Write Enable (WEN) bit is reset to ‘0’.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
SPI Operating Features
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
Power-Up
Power-Down
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
CS must be allowed to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull up resistor. As
a built in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS must have been
HIGH, before going Low to start the first operation.
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down.
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for tFA duration after power-up. The HSB pin can be
probed to check the Ready/Busy status of nvSRAM after powerup.
Power On Reset
A Power On Reset (POR) circuit is included to prevent
inadvertent writes. At power-up, the device does not respond to
any instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs an power-Up RECALL operation.
During power-Up RECALL all device accesses are inhibited. The
device is in the following state after POR:
■
Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
Document #: 001-54393 Rev. *F
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
on VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 21. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode after tSB time if a STORE or RECALL cycle is not in
progress. If a STORE/RECALL cycle is in progress, the device
goes into the standby power mode after the STORE or RECALL
cycle is completed. In the standby power mode, the current
drawn by the device drops to ISB.
Page 8 of 34
CY14C101Q
CY14B101Q, CY14E101Q
SPI Functional Description
The CY14X101Q uses an 8-bit instruction register. Instructions
and their opcodes are listed in Table 2. All instructions,
addresses, and data are transferred with the MSB first and start
with a HIGH to LOW CS transition. There are, in all, 18 SPI
instructions which provide access to most of the functions in
nvSRAM. Further, the WP, HOLD and HSB pins provide
additional functionality driven through hardware.
Table 2. Instruction Set
Instruction Category
Instruction Name
Opcode
Operation
Status Register Control Instructions
Status Register access
Write protection and block protection
RDSR
0000 0101
Read Status Register
FAST_RDSR
0000 1001
Fast Status Register read - SPI clock >40 MHz
WRSR
0000 0001
Write Status Register
WREN
0000 0110
Set write enable latch
WRDI
0000 0100
Reset write enable latch
SRAM Read/Write Instructions
Memory access
READ
0000 0011
Read data from memory array
FAST_READ
0000 1011
Fast read - SPI clock >40 MHz
WRITE
0000 0010
Write data to memory array
STORE
0011 1100
Software STORE
RECALL
0110 0000
Software RECALL
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable
Special NV Instructions
nvSRAM special functions
Special Instructions
Sleep
Serial number
SLEEP
1011 1001
Sleep mode enable
WRSN
1100 0010
Write serial number
RDSN
1100 0011
Read serial number
FAST_RDSN
1100 1001
Fast serial number read - SPI clock > 40 MHz
RDID
1001 1111
Read manufacturer JEDEC ID and product ID
Device ID read
FAST_RDID
1001 1001
Fast manufacturer JEDEC ID and product ID Read - SPI
clock > 40 MHz
Reserved
- Reserved -
0001 1110
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register control instructions:
• Status Register access: RDSR, FAST_RDSR and WRSR
instructions
• Write protection and block protection: WREN and WRDI
instructions along with WP pin and WEN, BP0, and BP1
bits
❐ SRAM read/write instructions
• Memory access: READ, FAST_READ and WRITE
instructions
Document #: 001-54393 Rev. *F
❐
Special NV instructions
• nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
❐ Special instructions
• SLEEP, WRSN, RDSN, FAST_RDSN, RDID, FAST_RDID
Page 9 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Status Register
The Status Register bits are listed in Table 3. The Status Register
consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready
or Busy status while a nvSRAM STORE or Software RECALL
cycle is in progress. The Status Register can be modified by
WRSR instruction and read by RDSR or FAST_RDSR
instruction. However, only the WPEN, BP1, and BP0 bits of the
Status Register can be modified by using the WRSR instruction.
The WRSR instruction has no effect on WEN and RDY bits. The
default value shipped from the factory for WEN, BP0, BP1, bits
4 -5, SNL and WPEN is ‘0’.
SNL (bit 6) of the Status Register is used to lock the serial
number written using the WRSN instruction. The serial number
can be written using the WRSN instruction multiple times while
this bit is still '0'. When set to '1', this bit prevents any modification
to the serial number. This bit is factory programmed to '0' and can
only be written to once. After this bit is set to '1', it can never be
cleared to '0'.
Table 3. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
SNL (0)
X (0)
X (0)
BP1 (0)
BP0 (0)
WEN (0)
RDY
Table 4. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = '1' --> Write enabled
WEN = '0' --> Write disabled
Bit 2 (BP0)
Block Protect bit ‘0’
Used for block protection. For details see Table 5 on page 12.
Bit 3 (BP1)
Block Protect bit ‘1’
Used for block protection. For details see Table 5 on page 12.
Bit 4-5
Don’t care
These bits are non-writable and always return ‘0’ upon read.
Bit 6 (SNL)
Serial Number Lock
Set to '1' for locking serial number
Bit 7 (WPEN)
Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12.
Read Status Register (RDSR) Instruction
Write Status Register (WRSR) Instruction
The Read Status Register instruction provides access to the
Status Register at SPI frequency up to 40 MHz. This instruction
is used to probe the Write Enable status of the device or the
Ready status of the device. RDY bit is set by the device to 1
whenever a STORE or Software RECALL cycle is in progress.
The block protection and WPEN bits indicate the extent of
protection employed.
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 (RDY), bit 1 (WEN) and bits 4-5. The BP0 and BP1 bits can be
used to select one of four levels of block protection. Further,
WPEN bit must be set to ‘1’ to enable the use of Write Protect
(WP) pin.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Fast Read Status Register (FAST_RDSR) Instruction
The FAST_RDSR instruction allows you to read the Status
Register at a SPI frequency above 40 MHz and up to 104 MHz
(max).This instruction is used to probe the Write Enable status
of the device or the Ready status of the device. RDY bit is set by
the device to 1 whenever a STORE or Software RECALL cycle
is in progress. The block protection and WPEN bits indicate the
extent of protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR followed by a dummy byte.
Document #: 001-54393 Rev. *F
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by eight bits of data to be
stored in the Status Register. WRSR instruction can be used to
modify only bits 2, 3, 6 and 7 of the Status Register.
Note In CY14X101Q, the values written to Status Register are
saved to nonvolatile memory only after a STORE operation. If
AutoStore is disabled (or while using CY14X101Q1A), any
modifications to the Status Register must be secured by
performing a Software STORE operation.
Note CY14X101Q2A does not have WP pin. Any modification to
bit 7 of the Status Register has no effect on the functionality of
CY14X101Q2A.
Page 10 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Figure 7. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
0
0
0
0
0
1
0
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Figure 8. Fast Read Status Register (FAST_RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
SCK
Dummy Byte
Op-Code
SI
0
0
0
0
1
0
0
X
1
X
X
X
X
X
X
0
X
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Figure 9. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
SI
SO
Document #: 001-54393 Rev. *F
0
0
0
0
0
0
0
1 D7 X
MSB
X
X D3 D2 X
X
LSB
HI-Z
Page 11 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Write Protection and Block Protection
Block Protection
CY14X101Q provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
Block Protect bits.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE and WRSN) and nvSRAM special instruction (STORE,
RECALL, ASENB and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Table 5. Block Write Protect Bits
Level
Write Enable (WREN) Instruction
Status Register
Bits
Array Addresses Protected
BP1
BP0
0
0
0
None
1 (1/4)
0
1
0x18000-0x1FFFF
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRSN, or nvSRAM special instruction
must therefore be preceded by a Write Enable instruction. If the
device is not write enabled (WEN = ‘0’), it ignores the write
instructions and returns to the standby state when CS is brought
HIGH. A new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Hardware Write Protection (WP)
Note After completion of a write instruction (WRSR, WRITE and
WRSN) or nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) instruction, WEN bit is cleared to ‘0’. This
is done to provide protection from any inadvertent writes.
Therefore, WREN instruction needs to be used before a new
write instruction is issued.
Figure 10. WREN Instruction
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
1
0
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 11. WRDI Instruction
CS
1
2
3
4
5
6
7
SCK
SI
SO
0
0
0
0
0
0x10000-0x1FFFF
1
1
0x00000-0x1FFFF
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note CY14X101Q2A does not have WP pin and therefore does
not provide hardware write protection.
Write Disable (WRDI) Instruction
0
1
3 (All)
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
HI-Z
SO
2 (1/2)
0
1
0
Table 6 summarizes all the protection features of this device
Table 6. Write Protection Operation
WPEN
WP
Unprotected
WEN Protected
Blocks
Blocks
Status
Register
X
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
1
Protected
Writable
Protected
1
HIGH
1
Protected
Writable
Writable
0
HI-Z
Document #: 001-54393 Rev. *F
Page 12 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Memory Access
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_READ instruction. When the highest
address in the memory array is reached, address counter rolls
over to start address 0x00000 and thus allowing the read
sequence to continue indefinitely. The FAST_READ instruction
is terminated by driving CS High at any time during data output.
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) Instruction
The read operations on this device are performed by giving the
instruction on the SI pin and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by three bytes
of address. The most significant address byte contains A16 in bit
0 and other bits as ‘don’t cares’. Address bits A15 to A0 are sent
in the following two address bytes. After the last address bit is
transmitted on the SI pin, the data (D7-D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
Note FAST_READ instruction operates up to maximum of
104 MHz SPI frequency.
Write Sequence (WRITE) Instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by three bytes of address and the data (D7-D0) which
is to be written. The Most Significant address byte contains A16
in bit 0 with other bits being ‘don’t cares’. Address bits A15 to A0
are sent in the following two address bytes.
CY14X101Q allows reads to be performed in bursts through SPI
which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x1FFFF) is reached, the address rolls over to
0x00000 and the device continues to read.
Fast Read Sequence (FAST_READ) Instruction
CY14X101Q enables writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address is incremented automatically.
The following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x1FFFF) is reached, the address rolls over to 0x00000
and the device continues to write. The WEN bit is reset to ‘0’ on
completion of a WRITE sequence.
The FAST_READ instruction allows you to read memory at SPI
frequency above 40 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS low, the
FAST_READ instruction is then written to SI, followed by 3
address byte containing the17 bit address (A16 -A0) and then a
dummy byte.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Note The READ instruction operates up to a maximum of
40 MHz SPI frequency.
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
Figure 12. Read Instruction Timing
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
SCK
Op-Code
SI
0
0
0
0
0
SO
0
6
7
~
~ ~
~
0
20 21 22 23 0
1
2
3
4
5
6
7
17-bit Address
1
1
0 0
MSB
0
HI-Z
0
0
0
0 A16
A3 A2 A1 A0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Data
MSB
Document #: 001-54393 Rev. *F
Page 13 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Figure 13. Burst Mode Read Instruction Timing
1
2
3
4
5
6
1
0
7
2
3
4
5
6
7
Op-Code
0
0
0
0
1
2
3
4
5
6
7
0
0
7
1
2
3
4
5
6
7
17-bit Address
0
1
0
1
0
0
0
0
0
0
~
~
SI
20 21 22 23 0
~
~
0
SCK
~
~
CS
A16
0
MSB
A3 A2 A1 A0
LSB
Data Byte N
~
~
Data Byte 1
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
LSB
LSB
Figure 14. Fast Read Instruction Timing
CS
1
2
3
4
5
6
1
0
7
2
3
4
5
6
7
~
~ ~
~
0
SCK
Op-Code
SI
0
0
0
0
1
20 21 22 23 24 25 26 27 28 29 30 31 0
1 1
0 0
MSB
0
0
0
0
0 A16
A3 A2 A1 A0 X X
LSB
X X
X
X X
3
4
5
6
7
X
HI-Z
SO
2
Dummy Byte
17-bit Address
0
1
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Data
MSB
Figure 15. Write Instruction Timing
CS
1
2
3
4
5
1
0
7
6
2
3
4
5
6
7
~
~ ~
~
0
SCK
Op-Code
SI
0
0
0
0
0
20 21
22 23
0
1
2
3
4
5
6
7
17-bit Address
0
1
0
0
0
0
0
0
0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A16
MSB
LSB MSB
LSB
Data
HI-Z
SO
Figure 16. Burst Mode Write Instruction Timing
CS
2
3
4
5
6
7
0
1
2
3
4
5
6
7
20 21 22 23 0
1
2
3
4
5
6
7
0
0
0
17-bit Address
0
1
0
0
0
0
0
0
0
0
~
~
SI
0
A16
Document #: 001-54393 Rev. *F
2
3
4
5
6
7
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
MSB
SO
1
~
~
Op-Code
0
0
Data Byte N
Data Byte 1
0
7
~
~
1
~
~
0
SCK
LSB
HI-Z
Page 14 of 34
CY14C101Q
CY14B101Q, CY14E101Q
nvSRAM Special Instructions
AutoStore Enable (ASENB) Instruction
CY14X101Q provides four special instructions which enables
access to the nvSRAM specific functions: STORE, RECALL,
ASDISB, and ASENB. Table 7 lists these instructions.
The AutoStore Enable instruction enables the AutoStore on
CY14X101Q2A/CY14X101Q3A. This setting is not nonvolatile
and needs to be followed by a STORE sequence to survive the
power cycle.
Table 7. nvSRAM Special Instructions
Function Name
STORE
RECALL
ASENB
ASDISB
Opcode
0011 1100
0110 0000
0101 1001
0001 1001
Operation
Software STORE
Software RECALL
AutoStore Enable
AutoStore Disable
Software STORE (STORE) Instruction
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Figure 17. Software STORE Operation
CS
0
1
2
3
4
5
6
7
SCK
0
1
1
1
1
0
Software RECALL (RECALL) Instruction
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Figure 18. Software RECALL Operation
CS
0
1
2
3
4
5
6
7
SCK
SI
0
1
0
1
1
0
0
1
HI-Z
SO
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASDISB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASDISB
instruction.
Figure 20. AutoStore Disable Operation
CS
0
1
2
3
4
5
6
7
SCK
CS
0
1
2
3
4
5
6
7
SI
SCK
SO
Figure 19. AutoStore Enable Operation
AutoStore
is
enabled
by
default
in
CY14X101Q2A/CY14X101Q3A. The ASDISB instruction
disables the AutoStore. This setting is not nonvolatile and needs
to be followed by a STORE sequence to survive the power cycle.
0
HI-Z
SO
SI
Note If ASDISB and ASENB instructions are executed in
CY14X101Q2A/CY14X101Q3A, the device is busy for the
duration of software sequence processing time (tSS). However,
ASDISB and ASENB instructions have no effect on
CY14X101Q1A as AutoStore is internally disabled.
AutoStore Disable (ASDISB) Instruction
0
SI
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASENB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASENB
instruction.
0
1
1
0
0
0
0
0
SO
0
0
0
1
1
0
0
1
HI-Z
HI-Z
Document #: 001-54393 Rev. *F
Page 15 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Special Instructions
Serial Number
SLEEP Instruction
The serial number is an 8 byte programmable memory space
provided to you uniquely identify this device. It typically consists
of a two byte Customer ID, followed by five bytes of unique serial
number and one byte of CRC check. However, nvSRAM does
not calculate the CRC and it is up to the system designer to utilize
the eight byte memory space in whatever manner desired. The
default value for eight byte locations are set to ‘0x00’.
SLEEP instruction puts the nvSRAM in a sleep mode. When the
SLEEP instruction is issued and CS is brought HIGH, the
nvSRAM performs a STORE operation to secure the data to
nonvolatile memory and then enters into sleep mode. The device
starts consuming IZZ current after tSLEEP time from the instance
when SLEEP instruction is registered. The device is not
accessible for normal operations after SLEEP instruction is
issued. Once in sleep mode, the SCK and SI pins are ignored
and SO is Hi-Z but device continues to monitor the CS pin.
To wake the nvSRAM from the sleep mode, the device must be
selected by toggling the CS pin from HIGH to LOW. The device
wakes up and is accessible for normal operations after tWAKE
duration after a falling edge of CS pin is detected.
WRSN (Serial Number Write) Instruction
The serial number can be written using the WRSN instruction. To
write serial number the write must be enabled using the WREN
instruction. The WRSN instruction can be used in burst mode to
write all the 8 bytes of serial number.
The serial number is locked using the SNL bit of the Status
Register. Once this bit is set to '1', no modification to the serial
number is possible. After the SNL bit is set to '1', using the WRSN
instruction has no effect on the serial number.
A STORE operation (AutoStore or Software STORE) is required
to store the serial number in nonvolatile memory. If AutoStore is
disabled, you must perform a Software STORE operation to
secure and lock the serial Number. If SNL bit is set to ‘1’ and is
not stored (AutoStore disabled), the SNL bit and serial number
defaults to ‘0’ at the next power cycle. If SNL bit is set to ‘1’ and
is stored, the SNL bit can never be cleared to ‘0’. This instruction
requires the WEN bit to be set before it can be executed. The
WEN bit is reset to '0' after completion of this instruction.
Note Whenever nvSRAM enters into sleep mode, it initiates
nonvolatile STORE cycle which results in an endurance cycle per
sleep command execution. A STORE cycle starts only if a write
to the SRAM has been performed since the last STORE or
RECALL cycle.
Figure 21. Sleep Mode Entry
t
SLEEP
CS
0
1
2
3
4
5
6
7
SCK
SI
1
0
1
1
1
0
0
1
Hi-Z
SO
Figure 22. WRSN Instruction
1
2
3
4
5
1
0
7
6
2
3
4
5
6
7
SI
1
1
0
0
0
56 57 58 59 60 61 62 63
Byte - 1
Byte - 8
Op-Code
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
~
~
0
SCK
~
~
CS
D7 D6 D5 D4 D3 D2 D1 D0
LSB
8-Byte Serial Number
HI-Z
SO
Figure 23. WRSN Instruction
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI
1
1
0
0
0
0
Document #: 001-54393 Rev. *F
Byte - 1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
56 57 58 59 60 61 62 63
Byte - 8
Op-Code
~
~
0
SCK
~
~
CS
D7 D6 D5 D4 D3 D2 D1 D0
8-Byte Serial Number
LSB
HI-Z
Page 16 of 34
CY14C101Q
CY14B101Q, CY14E101Q
RDSN (Serial Number Read) Instruction
RDSN instruction can be issued by shifting the op-code for
RDSN in through the SI pin of nvSRAM after CS goes LOW. This
is followed by nvSRAM shifting out the eight bytes of serial
number through the SO pin.
The serial number is read using RDSN instruction at SPI
frequency upto 40 MHz. A serial number read may be performed
in burst mode to read all the eight bytes at once. After the last
byte of serial number is read, the device does not loop back.
Figure 24. RDSN Instruction
0
1
2
1
1
0
3
4
5
0
7
6
1
2
3
4
5
6
7
SCK
~
~
CS
56 57 58 59 60 61 62 63
Op-Code
SI
0
0
0
1
1
Byte - 1
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
~
~
Byte - 8
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
LSB
8-Byte Serial Number
FAST_RDSN (Fast Serial Number Read) Instruction
the device does not loop back. FAST_RDSN instruction can be
issued by shifting the op-code for FAST_RDSN in through the SI
pin of nvSRAM followed by dummy byte after CS goes LOW.
This is followed by nvSRAM shifting out the eight bytes of serial
number through the SO pin.
The FAST_RDSN instruction is used to read serial number at SPI
frequency above 40 MHz and up to 104 MHz (max). A serial
number read may be performed in burst mode to read all the
eight bytes at once. After the last byte of serial number is read,
Figure 25. FAST_RDSN Instruction
0
1
2
3
4
5
7
6
8
9
10 11 12 13
14 15
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
1
1
0
0
1
0
~
~
CS
56 57 58 59 60 61 62 63
Dummy Byte
0
1
X
X
X
X
X
X X
X
Byte - 1
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-54393 Rev. *F
~
~
Byte - 8
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
8-Byte Serial Number
LSB
Page 17 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Device ID
Device ID is 4-byte read only code identifying a type of product
uniquely. This includes the product family code, configuration
and density of the product.
Table 8. Device ID
Bits
#of Bits
Device
CY14C101Q1A
CY14C101Q2A
CY14C101Q3A
CY14B101Q1A
CY14B101Q2A
CY14B101Q3A
CY14E101Q1A
CY14E101Q2A
CY14E101Q3A
31 - 21
(11 bits)
Manufacture ID
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
20 - 7
(14 bits)
Product ID
00001000000001
00001100000000
00001100000001
00001000010001
00001100010000
00001100010001
00001000100001
00001100100000
00001100100001
6- 3
(4 bits)
Density ID
0100
0100
0100
0100
0100
0100
0100
0100
0100
2-0
(3 bits)
Die Rev
000
000
000
000
000
000
000
000
000
The device ID is divided into four parts as shown in Table 8:
4. Die Rev (3 bits)
1. Manufacturer ID (11 bits)
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Cypress’s manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is:
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID is defined as shown in the Table 8
RDID (Device ID Read) Instruction
This instruction is used to read the JEDEC assigned manufacturer ID and product ID of the device at SPI frequency upto
40 MHz. This instruction can be used to identify a device on the
bus. RDID instruction can be issued by shifting the op-code for
RDID in through the SI pin of nvSRAM after CS goes LOW. This
is followed by nvSRAM shifting out the four bytes of device ID
through the SO pin.
3. Density ID (4 bits)
The 4 bit density ID is used as shown in Table 8 for indicating the
1Mb density of the product.
Figure 26. RDID instruction
CS
0 1
2
3 4
5
6
7 0 1
2
3 4
5
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Op-Code
SI
1 0 0 1 1 1 1
1
Byte - 4
SO
HI-Z
Byte - 3
Byte - 2
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB
MSB
4-Byte Device ID
Document #: 001-54393 Rev. *F
Page 18 of 34
CY14C101Q
CY14B101Q, CY14E101Q
FAST_RDID (Fast Device ID Read) Instruction
The FAST_RDID instruction allows the user you to read the
JEDEC assigned manufacturer ID and product ID at SPI
frequency above 40 MHz and up to 104 MHz (max). FAST_RDID
instruction can be issued by shifting the op-code for FAST_RDID
in through the SI pin of nvSRAM followed by dummy byte after
CS goes LOW. This is followed by nvSRAM shifting out the four
bytes of device ID through the SO pin.
Figure 27. FAST_RDID instruction
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Op-Code
SI
1 0 0 1 1
Dummy Byte
0 0
1 X X X X X X X X
Byte - 4
SO
HI-Z
Byte - 3
Byte - 2
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
4-Byte Device ID
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. To
resume serial communication, the HOLD pin must be brought
HIGH when the SCK pin is LOW (SCK may toggle during HOLD).
While the device serial communication is paused, inputs to the
SI pin are ignored and the SO pin is in the high impedance state.
This pin can be used by the master with the CS pin to pause the
serial communication by bringing the pin HOLD LOW and
deselecting an SPI slave to establish communication with
Document #: 001-54393 Rev. *F
another slave device, without the serial communication being
reset. The communication may be resumed at a later point by
selecting the device and setting the HOLD pin HIGH.
Figure 28. HOLD Operation
CS
SCK
~
~
~ ~
HOLD Pin Operation
HOLD
SO
Page 19 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Best Practices
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered by
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-54393 Rev. *F
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection.
Page 20 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Maximum Ratings
Transient voltage (< 20 ns) on
any pin to ground potential .................. –2.0 V to VCC + 2.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) .................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount lead soldering
temperature (3 seconds) .......................................... +260 C
At 150 C ambient temperature ....................... 1000 h
DC output current (1 output at a time, 1s duration) ..... 15 mA
At 85 C ambient temperature ..................... 20 Years
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Ambient temperature with
power applied ........................................... –55 C to +150 C
Latch up current..................................................... > 140 mA
Supply voltage on VCC relative to VSS
CY14C101Q: VCC = 2.4 V to 2.6 V ....–0.5 V to +3.1 V
CY14B101Q: VCC = 2.7 V to 3.6 V ....–0.5 V to +4.1 V
CY14E101Q: VCC = 4.5 V to 5.5 V ....–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z state ..................................... –0.5 V to VCC + 0.5 V
Table 9. Operating Range
Input voltage ........................................ –0.5 V to VCC + 0.5 V
Device
Range
Ambient
Temperature
VCC
CY14C101Q
Industrial –40 C to +85 C 2.4 V to 2.6 V
CY14B101Q
2.7 V to 3.6 V
CY14E101Q
4.5 V to 5.5 V
DC Electrical Characteristics
Parameter
VCC
ICC1
Description
Test Conditions
Power supply
Average VCC current
Min
Typ[4]
Max
Unit
CY14C101Q
2.4
2.5
2.6
V
CY14B101Q
2.7
3.0
3.6
V
CY14E101Q
4.5
5.0
5.5
V
CY14C101Q
–
–
3
mA
–
–
4
mA
fSCK = 104 MHz; Values obtained without output loads
(IOUT = 0 mA)
–
–
10
mA
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
2
mA
fSCK = 40 MHz; Values obtained without
output loads (IOUT = 0 mA)
CY14B101Q
CY14E101Q
ICC2
Average VCC current
during STORE
ICC3
Average VCC current All inputs cycling at CMOS levels.
Values obtained without output loads (IOUT = 0 mA)
fSCK = 1 MHz;
VCC = VCC (Typ), 25 °C
–
–
1
mA
ICC4
Average VCAP current All inputs don't care. Average current for duration tSTORE
during AutoStore cycle
–
–
3
mA
ISB
VCC standby current
CS > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. fSCK = 0 MHz.
–
–
150
A
IZZ
Sleep mode current
tSLEEP time after SLEEP Instruction is registered. All
inputs are static and configured at CMOS logic level.
–
–
8
A
IIX[5]
Input leakage current
(except HSB)
–1
–
+1
A
Input leakage current
(for HSB)
–100
–
+1
A
Notes
4. Typical values are at 25 °C, VCC = VCC (Typ). Not 100% tested.
5. The HSB pin has IOUT = -2 µA for VOH of 2.4 V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-54393 Rev. *F
Page 21 of 34
CY14C101Q
CY14B101Q, CY14E101Q
DC Electrical Characteristics (continued)
Parameter
Description
IOZ
Off-state output
leakage current
VIH
Input HIGH voltage
Test Conditions
Min
Typ[4]
Max
Unit
–1
–
+1
A
CY14C101Q
1.7
–
VCC + 0.5
V
CY14B101Q
2.0
–
VCC + 0.5
V
CY14C101Q
VSS – 0.5
–
0.7
V
CY14B101Q
VSS – 0.5
–
0.8
V
CY14E101Q
VIL
Input LOW voltage
CY14E101Q
VOH
Output HIGH voltage
IOUT = –1 mA
CY14C101Q
2.0
–
–
V
IOUT = –2 mA
CY14B101Q
2.4
–
–
V
CY14C101Q
–
–
0.4
V
CY14B101Q
–
–
0.4
V
CY14C101Q
170
220
270
F
CY14B101Q
42
47
180
F
CY14E101Q
VOL
Output LOW voltage
IOUT = 2 mA
IOUT = 4 mA
CY14E101Q
VCAP
Storage capacitor
Between VCAP pin and VSS
CY14E101Q
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
7
pF
8-pin SOIC 16-pin SOIC
Unit
Capacitance
Parameter[6]
Description
CIN
Input capacitance
COUT
Output pin capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = VCC (Typ)
Thermal Resistance
Parameter [6]
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
101.08
56.68
C/W
37.86
32.11
C/W
Note
6. These parameters are guaranteed by design and are not tested.
Document #: 001-54393 Rev. *F
Page 22 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Figure 29. AC Test Loads and Waveforms
For 2.5 V (CY14C101Q):
909 
909 
2.5 V
2.5 V
R1
For Tristate specs
R1
OUTPUT
OUTPUT
R2
1290 
30 pF
R2
1290 
5 pF
For 3 V (CY14B101Q):
577 
577 
3.0 V
3.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
R2
789 
30 pF
R2
789 
5 pF
For 5 V (CY14E101Q):
963 
963 
5.0 V
5.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
512 
R2
512 
5 pF
AC Test Conditions
CY14C101Q
CY14B101Q
CY14E101Q
0 V to 2.5 V
0 V to 3 V
0 V to 3 V
Input rise and fall times (10% - 90%)
< 3 ns
< 3 ns
< 3 ns
Input and output timing reference levels
1.25 V
1.5 V
1.5 V
Input pulse levels
Document #: 001-54393 Rev. *F
Page 23 of 34
CY14C101Q
CY14B101Q, CY14E101Q
AC Switching Characteristics
Cypress
Parameter
fSCK
tCL[7]
tCH[7]
tCS
tCSS
tCSH
tSD
tHD
tHH
tSH
tCO
tHHZ[7]
tHLZ[7]
tOH
tHZCS[7]
Alt. Parameter
40 MHz
Description
fSCK
tWL
tWH
tCE
tCES
tCEH
tSU
tH
tHD
tCD
tV
tHZ
tLZ
tHO
tDIS
Min
–
11
11
20
10
10
5
5
5
5
–
–
–
0
–
Clock frequency, SCK
Clock pulse width LOW
Clock pulse width HIGH
CS HIGH time
CS setup time
CS hold time
Data in setup time
Data in hold time
HOLD hold time
HOLD setup time
Output Valid
HOLD to output HIGH Z
HOLD to output LOW Z
Output hold time
Output disable time
104 MHz
Min
Max
–
104
4.5
–
4.5
–
20
–
5
–
5
–
4
–
3
–
3
–
3
–
–
8
–
8
–
8
0
–
–
8
Max
40
–
–
–
–
–
–
–
–
–
9
15
15
–
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 30. Synchronous Data Timing (Mode 0)
tCS
CS
tCH
tCL
tCSH
~
~
tCSS
SCK
tSD
tHD
VALID IN
SI
tCO
SO
tOH
HI-Z
tHZCS
HI-Z
~
~
~ ~
Figure 31. HOLD Timing
CS
SCK
tHH
tHH
tSH
tSH
HOLD
tHHZ
tHLZ
SO
Note
7. These parameters are guaranteed by design and are not tested.
Document #: 001-54393 Rev. *F
Page 24 of 34
CY14C101Q
CY14B101Q, CY14E101Q
AutoStore or Power-Up RECALL
Parameter
Description
tFA [8]
Power-Up RECALL duration
tSTORE [9]
STORE cycle duration
tDELAY [10]
VSWITCH
Time allowed to complete SRAM write cycle
tVCCRISE[11]
VCC rise time
VHDIS[11]
tLZHSB[11]
tHHHD[11]
tWAKE
Time for nvSRAM to wake up from SLEEP mode
tSLEEP
tSB
Time to enter SLEEP mode after issuing SLEEP instruction
Time to enter into standby mode after CS going HIGH
CY14C101Q
CY14B101Q
CY14E101Q
CY14X101Q
Min
Max
–
40
–
20
–
20
–
8
Unit
ms
ms
ms
ms
–
25
ns
–
–
–
150
2.35
2.65
4.40
–
V
V
V
s
HSB output disable voltage
–
1.9
V
HSB high to nvSRAM active time
–
5
s
–
500
ns
–
–
–
–
–
40
20
20
8
100
ms
ms
ms
ms
µs
Low voltage trigger level
CY14C101Q
CY14B101Q
CY14E101Q
HSB high active time
CY14C101Q
CY14B101Q
CY14E101Q
Switching Waveforms
Figure 32. AutoStore or Power-Up RECALL[12]
VCC
VSWITCH
VHDIS
t VCCRISE
9
tHHHD
Note
tSTORE
Note
tHHHD
13
Note
9
tSTORE
Note
13
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
8. tFA starts from the time VCC rises above VSWITCH.
9. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
10. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.
11. These parameters are guaranteed by design and are not tested.
12. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
13. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-54393 Rev. *F
Page 25 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Software Controlled STORE and RECALL Cycles
CY14X101Q
Parameter
Description
tRECALL
tSS
[14, 15]
Unit
Min
Max
RECALL duration
–
600
s
Soft sequence processing time
–
500
s
Switching Waveforms
Figure 33. Software STORE Cycle[15]
CS
CS
0
1
2
3
4
5
6
7
0
SCK
SI
Figure 34. Software RECALL Cycle[15]
1
2
3
4
5
6
7
SCK
0
0
1
1
1
1
0
0
SI
0
1
1
0
0
0
0
0
tRECALL
tSTORE
HI-Z
RWI
RDY
RDY
Figure 35. AutoStore Enable Cycle
CS
0
1
2
3
4
5
6
Figure 36. AutoStore Disable Cycle
CS
7
0
SCK
SI
HI-Z
RWI
1
2
3
4
5
6
7
SCK
0
1
0
1
1
0
0
1
SI
0
0
0
1
1
0
0
1
tSS
RWI
tSS
HI-Z
RDY
RWI
HI-Z
RDY
Notes
14. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
15. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-54393 Rev. *F
Page 26 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Hardware STORE Cycle
Parameter
tPHSB
CY14C101Q3A/CY14B101Q3A/
CY14E101Q3A
Description
Min
Max
15
–
Hardware STORE pulse width
Switching Waveforms
Unit
ns
Figure 37. Hardware STORE Cycle[16]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
tDELAY
HSB (OUT)
tLZHSB
RWI
tPHSB
HSB (IN)
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDELAY
RWI
~
~
HSB (OUT)
~
~
Write Latch not set
Note
16. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
Document #: 001-54393 Rev. *F
Page 27 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Ordering Information
Ordering Code
CY14B101Q1A-SXIT
CY14B101Q1A-SXI
Package Diagram
51-85066
Package Type
Operating Range
8-pin SOIC (with WP), 40 MHz
Industrial
8-pin SOIC (with WP), 40 MHz
CY14B101Q2A-SXIT
8-pin SOIC (with VCAP), 40 MHz
CY14B101Q2A-SXI
8-pin SOIC (with VCAP), 40 MHz
All these parts are Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Document #: 001-54393 Rev. *F
Page 28 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Ordering Code Definitions
CY 14 C 101 Q 1 A - S 104 X I T
Option:
T - Tape & Reel
Blank - Std.
Pb-free
Frequency:
Blank - 40 MHz
104 - 104 MHz
Die revision:
Blank - No Rev
A - 1st Rev
Temperature:
I - Industrial (-40 to 85 °C)
Package:
SXP - 8 SOIC
SFP - 16 SOIC
1 - With WP
2 - With VCAP
3 - With WP, VCAP and HSB
Q - Serial (SPI) nvSRAM
Density:
101 - 1 Mb
14 - nvSRAM
Voltage:
C - 2.5 V
B - 3.0 V
E - 5.0 V
Cypress
Document #: 001-54393 Rev. *F
Page 29 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Package Diagrams
Figure 38. 8-pin (150 mil) SOIC, 51-85066
51-85066 *D
Document #: 001-54393 Rev. *F
Page 30 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Package Diagrams (continued)
Figure 39. 16-pin (300 mil) SOIC, 51-85022
51-85022 *C
Document #: 001-54393 Rev. *F
Page 31 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Acronyms
Document Conventions
Description
Units of Measure
nvSRAM
Nonvolatile static random access memory
Symbol
SPI
Serial peripheral interface
°C
degree Celsius
RoHS
Restriction of hazardous substances
Hz
Hertz
I/O
Input/output
kbit
1024 bits
CMOS
Complementary metal oxide semiconductor
kHz
kilo Hertz
SOIC
Small outline integrated circuit
k
kilo ohms
SONOS
Silicon-oxide-nitride-oxide-silicon
A
micro Amperes
CPHA
Clock phase
mA
milli Amperes
CPOL
Clock polarity
F
micro Farad
EEPROM
Electrically erasable programmable
read-only memory
MHz
Mega Hertz
s
micro seconds
JEDEC
Joint Electron Devices Engineering Council
ms
milli seconds
ns
nano seconds
pF
pico Farad
V
Volts

ohms
W
Watts
Acronym
CRC
Cyclic redundancy check
EIA
Electronic Industries Alliance
RWI
Read and write inhibited
Document #: 001-54393 Rev. *F
Unit of Measure
Page 32 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Document History Page
Document Title: CY14C101Q, CY14B101Q, CY14E101Q 1-Mbit (128 K × 8) Serial (SPI) nvSRAM
Document Number: 001-54393
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
2754627
GVCH
08/21/09
New data sheet
*A
2864129
GVCH
01/22/2010 Changed Vcc range for CY14C101Q from 2.3 - 2.7 V to 2.4-2.6 V
Removed 16-SOIC 150 mil package
Added VOH, VOL, VIH, VIL and VCAP specs for Vcc (Typ) = 2.5 V
Updated VIH min value from 1.4 V to 2.0 V for Vcc (Typ) = 3 V & 5 V
*B
2963131
06/28/2010
GVCH
Updated logic block diagram
Updated Pinouts
Updated Pin Definitions
Complete content write
Table 3: Added FAST_RDSR, FAST_RDSN and FAST_RDID opcodes
Changed ICC4 value from 2 mA to 3 mA
Added Ci parameter in DC Electrical Characteristics
Changed VCAP value from for VCC=2.4 V-2.6 V in DC Electrical Characteristics
Changed min value from 100 uF to 170 uF
Changed typ value from 150 uF to 220 uF
Changed max value from 330 uF to 270 uF
Changed VCAP value from for VCC=2.7 V-3.6 V and VCC=4.5-5.5 V in DC
Electrical Characteristics
Changed min value from 40 uF to 42 uF
Added Data Retention and Endurance Table
Added Capacitance Table
Added Thermal Resistance Table
Added AC Test Conditions Table
Changed tCSS parameter min value from 3 ns to 5 ns for 104 MHz
Changed tCSH parameter min value from 3 ns to 5 ns for 104 MHz
Changed tSD parameter min value from 3 ns to 4 ns for 104 MHz
Changed tHD parameter min value from 2 ns to 3 ns for 104 MHz
Added Figures
Added tFA for VCC=2.4 V-2.6 V
Added tWAKE for VCC=2.4 V-2.6 V
Added tSB parameter
Changed VSWITCH from 4.45 V to 4.40 V for VCC = 4.5 V to 5.5 V
Added Software Controlled STORE and RECALL Cycles Table
Updated tRECALL value from 200 us to 300 us
Changed tSS value from 100 to 200 µs
Added Hardware STORE Cycle Table
Updated Ordering Information
Updated package diagram
*C
3084950
11/12/2010
GVCH
Updated tSS value from 200 us to 500 us
Updated tRECALL value from 300 us to 600 us
Added Units of Measure table
*D
3148547
01/20/2011
GVCH
Hardware STORE and HSB pin Operation: Added more clarity on HSB pin
operation
Updated tLZHSB parameter description
Fixed typo in Figure 32.
*E
3202556
03/22/2011
GVCH
Updated AutoStore Operation (description).
Updated Table 4 (definition of Bit 4-5).
Updated DC Electrical Characteristics (Added ICC1 parameter for 104 MHz
frequency).
Updated in new template.
*F
3249486
05/05/2011
GVCH
Datasheet status changed from “Preliminary” to “Final”
Updated Ordering Information
Document #: 001-54393 Rev. *F
Page 33 of 34
CY14C101Q
CY14B101Q, CY14E101Q
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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psoc.cypress.com/solutions
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
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PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-54393 Rev. *F
Revised May 5, 2011
All products and company names mentioned in this document may be the trademarks of their respective holders.
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