Micrel MIC74YQS 2-wire serial i/o expander and fan controller Datasheet

MIC74
2-Wire Serial I/O Expander
and Fan Controller
General Description
Features
The MIC74 is a fully programmable serial-to-parallel I/O
expander compatible with the SMBus™ (system management bus) protocol. It acts as a “slave” on the bus,
providing eight independent I/O lines.
Each I/O bit can be individually programmed as an input or
output. If programmed as an output; each I/O bit can be
programmed as an open-drain or complementary push-pull
output. If desired, the four most significant I/O bits can be
programmed to implement fan speed control. An internal
clock generator and state machine eliminate the overhead
generally associated with “bit-banging” fan speed control.
Programming the device and reading/writing the I/O bits is
accomplished using seven internal registers. All registers
can be read by the host. Output bits are capable of directly
driving high-current loads such as LEDs. A separate
interrupt output can notify the host of state changes on the
input bits without requiring the MIC74 to perform a
transaction on the serial bus or be polled by the host.
Three address selection inputs are provided, allowing up
to eight devices to share the same bus and provide a total
of 64 bits of I/O.
The MIC74 is available in an ultra-small-footprint 16-pin
QSOP. Low quiescent current, small footprint, and low
package height make the MIC74 ideal for portable and
desktop applications.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
• Provides eight bits of general purpose I/O
• Built in fan speed control logic (optional)
• 2-wire SMBus™/I2C™ compatible serial interface plus
interrupt output
• 2.7V to 3.6V operating voltage range
• 5V-tolerant I/O
• Low quiescent current: 2µA (typical)
• Bit-programmable I/O options:
– input or output
– push-pull or open-drain output
– interrupt on input changes
• Outputs can directly drive LEDs (10mA IOL)
• Up to 8 devices per bus
Applications
•
•
•
•
•
General purpose I/O expansion via serial bus
Personal computer system management
Distributed sensing and control
Microcontroller I/O expansion
Fan Control
Ordering Information
Part Number
Standard
Pb-Free
Temperature
Range
Package
MIC74BQS
MIC74YQS
–40° to +85°C
16-Pin QSOP
Typical Application
3.0V
3.0V
MIC74
R9
ALERT
DATA
CLK
VDD
/ALERT
DATA
P0
P1
P2
CLK
A0
P3
P4
A1
A2
GND
P5
P6
P7
LED1
R1
R2
R3
R4
R5
R6
R7
R8
LED8
Serial-Bus-Controlled LED Annunciator
2
SMBus is a trademark of Intel Corporation. I C is a trademark of Phillips Electronics N.V.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2006
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M9999-101006
Micrel, Inc.
MIC74
Pin Configuration
A0 1
16 VDD
A1 2
15 DATA
A2 3
14 CLK
P0 4
13 /ALERT
P1 5
12 P7 (/FS2)
P2 6
11 P6 (/FS1)
P3 7
10 P5 (/FS0)
GND 8
9 P4 (/SHDN0)
16-Pin QSOP (QS)
Pin Description
Pin Number
Pin Name
1–3
A0 – A2
Address (Input): Slave address selection inputs; sets the three least significant bits of the
MIC74’s slave address.
4–7
P0 – P3
Parallel I/O (Input/Output): General-purpose I/O pin. Direction and output type are user
programmable.
8
GND
9 – 12
P4 – P7
(/SHDN, /FS0 – FS2)
Parallel I/O (Input/output): P4–P7 are general-purpose I/O pins. Direction and output type
are user programmable.
Shutdown (Output): When the FAN bit is set, pin 9 becomes SHDN.
Fan Speed (Output): When the FAN bit is set, pins 10 through 12 become /FS0–/FS2
respectively, controlled by the FAN_SPEED register.
13
/ALERT
Interrupt (Output): Active-low, open-drain output signals input-change-interrupts to the host
on this pin. Signal is cleared when the bus master (host) polls the ARA (alert response
address = 0001 100) or reads status.
14
CLK
15
DATA
Serial Data (Input/Output): Serial data input and open-drain serial data output.
16
VDD
Power Supply (Input).
October 2006
Pin Function
Ground
Serial Bus Clock (Input): The host provides the serial bit clock in this input.
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M9999-101006
Micrel, Inc.
MIC74
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)...................................................+4.6V
Input Voltage [all pins except
VDD and GND] (VIN)........................ GND – 0.3V to 5.5V
Junction Temperature (TJ) ....................................... +150°C
Lead Temperature (soldering, 10 sec.).................... +260°C
EDS Rating(3)
VDD ........................................................................ 1.5kV
A0, A1, A2..............................................................500V
Others ....................................................................200V
Supply Voltage (VDD).................................... +2.7V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance ................................163°C/W
Electrical Characteristics
2.7V ≤ VDD ≤ 3.6V; TA = 25°C, bold values indicate –40°C < TA < +85°C, unless noted.
Symbol
Parameter
Condition
Min
VIN
Input Voltage, any pin except
VDD and GND
IDD
Operating Supply Current
P[7:0] inputs; P[7:0] = VDD or GND
/ALERT open; fCLK = 100kHz
ISTART
Fan Startup Supply Current
(Fan Mode Only)
during tSTART; /ALERT, /SHDN,
/FS2[2:0] = open;
VSMBCLK = VSMBDATA = VDD;
P[3:0] = inputs
ISTBY
Standby Supply Current
/ALERT = open,
VSMBCLK = VSMBDATA = VDD;
P[3:0] = inputs
Typ
GND–0.3
2
1
Max
Units
5.5
V
6
µA
1.75
mA
3
µA
Serial I/O (DATA, CLK)
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2
5.5
V
VOL
Output Low Voltage
IOL = 3mA
0.4
V
ILEAK
Leakage Current
VIN = 5.5V or GND
+1
µA
CIN
Input Capacitance
–1
10
pF
Parallel I/O [P0–P3, P4(/SHDN), P5(/FS0)–P7(/FS2)]
VIL
Input Low Voltage
VIH
Input High Voltage
IOL
Output Low Current
–0.5
0.8
2
5.5
V
V
VOL = 0.4V, VDD = 2.7V
7
mA
VOL = 1V, VDD = 3.3V
10
mA
IOH
Output High Current
VOH = 2.4V
7
ILEAK
Leakage Current
VIN = 5.5V or GND
–1
mA
CIN
Input Capacitance
10
pF
COUT
Output Capacitance
10
pF
+1
µA
Address Input (A0–A2)
VIL
Input Low Voltage
–0.3
0.3VDD
V
VIH
Input High Voltage
0.7VDD
VDD+0.3
V
ILEAK
Leakage Current
VIN = VDD or GND
–250
+250
nA
VOL
Output Low Voltage
IOL = 1mA
0.4
V
ILEAK
Leakage Current
VIN = VDD or VSS
+1
µA
/ALERT
October 2006
–1
3
±250
M9999-101006
Micrel, Inc.
Symbol
MIC74
Parameter
Condition
Min
Typ
Max
Units
1
3.3
sec
AC Characteristics
tSTART
Fan Startup Interval
normal operation
0.5
tPULSE
Minimum Pulse-Width
minimum pulse-width on Pn to generate
an interrupt, Note 7
10
t/INT
Interrupt Delay
interrupt delay from state change on Pn to
/ALERT ≤ VOL, Note 7
t/IR
Delay from Status Read or ARA
Response to /ALERT ≥ VOH
tHD:STA
Hold Time, Note 7
hold time after repeated start condition,
after this period, the first clock is
generated
tSU:STA
Setup Time, Note 7
repeated start condition setup time
tSU:STO
Stop Condition Setup Time
tHD:DAT
Data Hold Time
tSU:DAT
ns
4
µs
4
µs
4
µs
4.7
µs
Note 7
4
µs
Note 7
500
ns
Data Setup Time
Note 7
0
ns
tTIMEOUT
Clock Low Time-Out
Note 4, 7
25
tLOW
Clock Low Period
Note 5, 7
4.7
tHIGH
Clock High Period
Note 5, 7
4
tF
Clock/Data Fall Time
Note 6, 7
tR
Clock/Data Rise Time
Note 6, 7
tBUF
Bus free time between stop and
Start condition
Note 7
35
ms
µs
50
µs
300
ns
1000
4.7
ns
µs
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT(min) of 25ms. Devices that have detected a timeout
condition must reset the communication no later than tTIMEOUT(max) of 35ms. The maximum value specified must be adhered to by both a master and a
slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
5. tHIGH(max) provides a simple guaranteed method for devices to detect bus idle conditions.
6. Rise and fall time is defined as follows: tR = VIL(max) – 0.15V to VIH(min) + 0.15V; tF = 0.9VDD to VIL(max) – 0.15V.
7. Guaranteed by design.
Timing Definitions
tR
tF
CLK
tLOW
tHD:STA
tBUF
tHIGH
tSU:STA
tSU:STO
tSU:DAT
tHD:STA
tHD:DAT
DATA
StoP Start
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Start
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StoP
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Micrel, Inc.
MIC74
Register Descriptions
Device Configuration Register
Output Configuration Register
DEV_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
OUT_CFG
D[2]
Always write as zero
D[1]
D[0]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
FAN
IE
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
Power-On Default Value: 0000 0000b, 00h
all outputs open-drain
Command_byte addess: 0000 0010b, 02h
Type:
8-bits, read/write
Power-On Default Value: 0000 0000b, 00h
Interrupts disabled
Not in Fan Mode
Command_byte addess: 0000 0000b, 00h
Type:
8-bits, read/write
Bit Name:
Function:
OUTn
Selects output driver configuration of Pn when
Pn is configured as an output.
Operation: 1 = push-pull
0 = open-drain
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and
/SHDN. The OUT_CFG register has no effect
on these I/O bits while in Fan Mode.
Bit Name: IE
Function: Global interrupt enable
Operation: 1 = enabled
0 = disabled
Bit Name:
Function:
FAN
Selects Fan Mode
(P[7:4] vs. /FS[2:0], /SHDN)
Operation: 1 = Fan Mode
0 = I/O Mode
Bit Name: D[2] through D[6]
Function: Reserved
Operation: Reserved—always write as zero
Status Register
Data Direction Register
STATUS
DIR
D[7]
DIR7
D[6]
DIR6
D[5]
DIR5
D[4]
DIR4
D[3]
DIR3
D[2]
DIR2
D[1]
DIR1
D[0]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
DIR0
S7
S6
S5
S4
S3
S2
S1
S0
Power-On Default Value: 0000 0000b, 00h
all Pn’s configured as inputs
Command_byte addess: 0000 0001b, 01h
Type:
8-bits, read/write
Power-On Default Value: 0000 0000b, 00h
no interrupts pending
Command_byte addess: 0000 0011b, 03h
Type:
8-bits, read only
Bit Name: DIRn
Function: Selects data direction, input or output, of Pn
Operation: 1 = output
0 = input
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and
/SHDN. The DIR register has no effect on
these I/O bits while in Fan Mode.
Bit Name:
Function:
October 2006
Sn
Flag for Pn input-change event when Pn is
configured as an input; Sn is set when the
corresponding input changes state.
Operation: 1 = change occurred
0 = no change occurred
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and
/SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
All status bits are cleared after any read
operation is performed on STATUS.
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Micrel, Inc.
MIC74
Fan Speed Register
Interrupt Mask Register
INT_MASK
FAN_SPEED
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
D[7]
D[6]
D[5]
D[3]
D[2]
Always write as zero
D[1]
D[0]
Fan Speed
Power-On Default Value: 0000 0000b, 00h
fan off
Command_byte addess: 0000 0110b, 06h
Type:
8-bits, read/write
Power-On Default Value:0000 0000b, 00h
Command_byte addess: 0000 0100b, 04h
Type:
8-bits, read/write
Bit Name:
Function:
IMn
Interrupt enable bit for Pn when Pn is
configured as an input
Operation: 1 = enabled
0 = disabled
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and
/SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
Bit Name: D[0] through D[2]
Function: Determines bit-pattern on FS[2:0]
Operation:
Data Register
DATA
Output State
D[2:0]
Value
/FS[2:0]
/SHDN
000
111
0
off
001
110
1
speed 1 (slowest)
010
101
1
speed 2
011
100
1
speed 3
100
011
1
speed 4
101
010
1
speed 5
1
speed 6
1
speed 7 (fastest)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
110
001
P7
P6
P5
P4
P3
P2
P1
P0
111
000
Fan Speed
Fan Speed Settings
Power-On Default Value: 1111 1111b, FFh
Command_byte addess: 0000 0101b, 05h
Type:
8-bits, read/write
Notes:
Bit Name:
Function:
Pn
Returns the current state of any Pn configured
as an input and the last value written to Pn’s
configured as outputs; Writing the DATA
register sets the output state of any Pn’s
configured as outputs; writes to I/O bits
configured as inputs are ignored
Read Operation: 1 = Pn is high
0 = Pn is low
Write Operation: 1 = Pn is set to one
0 = Pn is cleared
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and
/SHDN. The state of these pins is determined
by the FAN_SPEED register. While in Fan
Mode, D[7:4] of the DATA registers have no
effect.
October 2006
D[4]
Any time the fan speed register contains zero,
that is, the fan is shut down, and a non-zero
value is written into the fan speed register, the
/FS[2:0] and /SHDN outputs will assume the
highest fan speed state for approximately one
second (tSTART). Following this interval, the
state of the fan speed control outputs will
assume the value indicated by the contents of
FAN_SPEED. This insures that the fan will
start reliably when low speed operation is
desired.
Bit Name: D[3] through D[7]
Function: Reserved
Operation: Always write as zero
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Micrel, Inc.
MIC74
Functional Diagram
INTn
IMn
STATUSn
Q
S
Q
R
EDGE
DETECT
STATUS_READn
VDD
DATAn
(INPUT)
OUT_CFGn
Pn (typical I/O port)
DIRn
DATAn
(OUTPUT)
GND
Typical I/O Port (Fan Speed Control Logic Not Shown)
A2, A1 and A0 should be connected to GND or VDD.
The state of these pins is sampled only once at device
power-on. New slave addresses are not accepted unless
the MIC74 is powered off then on.
Functional Description
Pin Descriptions
VDD
Power supply input connection. See “Operating Ratings.”
A2
0
0
0
0
1
1
1
1
GND
Ground or return connection for all MIC74 functions.
CLK
An CLK signal is provided by the host (master) and is
common to all devices on the bus. The CLK signal
controls all transactions in both directions on the bus and
is applied to each MIC74 at the CLK pin.
DATA
Serial data is bidirectional and is common to all devices
on the bus. The MIC74’s DATA output is open-drain.
The DATA line requires one external pull-up resistor or
current source per system that can be located anywhere
along the line.
MIC74 Slave Address
Bianary
010 0000b
010 0001b
010 0010b
010 0011b
010 0100b
010 0101b
010 0110b
010 0111b
Hex
20h
21h
22h
23h
24h
25h
26h
27h
Table 1. MIC74 Address Configuration
Alert Response Address
The MIC74 also responds to the ARA (Alert Response
Address). The ARA is used by the master (host) to
request the address of a slave that has provided an
interrupt to the master via the /ALERT line.
The ARA is a single address (0001 100) common to all
slaves and is described in more detail under “Interrupt
Generation” with related information under “/ALERT.”
Also see Figure 7.
A2, A1, A0
An MIC74 responds to its own unique address which is
assigned using the A0–A2 pins. A0–A2 set the three
LSBs (least significant bits) of the MIC74’s 7-bit slave
address. The three address pins allow eight unique
MIC74 addresses in a system. When the MIC74’s
address matches an address received in the serial bit
stream, communication is initiated.
October 2006
Inputs
A1
A0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
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Micrel, Inc.
MIC74
Similarly, the write-byte operation consists of sending
the device’s slave address followed by a command byte
and the byte to be written to the target register. Again, in
the case of the MIC74, the command byte is the address
of the target register. See Table 2.
In addition, to the read byte and write byte protocols, the
MIC74 adheres to the SMBus protocol for response to
the ARA (alert response address). An MIC74 expects to
be interrogated using the ARA when it has asserted its
/ALERT output. /ALERT interrupts can be enabled or
disabled using the IE bit in the DEV_CFG register.
Pn, /SHDN, and /FS0–/FS2
P0 through P7 are general-purpose input/output bits.
Each bit is independently programmable as an input or
an output. If programmed as an output, each bit is
further programmable as either a complementary pushpull or open-drain output.
If properly enabled, any Pn programmed as an input will
generate an interrupt to the host using the /ALERT
output when the input changes state. In this way, the
MIC74 can notify the host of an input change without
requiring periodic polling by the host or a message
transaction on the bus.
Regardless of whether interrupts are enabled or
disabled, each input-change event also sets the
corresponding bit in the status register. I/O configuration
is performed using the output configuration (OUT_CFG),
I/O direction (DIR), and interrupt mask (INT_MASK)
registers.
If the FAN bit in the device configuration register is set,
the states of P[7:4] are controlled by the FAN_SPEED
register. The bits in the OUT_CFG, DIR, and INT_MASK
registers corresponding to P[7:4] are ignored. When in
Fan Mode, P[7:4] are referred to as /FS2, /FS1, /FS0,
and /SHDN. While in this mode, no interrupts of any kind
will be generated by these pins.
Power-On
When power is initially applied, the MIC74’s internal
registers will assume their power-up default state and
the state of the address inputs, A2, A1 and A0, will be
read to establish the device’s slave address. See the
individual register descriptions for each registers default
state. Also see Table 2.
I/O Ports
Each I/O bit, P0 through P7, may be individually
programmed as an input or output using the
corresponding bit in the I/O direction register, DIR.
If programmed as an output, each is further
programmable as either a complementary push-pull or
open-drain output using the output configuration register,
OUT_CFG.
If enabled by the corresponding bit, IMn, in the interrupt
mask register INT_MASK, each Pn programmed as an
input will generate an interrupt to the host on /ALERT if
the input changes state. In this way, the MIC74 can
notify the host of an input change without requiring
periodic polling by the host or a transaction on the bus.
Each input-change event also sets the corresponding bit
in the status register, STATUS.
See “Functional Diagram” for the logic arrangement of
atypical MIC74 I/O port.
/ALERT
The alert signal is an open-drain, active-low output. The
operation of the /ALERT output is controlled by the IMn
bits in the INT_MASK register and the global interrupt
enable bit (IE) in the DEV_CFG register.
If the IE bit is set to zero, or if the corresponding interrupt
enable bit, IMn, is set to zero, no input-change interrupts
will be generated. (Regardless of the IE bit setting, the
change will be reflected in the status register.)
If the IE bit is set to one, IMn is set to one, and Pn is an
input, then /ALERT is driven active whenever Pn
changes state, (goes from a high-to-low or low-to-high
state). Once triggered, /ALERT is unconditionally reset
to its inactive state once the MIC74 successfully
responds to the alert response addressor STATUS is
read.
Fan Speed Control
If the FAN bit in the device configuration register is set,
the state of P[7:4] is controlled by the FAN_SPEED
register. The bits in the OUT_CFG, DIR, and INT_MASK
registers corresponding to P[7:4] are ignored. When in
Fan Control Mode, P[7:4] are referred to as /FS2, /FS1,
/FS0, and /SHDN. While in this mode, no interrupts of
any kind will be generated by these pins. See
“Applications Information” for typical fan speed control
applications.
Serial Port Operation
The MIC74 uses standard SMBus Read_Byte and
Write_Byte operations to communicate with its host.
The Read_Byte operation is a composite read-write
operation consisting of first sending the MIC74’s slave
address followed by a command byte (a write) and then
resending the slave address and clocking out the data
byte (a read). The command byte is the address of the
target register. See Table 2. An example of a Read_Byte
operation is shown in Figure 8.
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Micrel, Inc.
MIC74
Register
Name
Register
Description
DEV_CONFIG
DIR
OUT_CFG
STATUS
INT_MASK
DATA
FAN_SPEED
Device Configuration
I/O Direction
Output Configuration
Interrupt Status
Interrupt Mask
General-Purpose I/O
Fan Speed
Address
Binary
0000 0000b
0000 0001b
0000 0010b
0000 0011b
0000 0100b
0000 0101b
0000 0110b
Hex
00h
01h
02h
03h
04h
05h
06h
Available
Operations
8-bit read/write
8-bit read/write
8-bit read/write
8-bit read
8-bit read/write
8-bit read/write
8-bit read/write
Power-On Default
Binary
Hex
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
1111 1111b
FFh
0000 0000b
00h
Table 2. Register Summary
half of tSTART, the /SHDN pin is deasserted. Conversely,
when the fan is shutdown (zero is written to
FAN_SPEED), the /SHDN pin is deasserted first. The
/FS[2:0] lines are subsequently deasserted after a delay
of 1⁄2tSTART. The internal oscillator is also powered down
following the tSTART/2 interval at fan shut-down. These
timing relationships are illustrated in Figure 2.
Fan Start-Up
Any time the fan speed register contains zero (fan is off)
and then a nonzero value is written to FAN_SPEED, the
/FS[2:0] and /SHDN outputs will assume the highest fan
speed state for approximately one second (tSTART).
Following this interval, the state of the fan speed control
outputs will assume the value indicated by the contents
of FAN_SPEED. This insures that the fan will start
reliably when low speed operation is desired. The tSTART
interval is generated by an internal oscillator and
counters. At the end of tSTART, this oscillator is powered
down to reduce overall power consumption.
Interrupt Generation
Assuming that any or all of the I/O’s are configured as
inputs, the MIC74 will reflect the occurrence of an input
change in the corresponding bit in the status register,
STATUS. This action cannot be masked. An input
change will only generate an interrupt to the host if
interrupts are properly configured and enabled.
The MIC74 can operate in either polled mode or interrupt
mode. In the case of polled operation, the host
periodically reads the contents of STATUS to determine
the device state. The act of reading STATUS clears its
contents. Repeating events which have occurred since
the last read from STATUS will not be discernable to the
host.
Interrupts are only generated if the global interrupt
enable bit, IE, in the DEV_CFG register is set. The
/ALERT signal will be asserted (driven low) when an
interrupt is generated. The MIC74 expects to be
interrogated using the ARA when it has generated an
interrupt output. Once it has successfully responded to
the ARA (Alert Response Address), the /ALERT output
will be deasserted. The contents of the status register
will not be cleared until it is read using a read byte
operation.
If a given system does not wish to use the SMBus ARA
protocol for reporting interrupts, the system may simply
poll the contents of the status register after detecting an
interrupt on /ALERT. This action will clear the contents of
STATUS and cause /ALERT to be deasserted. Reading
the status register is an acceptable substitute for using
the ARA protocol. Presumably, however, it will involve
higher system overhead since all the devices on the bus
must be polled to determine which one generated the
interrupt.
Regulator
RPULL-UP
VIN VOUT
/SHDN FB
GND
RFB
FAN
/SHDN
/FS2
RF2
/FS1
RF2
/FS0
RF2
RMIN_SPEED
MIC74
Figure 1. Fan Speed Control Application
Proper sequencing of the /FS[2:0] and /SHDN signals is
performed by the MIC74’s internal logic state machine.
When activating the fan from the off state, the /FS[2:0]
lines change state first, then, after a delay equal to oneOctober 2006
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Micrel, Inc.
MIC74
Fan Supply
Output
Voltage*
shutdown
Value written to
FAN_SPEED (00h)
Fan
Rotation
Speed*
01h
tSTART
01h
02h
07h
05h
shutdown
00h
* FAN SUPPLY OUTPUT VOLTAGE AND
SPEED ARE NOT TO SCALE.
/FS2
/FS1
tSTART/2
/FS0
tSTART/2
/SHDN
Figure 2. Typical MIC74 Fan-Mode Timing and System Behavior
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MIC74
Application Information
DATA
Bit Transfer
The data received on the DATA pin must be stable
during the high period of the clock.
CLK
DATA
StoP
Start
Data Stable,
Data Valid
CLK
Figure 4. Start and Stop Definitions
Start (S) and stop (P) conditions are always generated
by the bus master (host). After a start condition, the bus
is considered to be busy. The bus becomes free again
after a certain time following a stop condition or after
both CLK and DATA lines remain high for more than
50µs.
Data Change Allowed
Figure 3. Acceptable Bit Transfer Conditions
Data can change state only when the CLK line is low.
Refer to Figure 3.
Serial Byte Format
Every byte consists of 8 bits. Each byte transferred on
the bus must be followed by an acknowledge bit. Bytes
are transferred with the MSB (most significant bit) first.
See Figure 5.
Start and Stop Conditions
Two unique bus situations define “start” and “stop”
conditions. A high-to-low transition of the DATA line
while CLK is high indicates a start condition. A low-tohigh transition of the DATA line while CLK is high
defines a stop condition. See Figure 4.
MSB
LSB
DATA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
CLK
ACK
Start
ACK
Byte Complete
StoP
Figure 5. Serial Byte Format
MSB
Acknowledge and Not Acknowledge
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high)
during the acknowledge clock cycle.
In order to acknowledge (ACK) a byte, the receiver must
pull the DATA line low during the high period of the clock
pulse according the bus timing specifications. A slave
device that wishes to not acknowledge a byte must let
the DATA line remain high during the acknowledge clock
pulse. See Figure 6.
October 2006
LSB
DATA
(Host)
NAK (high)
DATA
(Slave MIC74)
1
2
3
4
5
6
7
8
9
ACK (low)
CLK
ACK
Figure 6. Acknowledge and Not Acknowledge
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MIC74
Master-to-slave transmission
Slave-to-master response
R/W = READ
NOT ACKNOWLEDGE
ACKNOWLEDGE
STOP
S 0 0 0 1 1 0 0 1 A 0 1 0 0 A2 A1 A0 0 /A P
Alert Response Address
(master requests address
of interupting device)
Slave Address
(interrupting MIC74
announces its address)
P0*
t/INT
t/IR
/ALERT
* Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
Figure 7. Interrupt Handling Using the Alert Response Address
Master-to-slave transmission
Slave-to-master response
R/W = WRITE
R/W = READ
ACKNOWLEDGE
ACKNOWLEDGE
NOT ACKNOWLEDGE
ACKNOWLEDGE
STOP
S 0 0 0 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1 A S 0 0 0 1 A2 A1 A0 1 A X X X X X X X X /A P
Slave Address
(host addresses an MIC74)
Command Byte
(03h = selects status register)
Slave Address
(host addresses an MIC74)
Status Value†
(MIC74 sends status)
P0*
t /INT
t/R
/ALERT
* Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
† STATUS
register is cleared to zero following this
operation.
Figure 8. Interrupt Handling Without the Alert Response Address
October 2006
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Micrel, Inc.
MIC74
1.
2.
3.
4.
5.
6.
7.
Write DATA
Write OUT_CFG
Write DIR
Write FAN_SPEED (if using fan mode)
Write INT_MASK (if using interrupts)
Read STATUS to clear it.
Write DEV_CFG to enable fan mode and/or
interrupts, if using
At the conclusion of step three, any I/O’s configured as
outputs in step two will be driven to the levels
programmed into the data register in step one. The order
of step 1 through step 3 is important to insure that
spurious data does not appear at the I/O’s during
configuration. Following step 7, programming the device
configuration register, the MIC74 will begin generating
interrupts if they are enabled, and the fan will be started
if FAN_SPEED contains a nonzero value. The corresponddding interrupt service routines (if any) must be
initialized and enabled prior to step seven. STATUS
should be cleared (step 6) in both polled and interrupt
driven systems.
Initializing the MIC74
The MIC74’s internal registers are reset to their default
state at power-on. The MIC74’s default state can be
summarized as follows:
•
•
All I/O’s configured as inputs (DIR = 00h)
Output configuration set to opendrain(OUT_CFG = 00h)
• All outputs high/floating (DATA = FFh)
• Fan functions disabled (FAN_SPEED =
00h,FAN bit of DEV_CFG = 0)
• All interrupts masked (IE bit of DEV_CFG = 0)
The result of this configuration is that all I/O pins will
essentially float unless driven by external circuitry. Any
system using the MIC74 will need to initialize the internal
registers to the state required for proper system
operation. The recommended order for initializing the
MIC74’s registers is as follows:
Initialize for
interrupts
Write desired ouput
values to DATA
Initialize for
polling
Set output configuration
in OUT_CFG
Write desired output
values to DATA
Set desired I/O's as
outputs by writing DIR
Set output configuration
in OUT_CFG
Set initial fan speed in
FAN_SPEED (if using)
Set desired I/O's as
outputs by writing DIR
Write INT_MASK to
enable interrupts
(if using)
Set initial fan speed in
FAN_SPEED (if using)
Read STATUS to
clear it
Write DEV_CFG to
turn on fan (if using)
Read STATUS
to clear it
Write DEV_CFG to
turn on interrupts
and fan (if using)
Initialization
complete
Initialization
complete
Figure 9a. Initializing the MIC74 for Polled Operation
Figure 9b. Initializing the MIC74 for Interrupts
October 2006
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MIC74
Interrupt Mode
Input state changes on I/Os configured as inputs will be
reflected in the status register regardless of the state of
the global interrupt enable bit (IE) and the individual
interrupt mask bits in INT_MASK. In a system utilizing
interrupts to detect input changes, one or more of the
bits in the interrupt mask register, INT_MASK, are set to
allow interrupts on/ALERT to be generated by input
events. The global interrupt enable bit, IE, in the device
configuration register must also be set to enable
interrupts.
The flowchart shown in Figure 9b illustrates the steps
involved in initializing the MIC74 for interrupt-driven
operation. The flowchart in Figure 11 illustrates the
corresponding interrupt service routine using the SMBus
ARA (alert response address). The corresponding timing
diagram is shown in Figure 7. The flowchart in Figure 12
illustrates the corresponding interrupt service routine
using polling to determine the interrupt source. Figure 8
illustrates the timing. Utilizing the ARA greatly speeds
identification of the interrupting slave device and lowers
latency, as only a single transaction on the bus is
necessary to identify the interrupt source.
Using either method, STATUS must be read to determine the exact source of the interrupt within the MIC74.
Polled Mode
Input state changes on I/O’s configured as inputs will be
reflected in the status register regardless of the state of
the global interrupt enable bit (IE) and the individual
interrupt mask bits in INT_MASK. In a system utilizing
polling to monitor for input changes, the status register is
periodically read to check for input events. The act of
reading STATUS clears it in preparation for detecting
future events. The status bits corresponding to I/O’s
configured as outputs or corresponding to P[7:4] when in
fan mode will not be set by state changes on these pins.
It is always good practice, however, to mask the value
obtained when reading STATUS to eliminate any bits,
output or otherwise, that are not of immediate concern.
This will help avoid problems if software changes are
made in the future.
The flowchart shown in Figure 9a illustrates the steps
involved in initializing the MIC74 for polled operation.
The flowchart in Figure 10 illustrates the corresponding
polling routine. The process for writing output data is
straight-forward—simply write the desired bit pattern to
DATA. (Special precautions may be required when
changing output data in an interrupt driven system,
however. See the discussion below under “Writing to the
Data Register.”)
Polling the
MIC74
Read
STATUS
Is
STATUS
?
No
h
Yes
Is
Sn set
?
Yes
Service function n
No
Is
Sm set
?
Yes
Service function m
No
Is
Sx set
?
Yes
Service function x
No
Figure 10. Polling the MIC74
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Micrel, Inc.
MIC74
The act of reading STATUS clears it in preparation for
detecting future events. The status bits corresponding to
I/O’s configured as outputs or corresponding to P[7:4]
when in fan mode will not be set by state changes on
these pins. It is always good practice, however, for the
interrupt service routine to mask the value obtained
when reading STATUS to eliminate any bits, output or
otherwise, that are not of immediate concern. This will
help avoid problems if software changes are made in the
future.
The process for writing output data is straight-forward—
simply write the desired bit pattern to DATA. Special
precautions may be required, however, when changing
output data in an interrupt driven system. See the
discussion below under “Writing to the Data Register.”
Writing To The Data Register
Multiple software routines may use the various output
bits available on the MIC74 to control individual functions
such as power switches, LED’s, etc. These various
functions may be handled by independent software
routines which must manipulate individual output bits
without regard for other bits. Care must be taken to
insure that these various software routines do not
interfere with each other when modifying output data.
The recommended procedure for changing isolated
output bits is as follows:
1. Read DATA
2. Set desired bits by ORing the value read from
DATA with an appropriate mask value
3. Clear desired bits by ANDing the value read
from DATA with an appropriate mask value
4. Write the result back to DATA
A functionally equivalent alternative to this procedure is
to keep an image of the data register in software. Any
independent routines would make changes to this image
using the procedure above and then call a routine that
actually writes the new image to DATA. Interrupts would
be disabled briefly while DATA is being modified.
Interrupt Service
Routine
Read alert
response address
Is
interrupt
from
MIC74
No
Service other devices
Polled
I.S.R.
Yes
Read
STATUS
Read STATUS to
determine source
Is
Sn set
?
Is
STATUS
Yes
Service function n
?
Service other devices
h
Yes
No
Is
Sm set
?
No
Is
Sn set
?
Yes
Service function m
Yes
Service function n
No
No
Is
Sx set
?
Is
Sm set
?
Yes
Service function x
Yes
Service function m
No
No
Yes
Is
Sx set
?
Interrupts
pending
?
Service function x
No
No
Return from ISR
Return from ISR
Figure 12: Interrupt Service Routine Without ARA
Figure 11: Interrupt Service Routine Using the ARA
October 2006
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Micrel, Inc.
MIC74
equivalent resistance seen in the regulator’s feedback
path, thus changing the output voltage.
Any conventional adjustable regulator is usually suitable
for use with the MIC74. The output voltage corresponding to each value to be programmed into the fan speed
register can be determined by selecting the resistors in
the circuit. The regulator itself can be chosen to meet the
needs of the application, such as input voltage, output
voltage, current handling capability, maximum power
dissipation, and physical space constraints. Two circuit
examples are shown below.
The circuit of Figure 13 illustrates use of a typical LDO
linear regulator such as the MIC29152. A switching
regulator-based fan control circuit using the MIC4574
200kHz Simple 0.5A Buck Regulator is shown in Figure
14. Both circuits assume a 12V fan power supply but will
accommodate much higher input voltages if required
(MIC4574: 24V, MIC29152:26V). Care must be taken,
however, to insure that the maximum power dissipation
of the regulator is not exceeded. If the regulator
overheats, its internal thermal shutdown circuitry will
deactivate it. (See MIC29152 or MIC4574 datasheet.)
Since the MIC74 powers up with all its I/O’s inputs
(floating), both circuits will power-up with the fan running
at a minimum speed determined by the value of
RMIN_SPEED. Once the MIC74’s fan mode is activated
by setting the appropriate bit in the configuration register,
Regardless of which procedure is used, it is important
that only one software routine at a time attempts to make
changes to the output data. In a system where polling is
the exclusive method for servicing inputs, this is usually
not a problem. If interrupts are employed to any degree
in dealing with MIC74 inputs, care must be taken to
insure that a software routine in the midst of making
changes to outputs is not interrupted by another routine
that proceeds to make its own changes. The risk is that
the value in DATA will be changed by an interrupting
routine after it is read by a different routine in the
process of making its own changes. If this occurs, the
value written to DATA by the first routine may be
incorrect. The most straight-forward solution to this
potential problem is to disable system interrupts while
the data register is actually being modified.
Application Circuits
The MIC74, in conjunction with a linear low-dropout or
switching regulator, can be configured as a fan speed
controller. Most adjustable regulators have a feedback
pin and use an external resistor divider to adjust the
output voltage. The MIC74 is designed to take adventage of this configuration with its ability to manipulate
multiple feedback resistors connected to the P4–P7
outputs. Individual open-drain output bits are selectively
grounded or allowed to float under the control of the
internal state machine. This action raises or lowers the
MIC29152
+12V
+3.3V
OUT
IN
C1
10µF
RFB
3k
FB
EN
RPU
100k
GND
FAN
A-Speed
HP2A-B3
or similar
C3
220µF
MIC74
VDD
SMBCLK
SMBus
Host
/SHDN
RF2
/FS2
RF1
/FS1
SMBDATA
SMBALERT /FS0
C4
0.1µF
A2
P3
A1
P2
A0
P1
GND
P0
RF0
1k
1.8k
3.5k
RMIN_SPEED
1k
Figure 13.Fan Speed Control Using an Adjustable Low-Dropout Regulator
+3.3V
RPU
200k
RBASE
150k
+3.3V
C4
0.1µF
2N3906
Q1
100k
C1
10µF
MIC4574
SW
L1 100µH
SHDN
FB
SGND PGND
C2
3300pF
IN
RFB
3k
C3
220µF
D1
MIC74
VDD
SMBCLK
SMBus
Host
+12V
/SHDN
/FS2
SMBDATA
/FS1
SMBALERT
A2
/FS0
P3
A1
A0
P2
P1
GND
P0
FAN
A-Speed
HP2A-B3
or similar
RF2
RF1
1.8k
1k
RF0
3.5k
RMIN_SPEED
1k
Figure 14.Fan Speed Control Using a Buck Converter
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MIC74
The following equations show how to calculate the
resistor values for the fan controllers. For example, when
the fan speed register contains 011b, which is the 3rd
lowest speed, RF1 and RF0 are parallel to RMIN to give the
equivalence resistor (REQ) value of 545Ω.
REQ = RF1 || RF0 || RMIN
REQ = 1.8k || 3.6k || 1k
REQ = 545Ω
The output voltage is calculated by using:
the fan will be shutdown by the assertion of the /SHDN
output if FAN_SPEED is zero. If FAN_SPEED is
programmed with any nonzero value, the fan will be
driven to its maximum speed for the duration of tSTART
(about 1 second) and then assume the programmed
speed. Note that the circuit in Figure 14 contains an
additional transistor, Q1, as an inverter because the
regulator in this example has an active-high shutdown
input rather than an enable input. Otherwise the circuits
function identically.
Table 3 lists the output voltages corresponding to all the
fan speeds and system states possible with these
circuits. The following equations are used to calculate
the resistor values used in MIC74 fan speed control
circuits. It is assumed here that the regulator’s internal
reference voltage is 1.24V. If the regulator uses a
different reference voltage, that value should be used
instead.
⎛
R
VOUT = 1.24V ⎜⎜1 + FB
R EQ
⎝
⎞
⎟
⎟
⎠
3k ⎞
⎛
VOUT = 1.24V ⎜1 +
⎟
545Ω
⎝
⎠
VOUT = 8.06V
FAN_SPEED
Value
Fan Speed
Selected
RFB
RMIN
RF2
RF1
RF0
REQ
VOUT
0000 0000b
power-up
3k
1k
open
open
open
1k
4.96V
0000 0000b
fan off
3k
1k
open
open
open
1k
0V
0000 0001b
lowest
3k
1k
open
open
3.6k
783
5.99V
1k
open
1.8k
open
643
7.03V
0000 0010b
nd
lowest
3k
0000 0011b
rd
3 lowest
3k
1k
open
1.8k
3.6k
545
8.06V
0000 0100b
medium
3k
1k
1k
open
open
500
8.68V
0000 0101b
3 highest
rd
3k
1k
1k
open
3.6k
439
9.71V
3k
1k
1k
1.8k
open
391
10.75V
3k
1k
1k
1.8k
3.6k
353
11.78V
0000 0110b
0000 0111b
2
nd
2
highest
highest
Table 3. Fan Speed Selection
October 2006
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Micrel, Inc.
MIC74
Package Information
16-Pin QSOP (QS)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2000 Micrel, Incorporated.
October 2006
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M9999-101006
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