TI1 HPA01203YFFR 3.2-w mono filter-free class-d audio power amplifier with auto-recovering short-circuit protection Datasheet

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TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015
TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier
With Auto-Recovering Short-Circuit Protection
1 Features
3 Description
•
The TPA2011D1 is a 3.2-W high efficiency filter-free
class-D audio power amplifier (class-D amp) in a
1.21 mm × 1.16 mm wafer chip scale package
(DSBGA) that requires only three external
components.
1
•
•
•
•
•
•
•
Powerful Mono Class-D Amplifier
– 3.24 W (4 Ω, 5 V, 10% THDN)
– 2.57 W (4 Ω, 5 V, 1% THDN)
– 1.80 W (8 Ω, 5 V, 10% THDN)
– 1.46 W (8 Ω, 5 V, 1% THDN)
Integrated Feedback Resistor of 300 kΩ
Integrated Image Reject Filter for DAC Noise
Reduction
Low Output Noise of 20 μV
Low Quiescent Current of 1.5 mA
Auto Recovering Short-Circuit Protection
Thermal Overload Protection
9-Ball, 1.21mm x 1.16 mm 0.4 mm Pitch DSBGA
Device Information(1)
PART NUMBER
TPA2011D1
2 Applications
•
•
•
Features like 95% efficiency, 86-dB PSRR, 1.5 mA
quiescent current and improved RF immunity make
the TPA2011D1 class-D amp ideal for cellular
handsets. A fast start-up time of 4 ms with no audible
turn-on pop makes the TPA2011D1 ideal for PDA
and smart-phone applications. The TPA2011D1
allows independent gain while summing signals from
separate sources, and has a low 20 μV noise floor.
Wireless or Cellular Handsets and PDAs
Portable Navigation Devices
General Portable Audio Devices
PACKAGE
DSBGA (9)
BODY SIZE (NOM)
1.60 mm x 1.21 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
EN
TPA2011D1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 15
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Applications .............................................. 18
11 Power Supply Recommendations ..................... 21
11.1 Power Supply Decoupling Capacitors................... 21
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Example .................................................... 23
13 Device and Documentation Support ................. 24
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
14 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2010) to Revision B
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Original (December 2009) to Revision A
•
2
Page
Page
Changed the Package Dimensions table. D was Max = 1244μm, Min = 1184μm. E was Max = 1190μm, Min =
1130μm .................................................................................................................................................................................. 1
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5 Device Comparison Table
DEVICE NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER (W)
PSRR (dB)
TPA2011D1
Mono
Class D
3.2
86
TPA2005D1
Mono
Class D
1.4
75
TPA2010D1
Mono
Class D
2.5
75
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6 Pin Configuration and Functions
IN+
GND
VO-
A1
A2
A3
VDD
PVDD
PGND
B1
B2
B3
IN-
EN
VO+
C1
C2
C3
1.160 mm
YFF Package
9-Pin DSBGA
Top View
1.214 mm
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
EN
C2
I
Shutdown terminal. When terminal is low the device is put into Shutdown mode.
GND
A2
I
Analog ground terminal. Must be connected to same potential as PGND using a direct connection
to a single point ground.
IN–
C1
I
Negative differential audio input
IN+
A1
I
Positive differential audio input
PGND
B3
I
High-current Analog ground terminal. Must be connected to same potential as GND using a direct
connection to a single point ground.
PVDD
B2
I
High-current Power supply terminal. Must be connected to same power supply as VDD using a
direct connection. Voltage must be within values listed in Recommended Operating Conditions
table.
VDD
B1
I
Power supply terminal. Must be connected to same power supply as PVDD using a direct
connection. Voltage must be within values listed in Recommended Operating Conditions table.
VO-
A3
O
Negative BTL audio output
VO+
C3
O
Positive BTL audio output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, TA = 25°C (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
6
V
In shutdown mode
–0.3
6
V
–0.3
VDD + 0.3
VDD, PVDD
Supply
voltage
In active mode
VI
Input
voltage
EN, IN+, IN–
RL
Minimum load resistance
Ω
3.2
Output continuous total power dissipation
V
See Dissipation Ratings
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
260
°C
85
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Tstg
(1)
4
Storage temperature
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VDD
Class-D supply voltage
VIH
High-level input voltage
EN
VIL
Low-level input voltage
EN
RI
Input resistor
Gain ≤ 20 V/V (26 dB)
VIC
Common mode input voltage range
VDD = 2.5V, 5.5V, CMRR ≥ 49 dB
TA
Operating free-air temperature
MIN
MAX
2.5
5.5
UNIT
V
1.3
V
0.35
15
V
kΩ
0.75 VDD-1.1
V
–40
°C
85
7.4 Thermal Information
TPA2011D1
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance
107
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.9
°C/W
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
3.8
°C/W
ψJB
Junction-to-board characterization parameter
18
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
|IIH|
High-level input current
VDD = 5.5 V, VEN = 5.5 V
|IIL|
Low-level input current
VDD = 5.5 V, VEN = 0 V
I(Q)
Quiescent current
TYP
MAX
UNIT
1
5
mV
50
μA
1
μA
VDD = 5.5 V, no load
1.8
2.5
VDD = 3.6 V, no load
1.5
2.3
VDD = 2.5 V, no load
1.3
2.1
0.1
2
μA
300
350
kHz
285/RI 300/RI
315/RI
V/V
I(SD)
Shutdown current
VEN = 0.35 V, VDD = 2.5 V to 5.5 V
RO, SD
Output impedance in shutdown mode
VEN = 0.35 V
f(SW)
Switching frequency
VDD = 2.5 V to 5.5 V
AV
Gain
VDD = 2.5 V to 5.5 V, RI in kΩ
REN
Resistance from EN to GND
2
250
kΩ
300
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kΩ
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7.6 Operating Characteristics
VDD = 3.6 V, TA = 25°C, AV = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
THD + N = 10%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
PO
Output power
THD + N = 10%, f = 1 kHz, RL = 8 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
Vn
VDD = 3.6 V, Inputs AC grounded
with CI = 2μF, f = 20 Hz to 20 kHz
Noise output voltage
THD+N
Total harmonic distortion
plus noise
MIN
TYP
VDD = 5 V
3.24
VDD = 3.6 V
1.62
VDD = 2.5 V
0.70
VDD = 5 V
2.57
VDD = 3.6 V
1.32
VDD = 2.5 V
0.57
VDD = 5 V
1.80
VDD = 3.6 V
0.91
VDD = 2.5 V
0.42
VDD = 5 V
1.46
VDD = 3.6 V
0.74
VDD = 2.5 V
0.33
A-weighting
20
No weighting
25
VDD = 5.0 V, PO = 1.0 W, f = 1 kHz, RL = 8 Ω
0.11%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz, RL = 8 Ω
0.05%
VDD = 2.5 V, PO = 0.2 W, f = 1 kHz, RL = 8 Ω
0.05%
VDD = 5.0 V, PO = 2.0 W, f = 1 kHz, RL = 4 Ω
0.23%
VDD = 3.6 V, PO = 1.0 W, f = 1 kHz, RL = 4 Ω
0.07%
VDD = 2.5 V, PO = 0.4 W, f = 1 kHz, RL = 4 Ω
0.06%
MAX
UNIT
W
W
W
W
μVRMS
AC power supply rejection
ratio
VDD = 3.6 V, Inputs AC grounded with CI = 2 μF,
200 mVpp ripple, f = 217 Hz
86
dB
CMRR
Common mode rejection
ratio
VDD = 3.6 V, VIC = 1 VPP, f = 217 Hz
79
dB
TSU
Startup time from
shutdown
VDD = 3.6 V
4
ms
VDD = 3.6 V, VO+ shorted to VDD
2
VDD = 3.6 V, VO– shorted to VDD
2
VDD = 3.6 V, VO+ shorted to GND
2
VDD = 3.6 V, VO– shorted to GND
2
VDD = 3.6 V, VO+ shorted to VO–
2
PSRR
IOC
TSD
Overcurrent protection
threshold
Time for which output is
disabled after a shortcircuit event, after which
auto-recovery trials are
continuously made
VDD = 2.5 V to 5.5 V
A
100
ms
7.7 Dissipation Ratings
(1)
6
PACKAGE
DERATING FACTOR (1)
TA < 25°C
TA = 70°C
TA = 85°C
YFF (DSBGA)
4.2 mW/°C
525 mW
336 mW
273 mW
Derating factor measure with high K board.
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7.8 Typical Characteristics
100
100
90
90
80
80
70
70
60
50
40
RL = 8 Ω + 33 µH
Gain = 6 dB
30
20
η − Efficiency − %
η − Efficiency − %
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
50
40
RL = 4 Ω + 33 µH
Gain = 6 dB
30
20
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
10
60
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
10
0
0.0
2.0
0.4
0.8
1.2
PO − Output Power − W
Figure 1. Efficiency vs Output Power
0.4
1.6
2.0
2.4
2.8
3.2
3.6
PO − Output Power − W
Figure 2. Efficiency vs Output Power
0.6
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
VDD = 3.6 V
Gain = 6 dB
VDD = 5.0 V
Gain = 6 dB
PD − Power Dissipation − W
PD − Power Dissipation − W
0.5
0.3
0.2
0.1
0.4
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0
0.0
2.0
0.4
0.8
1.2
PO − Output Power − W
Figure 3. Power Dissipation vs Output Power
1.0
IDD − Supply Current − A
0.8
2.0
2.4
2.8
3.2
3.6
4.0
Figure 4. Power Dissipation vs Output Power
0.5
RL = 4 Ω + 33 µH
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
0.7
0.6
0.5
0.4
0.3
0.2
RL = 8 Ω + 33 µH
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
0.4
IDD − Supply Current − A
0.9
1.6
PO − Output Power − W
0.3
0.2
0.1
0.1
0.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
PO − Output Power − W
PO − Output Power − W
Figure 5. Supply Current vs Output Power
Figure 6. Supply Current vs Output Power
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Typical Characteristics (continued)
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
2.00
200
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Gain = 6 dB
1.75
IDD − Supply Current − nA
IDD − Supply Current − mA
RL = No Load
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
1.50
1.25
1.00
2.5
3.0
3.5
4.0
4.5
5.0
50
0.1
0.2
0.3
0.4
0.5
VEN − EN Voltage − V
Figure 7. Supply Current vs Supply Voltage
Figure 8. Supply Current vs EN Voltage
4
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 10 %
Frequency = 1 kHz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 1 %
Frequency = 1 kHz
Gain = 6 dB
PO − Output Power − W
4
PO − Output Power − W
100
VDD − Supply Voltage − V
5
3
2
1
0
3
2
1
0
4
4
PO − Output Power − W
150
0
0.0
5.5
Gain = 6 dB
8
12
16
20
24
28
32
4
8
12
16
20
24
28
RL − Load Resistance − Ω
RL − Load Resistance − Ω
Figure 9. Output Power vs Load Resistance
Figure 10. Output Power vs Load Resistance
32
RL = 4 Ω, THD+N = 1 %
RL = 4 Ω, THD+N = 10 %
RL = 8 Ω, THD+N = 1 %
RL = 8 Ω, THD+N = 10 %
3
2
1
Frequency = 1 kHz
Gain = 6 dB
0
2.5
3.0
3.5
4.0
4.5
5.0
VDD − Supply Voltage − V
Figure 11. Output Power vs Supply Resistance
8
Figure 12. THD + Noise vs Output Power
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Typical Characteristics (continued)
THD+N − Total Harmonic Distortion + Noise − %
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
10
1
0.1
0.01
0.001
20
100
PO = 25 mW
PO = 125 mW
PO = 500 mW
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
1
0.1
0.01
0.001
20
100
0.1
0.01
0.001
10k
20k
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
PO = 100 mW
PO = 500 mW
PO = 2 W
1k
f − Frequency − Hz
1k
f − Frequency − Hz
10k
20k
Figure 16. THD + Noise vs Frequency
1
100
20k
PO = 15 mW
PO = 75 mW
PO = 200 mW
VDD = 2.5 V
RL = 8 Ω + 33 µH
Gain = 6 dB
Figure 15. THD + Noise vs Frequency
20
10k
10
20k
10
VDD = 5.0 V
RL = 4 Ω + 33 µH
Gain = 6 dB
1k
f − Frequency − Hz
Figure 14. THD + Noise vs Frequency
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Figure 13. THD + Noise vs Output Power
10
VDD = 3.6 V
RL = 8 Ω + 33 µH
Gain = 6 dB
PO = 50 mW
PO = 250 mW
PO = 1 W
VDD = 5.0 V
RL = 8 Ω + 33 µH
Gain = 6 dB
10
PO = 50 mW
PO = 250 mW
PO = 1 W
VDD = 3.6 V
RL = 4 Ω + 33 µH
Gain = 6 dB
1
0.1
0.01
0.001
20
Figure 17. THD + Noise vs Frequency
100
1k
f − Frequency − Hz
10k
20k
Figure 18. THD + Noise vs Frequency
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Typical Characteristics (continued)
10
PO = 30 mW
PO = 150 mW
PO = 400 mW
VDD = 2.5 V
RL = 4 Ω + 33 µH
Gain = 6 dB
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
20k
1
0.1
0.01
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
−20
−30
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−40
−50
−60
−70
−80
−90
−100
−110
PSRR − Power Supply Rejection Ratio − dB
0
Inputs AC−Grounded
CI = 2 µF
RL = 8 Ω + 33 µH
Gain = 6 dB
−10
−120
Inputs AC−Grounded
CI = 2 µF
RL = 4 Ω + 33 µH
Gain = 6 dB
−10
−20
−30
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−40
−50
−60
−70
−80
−90
−100
−110
−120
20
100
1k
f − Frequency − Hz
10k
20k
20
0
−10
−20
RL = 8 Ω + 33 µH
Frequency = 217 Hz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−30
−40
−50
−60
−70
−80
−90
−100
0.0
100
1k
f − Frequency − Hz
10k
20k
Figure 22. Power Supply Rejection Ratio vs Frequency
CMRR − Common Mode Rejection Ratio − dB
Figure 21. Power Supply Rejection Ratio vs Frequency
−30
VIC = 1 VPP
RL = 8 Ω + 33 µH
Gain = 6 dB
−40
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−50
−60
−70
−80
−90
−100
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
VIC − Common Mode Input Voltage − V
Figure 23. Power Supply Rejection Ratio vs Common Mode
Input Voltage
10
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Figure 20. THD + Noise vs Common Mode Input Voltage
0
PSRR − Power Supply Rejection Ratio − dB
RL = 8 Ω + 33 µH
Frequency = 1 kHz
PO = 200 mW
Gain = 6 dB
VIC − Common Mode Input Voltage − V
Figure 19. THD + Noise vs Frequency
PSRR − Power Supply Rejection Ratio − dB
10
100
1k
f − Frequency − Hz
10k
20k
Figure 24. Common Mode Rejection Ratio vs Frequency
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Typical Characteristics (continued)
CMRR − Common Mode Rejection Ratio − dB
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
0
−10
RL = 8 Ω + 33 µH
Frequency = 217 Hz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
VDD
High – 3.6 V
Amplitude – 500 mV
Duty Cycle – 20%
−20
−30
−40
−50
VOUT
2 mV/div
−60
−70
−80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
5.0
2.5m
5m
10m
12.5m
15m
17.5m
20m
Figure 26. GSM Power Supply Rejection vs Time
VDD - Supply Voltage (dBV)
Figure 25. Common Mode Rejection Ratio vs Common Mode
Input Voltage
VO - Output Voltage (dBV)
7.5m
t – Time – 2.5ms/div
VIC − Common Mode Input Voltage − V
Inputs ac-grounded
Gain = 6 dB
Frequency (Hz)
Figure 27. GSM Power Supply Rejection vs Frequency
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
CI
RI
CI
RI
Measurement
Output
OUT+
IN+
+
TPA2011D1
-
IN-
+
Load
30 kHz
Low Pass
Filter
OUTVDD
Measurement
Input
-
GND
CS1
CS2
+
VDD
-
(1)
Input resistor RI = 150kΩ gives a gain of 6 dB which is used for all the graphs
(2)
CI was shorted for any common-mode input voltage measurement. All other measurements were taken with CI = 0.1μF (unless otherwise noted).
(3)
CS1 = 0.1μF is placed very close to the device. The optional CS2 = 10μF is used for datasheet graphs.
(4)
The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low-pass filter (1kΩ,
4700pF) is used on each output for the data sheet graphs.
Figure 28. Test Setup for Typical Application Graphs
12
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9 Detailed Description
9.1 Overview
The TPA2011D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 3.2W into 4-Ω
load with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications as only three external components are required. The advanced modulation
used in the TPA2011D1 PWM output stage eliminates the need for an output filter.
9.2 Functional Block Diagram
EN
Input
Buffer
SC
300 KΩ
9.3 Feature Description
9.3.1 Fully Differential Amplifier
The TPA2011D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2
regardless of the common-mode voltage at the input. The fully differential TPA2011D1 can still be used with a
single-ended input; however, the TPA2011D1 should be used with differential inputs when in a noisy
environment, like a wireless handset, to ensure maximum noise rejection.
9.3.1.1 Advantages of Fully Differential Amplifiers
• Input-coupling Capacitors Not Required
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example,
if a codec has a midsupply lower than the midsupply of the TPA2011D1, the common-mode feedback
circuit will adjust, and the TPA2011D1 outputs will still be biased at midsupply of the TPA2011D1. The
inputs of the TPA2011D1 can be biased from 0.5 V to VDD –0.8 V. If the inputs are biased outside of that
range, input-coupling capacitors are required.
• Midsupply Bypass Capacitor, C(BYPASS), Not Required
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
• Better RF-Immunity
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
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Feature Description (continued)
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
much better than the typical audio amplifier.
9.3.2 Eliminating the Output Filter With the TPA2011D1
This section focuses on why the user can eliminate the output filter with the TPA2011D1.
9.3.2.1 Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
9.3.2.2 When to Use an Output Filter
Design the TPA2011D1 without an Inductor / Capacitor (LC) output filter if the traces from the amplifier to the
speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used
without an output filter.
The TPA2011D1 does not require an LC output filter for short speaker connections (approximately 100 mm long
or less). A ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter;
and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into
account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower
than rated current values. See the TPA2011D1 EVM User's Guide for components used successfully by TI.
Figure 29 shows a typical ferrite-bead output filter.
Ferrite
Chip Bead
VO−
1 nF
Ferrite
Chip Bead
VO+
1 nF
Figure 29. Typical Ferrite Chip Bead Filter
9.3.3 Short Circuit Auto-Recovery
When a short-circuit event occurs, the TPA2011D1 goes to shutdown mode and activates the integrated autorecovery process whose aim is to return the device to normal operation once the short-circuit is removed. This
process repeatedly examines (once every 100ms) whether the short-circuit condition persists, and returns the
device to normal operation immediately after the short-circuit condition is removed. This feature helps protect the
device from large currents and maintain a good long-term reliability.
9.3.4 Integrated Image Reject Filter for DAC Noise Rejection
In applications which use a DAC to drive Class-D amplifiers, out-of-band noise energy present at the DAC's
image frequencies fold back into the audio-band at the output of the Class-D amplifier. An external low-pass filter
is often placed between the DAC and the Class-D amplifier in order to attenuate this noise.
The TPA2011D1 has an integrated Image Reject Filter with a low-pass cutoff frequency of 130 kHz, which
significantly attenuates this noise. Depending on the system noise specification, the integrated Image Reject
Filter may help eliminate external filtering, thereby saving board space and component cost.
14
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9.4 Device Functional Modes
9.4.1 Summing Input Signals With the TPA2011D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2011D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
9.4.1.1 Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see Equation 1 and Equation 2, and Figure 30).
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(1)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(2)
ǒǓ
ǒǓ
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1
= 0.1 V/V. The resistor values would be:
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
Differential
Input 1
+
RI1
-
RI1
+
RI2
To Battery
Internal
Oscillator
Differential
Input 2
RI2
CS
IN_
-
VDD
PWM
HBridge
VO+
VO-
+
IN+
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 30. Application Schematic With TPA2011D1 Summing Two Differential Inputs
9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 5. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(3)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(4)
ǒǓ
ǒǓ
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Device Functional Modes (continued)
C
I2
+
1
ǒ2p RI2 f c2Ǔ
(5)
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set
to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
1
C u
I2
ǒ2p 150kW 20HzǓ
(6)
CI2 > 53 nF
(7)
RI1
Differential
Input 1
Single-Ended
Input 2
RI1
CI2 R
I2
To Battery
Internal
Oscillator
CS
IN_
RI2
VDD
PWM
HBridge
VO+
VO-
+
IN+
CI2
SHUTDOWN
GND
Bias
Circuitry
Filter-Free Class D
Figure 31. Application Schematic With TPA2011D1 Summing Differential Input and Single-Ended Input
Signals
9.4.1.3 Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 8 through Equation 11,
and Figure 32). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
V
Gain 1 + O + 2 x 150 kW
V
R
V
I1
I1
(8)
V
V
Gain 2 + O + 2 x 150 kW
V
R
V
I2
I2
(9)
1
C +
I1
2p R f
I1 c1
(10)
1
C +
I2
2p R f
I2 c2
(11)
C +C ) C
P
I1
I2
(12)
ǒǓ
ǒǓ
16
ǒ
Ǔ
ǒ
Ǔ
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Device Functional Modes (continued)
R
R +
P
I1
ǒRI1
R
) R
I2
Ǔ
I2
(13)
Single-Ended
Input 1
Single-Ended
Input 2
CI1 R
I1
To Battery
CI2 R
I2
Internal
Oscillator
CS
IN_
RP
VDD
PWM
HBridge
VO+
VO-
+
IN+
CP
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 32. Application Schematic With TPA2011D1 Summing Two Single-Ended Inputs
9.4.2 Shutdown Mode
The TPA2011D1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases. Each of these configurations can be realized using
the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the
most common modes of operation. Any design variation can be supported by TI through schematic and layout
reviews. Visit e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional
information.
10.2 Typical Applications
10.2.1 TPA2011D1 with Differential Input
To Battery
Internal
Oscillator
RI
+
Differential
Input
RI
EN
CS
IN−
_
−
VDD
PWM
VO+
H−
Bridge
VO−
+
IN+
GND
Bias
Circuitry
TPA2011D1
Filter-Free Class D
Figure 33. Typical TPA2011D1 Application Schematic with Differential Input
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXMAPLE VALUE
Power supply
5V
Enable input
High > 2 V
Low < 0.8 V
8Ω
Speaker
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to the following equation.
Gain =
2 ´ 150kW æ V ö
çV÷
RI
è ø
(14)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with
1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2011D1 to limit noise injection on the high-impedance nodes.
For optimal performance, the gain should be set to 2 V/V or lower. Lower gain allows the TPA2011D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
10.2.1.2.2 Decoupling Capacitor (CS)
The TPA2011D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
μF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to
the TPA2011D1 is very important for the efficiency of the class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lowerfrequency noise signals, a 10 μF or greater capacitor placed near the audio power amplifier would also help, but
it is not required in most applications because of the high PSRR of this device.
10.2.1.3 Application Curves
For application curves, see the figures listed in Table 2.
Table 2. Table of Graphs
DESCRIPTION
FIGURE NUMBER
Output Power vs Supply Resistance
Figure 11
GSM Power Supply Rejection vs Time
Figure 26
GSM Power Supply Rejection vs Frequency
Figure 27
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10.2.2 TPA2011D1 with Differential Input and Input Capacitors
To Battery
CI
Differential
Input
RI
Internal
Oscillator
CS
IN−
_
CI
VDD
PWM
VO+
H−
Bridge
VO −
+
RI
IN+
GND
EN
Bias
Circuitry
TPA2011D1
Filter-Free Class D
Figure 34. TPA2011D1 Application Schematic with Differential Input and Input Capacitors
10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
10.2.2.2 Detailed Design Procedure
For the design procedure see Input Resistors (RI) and Decoupling Capacitor (CS).
10.2.2.2.1 Input Capacitors (CI)
The TPA2011D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD –0.8 V. If the input signal is not biased within the recommended common mode input range, if
needing to use the input as a high pass filter, or if using a single-ended source, input coupling capacitors are
required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in the
following equation.
fC =
1
2pRICI
(15)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
The equation below is reconfigured to solve for the input coupling capacitance.
CI =
1
2pRIfC
(16)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 μF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
10.2.2.3 Application Curves
For application curves, see the figures listed in Table 2.
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10.2.3 TPA2011D1 with Single-Ended Input
CI
RI
Single-ended
Input
To Battery
Internal
Oscillator
VDD
IN−
_
RI
PWM
H−
Bridge
CS
VO+
VO−
+
IN+
CI
GND
Bias
Circuitry
EN
TPA2011D1
Filter-Free Class D
Figure 35. TPA2011D1 Application Schematic with Single-Ended Input
10.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 1.
10.2.3.2 Detailed Design Procedure
For the design procedure see Input Resistors (RI), Decoupling Capacitor (CS), and Input Capacitors (CI).
10.2.3.3 Application Curves
For application curves, see the figures listed in Table 2.
11 Power Supply Recommendations
The TPA2011D1 is designed to operate from an input voltage supply range between 2.5-V and 5.5-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA2011D1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, is recommended to place a 2.2 μF
to 10 μF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any drop in the supply voltage.
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12 Layout
12.1 Layout Guidelines
In making the pad size for the DSBGA balls, TI recommends that the layout use nonsolder mask defined (NSMD)
land. With this method, the solder mask opening is made larger than the desired land area, and the opening size
is defined by the copper pad width. Figure 36 shows the appropriate diameters for a DSBGA layout.
Place all the external components close to the TPA2011D1 device. Placing the decoupling capacitors as close as
possible to the device is important for the efficiency of the class-D amplifier. Any resistance or inductance in the
trace between the device and the capacitor can cause a loss in efficiency.
An on-pad via is not required to route the middle ball B2 (PVDD) of the TPA2011D1. Just short ball B2 (PVDD) to
ball B1 (VDD) and connect both to the supply trace as shown in Figure 37. This simplifies board routing and
saves manufacturing cost.
Copper
Trace Width
Solder Mask
Opening
Solder Mask
Thickness
Solder
Pad Width
Copper Trace
Thickness
Figure 36. Land Pattern Dimensions
Table 3. Land Pattern Dimensions (1) (2) (3) (4)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
22
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK
OPENING (5)
COPPER
THICKNESS
STENCIL OPENING (6) (7)
STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)
0.23 mm
0.310 mm
1 oz max
(0.032 mm)
0.275 mm x 0.275 mm Sq.
(rounded corners)
0.1 mm thick
Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
Recommend solder paste is Type 3 or Type 4.
For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils give inferior
solder paste volume control.
Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
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12.2 Layout Example
Input Resistors
placed as close as
possible to the device
OUT -
IN +
Decoupling capacitor
placed as close as
possible to the device
0.1µF
A1
A2
A3
B1
B2
B3
C1
C2
C3
TPA2011D1
IN -
OUT +
EN
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Via to Power Supply
Via to Bottom Layer Ground Plane
Figure 37. TPA2011D1 Layout Example
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
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15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA01086YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
OEW
HPA01203YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
OEW
TPA2011D1YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
OEW
TPA2011D1YFFT
ACTIVE
DSBGA
YFF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
OEW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA2011D1YFFR
DSBGA
YFF
9
3000
180.0
8.4
TPA2011D1YFFT
DSBGA
YFF
9
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.34
1.34
0.81
4.0
8.0
Q1
1.34
1.34
0.81
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2011D1YFFR
DSBGA
YFF
9
3000
210.0
185.0
35.0
TPA2011D1YFFT
DSBGA
YFF
9
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0009
DSBGA - 0.625 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.30
0.12
BALL TYP
0.05 C
0.8 TYP
C
0.8
TYP
SYMM
B
D: Max = 1.244 mm, Min =1.184 mm
0.4 TYP
E: Max = 1.19 mm, Min = 1.13 mm
A
9X
0.015
0.3
0.2
C A B
1
2
3
SYMM
0.4 TYP
4219552/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
9X ( 0.23)
1
2
3
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219552/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
9X ( 0.25)
1
2
3
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219552/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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