DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 DS89C387 Twelve Channel CMOS Differential Line Driver Check for Samples: DS89C387 FEATURES DESCRIPTION • • • The DS89C387 is a high speed twelve channel CMOS differential driver that meets the requirements of TIA/EIA-422-B. The DS89C387 features a low ICC specification of 1.5 mA maximum, which makes it ideal for battery powered and power conscious applications. The device replaces three DS34C87s and offers a PC board space savings up to 30%. The twelve channel driver is available in a SSOP package. The device is ideal for wide parallel bus applications. 1 2 • Low Power ICC: 1.5 mA Maximum Meets TIA/EIA-422-B (RS-422) Ensured AC Parameters: – Maximum Driver Skew −3 ns – Maximum Transition Time −10 ns Available in SSOP Packaging: – Requires 30% Less PCB Space than 3 DS34C87TMs Each TRI-STATE enable (EN) allows the driver outputs to be active or in a HI-impedance off state. Each enable is common to only two drivers for flexibility and control. The drivers may be disabled to turn off load current and to save power when data is not being transmitted. The driver's input (DI) is compatible with both TTL and CMOS signal levels. Connection Diagrams 1/6 of package Figure 2. Functional Diagram Truth Table Enable Input EN DI Outputs DO DO* Z L X Z H H H L H L L H Figure 1. 48-Pin SSOP Package See Package Number DL0048A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2013, Texas Instruments Incorporated DS89C387 SNLS101E – MAY 1995 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.5 to 7.0V Supply Voltage (VCC) −1.5 to VCC +1.5V DC Voltage (VIN) −0.5 to 7V DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±150 mA DC VCC or GND Current (ICC) ±500 mA −65°C to +150°C Storage Temperature Range (TSTG) Junction Temperature +150°C Maximum Power Dissipation (PD) @ 25°C (4) SSOP Package 1359 mW Thermal Resistance θJA 81.7°C/W θJC 31.7°C/W Lead Temperature (TL) (Soldering 4 sec.) 260°C This device does not meet 2000V ESD rating. (5) (1) Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Ratings apply to ambient temperature at 25°C. Above this temperature derate SSOP (MEA) Package 10.9 mW/°C. ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥ 1500V Outputs ≥ 1000V EIAJ (0Ω, 200 pF) All Pins ≥ 350V (2) (3) (4) (5) Operating Conditions Min Max Units 4.50 5.50 V 0 VCC V −40 +85 °C 500 ns Max Units 2.0 VCC V GND 0.8 V Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) DS89C387T Input Rise or Fall Times (tr, tf) DC Electrical Characteristics (1) (2) VCC = 5V ±10% (unless otherwise specified) Parameter VIH Test Conditions High Level Input Min Typ Voltage VIL Low Level Input Voltage VOH VOL (1) (2) 2 High Level Output VIN = VIH or VIL, Voltage IOUT = −20 mA Low Level Output VIN = VIH or VIL, Voltage IOUT = 48 mA 2.5 3.4 0.3 V 0.5 V Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative. Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and TA = 25°C. Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 DC Electrical Characteristics(1)(2) (continued) VCC = 5V ±10% (unless otherwise specified) Parameter VT |VT|–|VT| VOS |VOS–VOS| Test Conditions Differential Output RL = 100Ω Voltage See (3) Difference In RL = 100Ω Differential Output See (3) Common Mode RL = 100Ω Output Voltage See (3) Difference In RL = 100Ω See Input Current VIN = VCC, GND, VIH, or VIL ICC Quiescent Supply IOUT = 0 μA, Current VIN = VCC or GND IOFF 3.1 Units V 0.4 V 3.0 V 0.4 V 600 ±1.0 μA 1500 μA VIN = 2.4V or 0.5V (4) 0.8 2.0 mA TRI-STATE Output VOUT = VCC or GND ±0.5 ±5.0 μA Leakage Current Control = VIL Output Short VIN = VCC or GND −115 −150 mA Circuit Current See (3) and Power Off Output VCC = 0V VOUT = 6V 100 μA VOUT = −0.25V −100 μA Leakage Current (3) (4) (5) (6) 2.0 Max (3) Common Mode Output ISC Typ 2.0 IIN IOZ Min See (6) −30 (5) See TIA/EIA-422-B for exact test conditions. Measured per input. All other inputs at VCC or GND. This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted. See TIA/EIA-422-B for exact test conditions. Switching Characteristics (1) VCC = 5V ±10%, tr, tf ≤ 6 ns (Figure 3, Figure 4, Figure 5, and Figure 6) Parameter tPLH, tPHL Test Conditions Propagation Delay Min Typ Max Units S1 Open 2 6 11 ns 0 Input to Output Skew See (2) S1 Open 0.5 3 ns tTLH, tTHL Differential Output Rise S1 Open 6 10 ns And Fall Times tPZH Output Enable Time S1 Closed 12 25 ns tPZL Output Enable Time S1 Closed 13 26 ns tPHZ Output Disable Time (3) S1 Closed 4 8 ns tPLZ Output Disable Time (3) S1 Closed 6 12 CPD Power Dissipation ns 100 pF 6 pF Capacitance (4) CIN (1) (2) (3) (4) Input Capacitance Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and TA = 25°C. Skew is defined as the difference in propagation delays between complementary outputs at the crossing point. Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are less than indicated due to the delay added by the RC time constant of the load. CPD determines the no load dynamic power consumption, PD = CPD V2CC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 3 DS89C387 SNLS101E – MAY 1995 – REVISED APRIL 2013 www.ti.com Logic Diagram Parameter Measurement Information C1 = C2 = C3 = 40 pF (including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω Figure 3. AC Test Circuit 4 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 4. Propagation Delays Figure 5. Enable and Disable Times Input pulse; f = 1 MHz, 50%, tr ≤ 6 ns, tf ≤ 6 ns Figure 6. Differential Rise and Fall Times Typical Application * RT is optional although highly recommended to reduce reflection. Figure 7. Two-Wire Balanced System, RS-422 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 5 DS89C387 SNLS101E – MAY 1995 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION SKEW Skew may be thought of in a lot of different ways, the next few paragraphs should clarify what is represented by “Skew” in the datasheet and how it is determined. Skew, as used in this databook, is the absolute value of a mathematical difference between two propagation delays. This is commonly accepted throughout the semiconductor industry. However, there is no standardized method of measuring propagation delay, from which skew is calculated, of differential line drivers. Elucidating, the voltage level, at which propagation delays are measured, on both input and output waveforms are not always consistant. Therefore, skew calculated in this datasheet, may not be calculated the same as skew defined in another. This is important to remember whenever making a skew comparison. Skew may be calculated for the DS89C387, from many different propagation delay measurements. They may be classified into three categories, single-ended, differential, and complementry. Single-ended skew is calculated from tPHL and tPLH measurements (see Figure 9 and Figure 11). Differential skew is calculated from tPHLD and tPLHD measurements (see Figure 12 and Figure 13). Complementry skew is calculated from tPHL and tPLH measurements (see Figure 14 and Figure 15). Figure 8. (Circuit 1) – Circuits for Measuring Single-Ended Propagation Delays (See Figure 11) Figure 9. (Circuit 2) – Circuits for Measuring Single-Ended Propagation Delays (See Figure 11) Figure 10. Waveforms for Circuit 1 – Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 9) Figure 11. Waveforms for Circuit 2 – Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 9) 6 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 In Figure 4, VX, where X is a number, is the waveform voltage level at which the propagation delay measurement either starts or stops. Furthermore, V1 and V2 are normally identical. The same is true for V3 and V4. However, as mentioned before, these levels are not standardized and may vary, even with similar devices from other companies. Also note, NC (no connection) in Figure 3 means the pin is not used in propagation delay measurement for the corresponding circuit. The single-ended skew provides information about the pulse width distortion of the output waveform. The lower the skew, the less the output waveform will be distorted. For best case, skew would be zero, and the output duty cycle would be 50%, assuming the input has a 50% duty cycle. Figure 12. (Circuit 3) – Circuit for Measuring Differential Propagation Delays (See Figure 13) Figure 13. Waveforms for Circuit 3 – Propagation Delay Waveforms for Circuit 3 (See Figure 12) For differential propagation delays, V1 should equal V2. Furthermore, the crossing point of DO and DO* corresponds to zero volts on the differential waveform (see bottom waveform in Figure 13). This is true whether V3 equals V4 or not. However, if V3 and V4 are specified voltages, then V3 and V4 are less likely to be equal to the crossing point voltage. Thus, the differential propagation delays will not be measured to zero volts on the differential waveform. The differential skew also provides information about the pulse width distortion of the differential output waveform relative to the input waveform. The higher the skew, the greater the distortion of the differential output waveform. Assuming the input has a 50% duty cycle, the differential output will have a 50% duty cycle if skew equals zero and less than a 50% duty cycle if skew is greater than zero. Figure 14. (Circuit 4) – Circuit for Measuring Complementary Skew (See Figure 15) Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 7 DS89C387 SNLS101E – MAY 1995 – REVISED APRIL 2013 www.ti.com Figure 15. Waveforms for Circuit 4 – Waveforms for Circuit 4 (See Figure 14) Complementary skew is calculated from single-ended propagation delay measurements on complementary output signals, DO and DO*. Note, when V3 and V4 are absolute values, they are identical on DO and DO*; but vary whenever they are relative values. The complementary skew reveals information about the contour of the rising and falling edge of the differential output signal of the driver. This is important information because the receiver will interpret the differential output signal. If the differential transitions do not continuously ascend or decend through the receivers threshold region, errors may occur. Errors may also occur if the transitions are too slow. In addition, complementary skew provides information about the common mode modulation of the driver. The common mode voltage is represented by (DO–DO*)/2. This information may be used as a means for determining EMI affects. Only “Skew” is specified in this datasheet for the DS89C387. It refers to the complementary skew of the driver. Complementary skew is measured at both V3 and V4 (see Figure 15). More information can be calculated from the propagation delays. The channel to channel and device to device skew may be calculated in addition to the types of skew mentioned previously. These parameters provide timing performance information beneficial when designing. The channel to channel skew is calculated from the variation in propagation delay from receiver to receiver within one package. The device to device skew is calculated from the variation in propagation delay from one DS89C387 to another DS89C387. For the DS89C387, the maximum channel to channel skew is 9 ns (tp max–tp min) where tp is the low to high or high to low propagation delay. The minimum channel to channel skew is 0 ns since it is possible for all 12 drivers to have identical propagation delays. Note, this is best and worst case calculations used whenever Skew (channel) is not independently characterized and specified in the datasheet. The device to device skew may be calculated in the same way and the results are the same. Therefore, the device to device skew is 9 ns and 0 ns maximum and minimum respectively. Table 1. DS89C387 Skew Table Parameter Min Typ Max Units Skew (comp.) 0 0.5 3 ns Skew (channel) 0 9 ns Skew (device) 0 9 ns Note Skew (comp.) in Table 1 is the same as “Skew” in the datasheet. Also Skew (channel) and Skew (device) are calculations, but are specified by the propagation delay tests. Both Skew (channel) and Skew (device) would normally be tighter whenever specified from characterization data. The information in this section of the datasheet is to help clarity how skew is defined in this datasheet. This should help when designing the DS89C387 into most applications. 8 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 DS89C387 Equivalent Input/Output Circuits Figure 16. Driver Output Equivalent Circuit Figure 17. Driver Input or Driver Enable Equivalent Circuit Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 9 DS89C387 SNLS101E – MAY 1995 – REVISED APRIL 2013 www.ti.com Table 2. Pin Descriptions Pin No. Pin Name 7, 8, 15, 16, 22, 23, DI TTL/CMOS Compatible Driver Input Pin Description DO Non-Inverting Driver Output Pin DO* Inverting Driver Output Pin 4, 11, 19, 28, 35, 43 EN Active High Dual Driver Enabling Pin 38 VCC Positive Power Supply Pin +5 ±10% 14, 24 GND Device Ground Pin 1, 25, 48 NC 31, 32, 39, 40, 46, 47 2, 6, 9, 13, 17, 21, 26, 30, 33, 37, 41, 45 3, 5, 10, 12, 18, 20, 27, 29, 34, 36, 44, 44 10 Unused Pin (NOT CONNECTED) Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 DS89C387 www.ti.com SNLS101E – MAY 1995 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: DS89C387 11 PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS89C387TMEA NRND SSOP DL 48 29 TBD Call TI Call TI -40 to 85 DS89C387T MEA DS89C387TMEA/NOPB ACTIVE SSOP DL 48 29 Pb-Free (RoHS) CU SN | Call TI Level-2A-260C-4 WEEK -40 to 85 DS89C387T MEA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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