LTC2634 Quad 12-/10-/8-Bit Rail-to-Rail DACs with 10ppm/°C Reference FEATURES DESCRIPTION n The LTC®2634 is a family of quad 12-, 10- and 8-bit voltage output DACs with an integrated, high accuracy, low drift 10ppm/°C reference in 16-lead QFN and 10-lead MSOP packages. It has rail-to-rail output buffers and is guaranteed monotonic. The LTC2634-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2634-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to the external reference voltage. n n n n n n n n n n Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2634-L) 4.096V Full-Scale 10ppm/°C (LTC2634-H) Maximum INL Error: ±2.5 LSB (LTC2634-12) Low Noise: 0.75mVP-P 0.1Hz to 200KHz Guaranteed Monotonic over –40°C to 125°C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2634-L) Ultralow Crosstalk Between DACs (2.4nV•s) Low Power: 0.6mA at 3V Power-On Reset to Zero-Scale/Mid-Scale Double Buffered Data Latches Tiny 16-Lead 3mm × 3mm QFN and 10-Lead MSOP Packages These DACs communicate via an SPI/MICROWIRE compatible 3-wire serial interface which operates at clock rates up to 50MHz. Serial data output (SDO), a hardware clear (CLR), and an asynchronous DAC update (LDAC) capability are available in the QFN package. The LTC2634 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. APPLICATIONS n n n n n Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178, 7414561. BLOCK DIAGRAM INTERNAL REFERENCE GND SWITCH REF Integral Nonlinearity (LTC2634-LZ12) VREF VCC REGISTER REGISTER DAC A REGISTER 2 DAC D 1 VREF REGISTER REGISTER REGISTER DAC B REGISTER VREF VOUTB VCC = 3V INTERNAL REF VOUTD DAC C CS/LD INL (LSB) VOUTA REGISTER (REFLO) VOUTC SDI CONTROL LOGIC 0 –1 DECODE –2 SCK (LDAC) 32-BIT SHIFT REGISTER POWER-ON RESET (CLR) 0 1024 2048 3072 4095 CODE (SDO) 2634 TA01 2634 BD ( ) QFN PACKAGE ONLY 2634fb 1 LTC2634 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V CS/LD, SCK, SDI, LDAC, CLR, SDO, REFLO.. –0.3V to 6V VOUTA-VOUTD .................... –0.3V to Min (VCC + 0.3V, 6V) REF .................................. –0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2634C ................................................ 0°C to 70°C LTC2634I.............................................. –40°C to 85°C LTC2634H (Note 3) ............................ –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP ............................................................... 300°C GND DNC VCC TOP VIEW REFLO PIN CONFIGURATION 16 15 14 13 TOP VIEW VOUTA 1 12 VOUTD VOUTB 2 11 VOUTC 17 LDAC 3 10 REF CS/LD 4 6 7 8 SCK DNC SDO SDI 9 5 CLR UD PACKAGE 16-LEAD (3mm s 3mm) PLASTIC QFN VCC 1 VOUTA 2 VOUTB 3 CS/LD 4 SCK 5 11 10 9 8 7 6 GND VOUTD VOUTC REF SDI MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 35°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 68°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB 2634fb 2 LTC2634 ORDER INFORMATION LTC2634 C UD -L Z 12 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = 2,500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UD = 16-Lead QFN MSE = 10-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2634fb 3 LTC2634 PRODUCT SELECTION GUIDE PART MARKING* VFS WITH INTERNAL POWER-ON REFERENCE RESET TO CODE POWER-ON REFERENCE MODE PART NUMBER QFN MSOP RESOLUTION VCC MAXIMUM INL LTC2634-LMI12 LTC2634-LMI10 LTC2634-LMI8 LDQX LDRF LDRN LTDRV LTDSC LTDSK 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2634-LMX12 LTC2634-LMX10 LTC2634-LMX8 LDQW LDRD LDRM LTDRT LTDSB LTDSJ 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Mid-Scale Mid-Scale Mid-Scale External External External 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2634-LZ12 LTC2634-LZ10 LTC2634-LZ8 LDQV LDRC LDRK LTDRS LTDRZ LTDSH 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2634-HMI12 LTC2634-HMI10 LTC2634-HMI8 LDRB LDRJ LDRR LTDRY LTDSG LTDSP 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2634-HMX12 LTC2634-HMX10 LTC2634-HMX8 LDQZ LDRH LDRQ LTDRX LTDSF LTDSN 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) Mid-Scale Mid-Scale Mid-Scale External External External 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2634-HZ12 LTC2634-HZ10 LTC2634-HZ8 LDQY LDRG LDRP LTDRW 4.096V • (4095/4096) LTDSD 4.096V • (1023/1024) LTDSM 4.096V • (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V ±2.5LSB ±1LSB ±0.5LSB *Above options are available in a 16-lead QFN package (LTC2634-UD) or 10-lead MSOP package (LTC2634-MSE). 2634fb 4 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V) SYMBOL PARAMETER LTC2634-8 LTC2634-10 LTC2634-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX CONDITIONS UNITS DC Performance Resolution l 8 8 10 Monotonicity VCC = 3V, Internal Ref. (Note 4) l DNL Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4) l ±0.5 ±0.05 ±0.5 12 10 Bits 12 Bits ±0.5 ±1 LSB INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 4) l ±0.2 ±1 ±1 ±2.5 LSB ZSE Zero-Scale Error VCC = 3V, Internal Ref., Code = 0 l 0.5 5 0.5 5 0.5 5 mV VOS Offset Error VCC = 3V, Internal Ref. (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV VOSTC VOS Temperature Coefficient VCC = 3V, Internal Ref. l ±10 ±10 ±10 μV/°C ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR GE Gain Error VCC = 3V, Internal Ref. GETC Gain Temperature Coefficient VCC = 3V, Internal Ref. (Note 10) C-Grade I-Grade H-Grade Load Regulation Internal Ref., Mid-Scale VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA Internal Ref., Mid-Scale VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA Internal Ref., Mid-Scale VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω Internal Ref., Mid-Scale VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω ROUT DC Output Impedance 10 10 10 10 10 10 SYMBOL PARAMETER CONDITIONS MIN VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% ISC Short-Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l 10 10 10 TYP ppm/°C ppm/°C ppm/°C MAX UNITS 0 to VREF 0 to 2.5 V V –80 dB 27 –27 48 –48 mA mA Power Supply VCC Positive Supply Voltage For Specified Performance l 5.5 V ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference l l l l 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 mA mA mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l 0.5 0.5 20 30 μA μA 2.7 2634fb 5 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 160 200 kΩ 0.005 1.5 μA 1.25 1.26 Reference Input VREF Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 14 DAC Powered Down l pF Reference Output l Output Voltage 1.24 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 μF 2.5 mA Short-Circuit Current VCC = 5.5V, REF Shorted to GND VIH Digital Input High Voltage VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V l l VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V l l VOH Digital Output High Voltage Load Current = –100μA l VOL Digital Output Low Voltage Load Current = 100μA l ILK Digital Input Leakage VIN = GND to VCC CIN Digital Input Capacitance (Note 8) Digital I/O 2.4 2.0 V V 0.8 0.6 V V 0.4 V l ±1 μA l 2.5 pF VCC – 0.4 V AC Performance tS en Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.3 3.8 4.2 μs μs μs Voltage Output Slew Rate 1.0 V/μs Capacitive Load Driving 500 pF 2.1 nV•s Glitch Impulse At Mid-Scale Transition DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 – FS 2.1 nV•s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1μF 35 40 680 730 μVP-P μVP-P μVP-P μVP-P 2634fb 6 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8 (VFS = 2.5V) SYMBOL PARAMETER t1 SDI Valid to SCK Setup l 4 ns t2 SDI Valid to SCK Hold l 4 ns t3 SCK High Time l 9 ns t4 SCK Low Time l 9 ns t5 CS/LD Pulse Width l 10 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 ns t8 CLR Pulse Width l 20 ns t9 LDAC Pulse Width l 15 ns t10 CS/LD High to SCK Positive Edge l 7 SCK Frequency t11 CS/LD High to LDAC High or Low Transition t12 SDO Propagation Delay from SCK Falling Edge CONDITIONS 50% Duty Cycle MIN l l CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V l l TYP MAX UNITS ns 50 200 MHz ns 20 45 ns ns 2634fb 7 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER LTC2634-8 LTC2634-10 LTC2634-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX CONDITIONS UNITS DC Performance Resolution l 8 8 10 Monotonicity VCC = 5V, Internal Ref. (Note 4) l DNL Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4) l ±0.5 ±0.05 ±0.5 12 10 Bits 12 Bits ±0.5 ±1 LSB INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 4) l ±0.2 ±1 ±1 ±2.5 LSB ZSE Zero-Scale Error VCC = 5V, Internal Ref., Code = 0 l 0.5 5 0.5 5 0.5 5 mV VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV VOSTC VOS Temperature Coefficient VCC = 5V, Internal Ref. l ±10 ±10 ±10 μV/°C ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR GE Gain Error VCC = 5V, Internal Ref. GETC Gain Temperature Coefficient VCC = 5V, Internal Ref. (Note 10) C-Grade I-Grade H-Grade Load Regulation VCC = 5V ±10%, Internal Ref., Mid-Scale, –10mA ≤ IOUT ≤ 10mA l 0.006 0.01 0.022 0.04 0.09 0.16 LSB/mA VCC = 5V ±10%, Internal Ref., Mid-Scale, –10mA ≤ IOUT ≤ 10mA l 0.09 0.156 0.09 0.156 0.09 0.156 ROUT DC Output Impedance SYMBOL PARAMETER 10 10 10 10 10 10 CONDITIONS MIN VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 5V ±10% ISC Short-Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l 10 10 10 TYP ppm/°C ppm/°C ppm/°C MAX Ω UNITS 0 to VREF 0 to 4.096 V V –80 dB 27 –27 48 –48 mA mA 5.5 V Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 7) VCC = 5V, VREF = 4.096V, External Reference VCC = 5V, Internal Reference l l 0.6 0.7 0.8 0.9 mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l 0.5 0.5 20 30 μA μA 4.5 2634fb 8 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ 0.005 1.5 μA 2.048 2.064 Reference Input VREF Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 14 DAC Powered Down l pF Reference Output l Output Voltage 2.032 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 μF 4 mA Short-Circuit Current VCC = 5.5V, REF Shorted to GND Digital I/O l VIH Digital Input High Voltage VIL Digital Input Low Voltage VOH Digital Output High Voltage Load Current = –100μA l VOL Digital Output Low Voltage Load Current = 100μA l ILK Digital Input Leakage VIN = GND to VCC CIN Digital Input Capacitance (Note 8) 2.4 V l 0.8 VCC – 0.4 V V 0.4 V l ±1 μA l 2.5 pF AC Performance tS en Settling Time VCC = 5V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.8 4.2 4.8 μs μs μs Voltage Output Slew Rate 1.0 V/μs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3.0 nV•s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 – FS 2.4 nV•s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1μF 35 50 680 750 μVP-P μVP-P μVP-P μVP-P 2634fb 9 LTC2634 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2634-HMI12/-HMI10/-HMI8/-HMX12/-HMX10/-HMX8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t1 SDI Valid to SCK Setup l 4 ns t2 SDI Valid to SCK Hold l 4 ns t3 SCK High Time l 9 ns t4 SCK Low Time l 9 ns t5 CS/LD Pulse Width l 10 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 ns t8 CLR Pulse Width l 20 ns t9 LDAC Pulse Width l 15 ns t10 CS/LD High to SCK Positive Edge l 7 ns SCK Frequency t11 CS/LD High to LDAC High or Low Transition t12 SDO Propagation Delay from SCK Falling Edge l 50% Duty Cycle l CLOAD = 10pF VCC = 4.5V to 5.5V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. Note 4: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2634-12), code 4 (LTC2634-10) or code 1 (LTC2634-8), and at full-scale. l 50 200 MHz ns 20 ns Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 2634fb 10 LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2634-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 0 1024 2048 CODE –1.0 4095 3072 0 2048 CODE 1024 3072 2634 G01 INL vs Temperature Reference Output Voltage vs Temperature 1.0 0.5 DNL (LSB) INL (POS) 0 –0.5 1.255 DNL (POS) 0 DNL (NEG) –0.5 INL (NEG) 0 VCC = 3V VREF (V) 0.5 –1.0 –50 –25 1.260 VCC = 3V VCC = 3V INL (LSB) 2634 G02 DNL vs Temperature 1.0 25 50 75 100 125 150 TEMPERATURE (°C) 1.250 1.245 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G04 2634 G03 Settling to ±1LSB Rising 2634 G05 Settling to ±1LSB Falling CS/LD 5V/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 3.1μs VOUT 1LSB/DIV 4095 4.2μs 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS CS/LD 5V/DIV 2μs/DIV 2μs/DIV 2634 G06 2634 G07 2634fb 11 LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2634-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 5V VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 0 1024 2048 CODE 3072 –1.0 4095 0 1024 2048 CODE 3072 2634 G08 INL vs Temperature 2.068 VCC = 5V INL (POS) VCC = 5V 0.5 0 INL (NEG) –0.5 2.058 DNL (POS) VREF (V) 0.5 INL (LSB) Reference Output Voltage vs Temperature 1.0 VCC = 5V –1.0 –50 –25 2634 G09 DNL vs Temperature DNL (LSB) 1.0 0 DNL (NEG) –0.5 0 25 50 75 100 125 150 TEMPERATURE (°C) 2.048 2.038 –1.0 –50 –25 0 2.028 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G10 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G11 Settling to ±1LSB Rising 2634 G12 Settling to ±1LSB Falling CS/LD 5V/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 4.8μs 3.8μs VOUT 1LSB/DIV 4095 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS CS/LD 5V/DIV 2μs/DIV 2μs/DIV 2634 G13 2634 G14 2634fb 12 LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted LTC2634-10 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VFS = 2.5V INTERNAL REF VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 256 0 512 CODE 768 –1.0 1023 256 0 512 CODE 768 2634 G15 1023 2634 G16 LTC2634-8 Integral Nonlinearity (INL) 0.50 Differential Nonlinearity (DNL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.25 DNL (LSB) INL (LSB) 0.25 0 –0.25 –0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0 –0.25 0 64 128 CODE 192 –0.50 255 64 0 128 CODE 192 2634 G17 255 2634 G18 LTC2634 Load Regulation Current Limiting 6 VCC = 5V (LTC2634-H) VCC = 5V (LTC2634-L) VCC = 3V (LTC2634-L) 0.15 3 VCC = 5V (LTC2634-H) VCC = 5V (LTC2634-L) VCC = 3V (LTC2634-L) 2 0.10 OFFSET ERROR (mV) 8 Offset Error vs Temperature 0.20 10 2 $VOUT (V) $VOUT (mV) 4 0 –2 –4 0.05 0 –0.05 0 –1 –0.01 –6 INTERNAL REF. CODE = MID-SCALE –8 –10 –30 1 –20 –10 0 10 IOUT (mA) 20 30 2634 G19 –2 –0.15 –0.20 –30 INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2634 G20 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G21 2634fb 13 LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted LTC2634 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2634-L CS/LD 5V/DIV VOUT 0.5V/DIV VCC 2V/DIV LTC2634-H12, VCC = 5V 3.0nV•s TYP ZERO SCALE VOUT 5mV/DIV VOUT 5mV/DIV LTC2634-L12, VCC = 3V 2.1nV•s TYP VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2μs/DIV 2μs/DIV 2634 G22 Headroom at Rails vs Output Current VCC = 5V INTERNAL REF 4.0 3.5 VOUT (V) Power-On Reset to Mid-Scale LTC2634-H 5V SOURCING VCC 2V/DIV CS/LD 2V/DIV 3V (LTC2634-L) SOURCING 3.0 2636 G24 Exiting Power-Down to Mid-Scale 5.0 4.5 200μs/DIV 2634 G23 LTC2634-H 2.5 2.0 VOUT 0.5V/DIV 1.5 5V SINKING 1.0 LTC2634-L VOUT 0.5V/DIV 3V (LTC2634-L) SINKING 0.5 0 DACs A-C IN POWER-DOWN MODE 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 5μs/DIV 10 200μs/DIV 2634 G26 2634 G27 2634 G25 Hardware CLR Supply Current vs Logic Voltage 1.4 SWEEP SCK, SDI, CS/LD BETWEEN 0V AND VCC Hardware CLR to Mid-Scale VCC = 5V VREF = 4.096V CODE = FULL-SCALE 1.2 VOUT 1V/DIV VCC = 5V VREF = 4.096V CODE = FULL-SCALE ICC (mA) VOUT 1V/DIV 1.0 VCC = 5V 0.8 VCC = 3V (LTC2634-L) 0.6 0.4 0 1 3 2 LOGIC VOLTAGE (V) CLR 5V/DIV CLR 5V/DIV 4 5 1μs/DIV 1μs/DIV 2634 G29 2634 G30 2634 G28 2634fb 14 LTC2634 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted LTC2634 Noise Voltage vs Frequency 500 0 NOISE VOLTAGE (nV/√Hz) –2 –4 dB –6 –8 –10 –12 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE –14 –16 –18 1k 10k 100k FREQUENCY (Hz) 400 Gain Error vs Reference Input 1.0 VCC = 5V CODE = MID-SCALE INTERNAL REF VCC = 5.5V 0.8 GAIN ERROR OF 4 CHANNELS 0.6 GAIN ERROR (%FSR) Mulitplying Bandwidth 2 300 LTC2634-H 200 LTC2634-L 0.4 0.2 0 –0.2 –0.4 –0.6 100 –0.8 1M 0 100 –1.0 1k 10k 100k FREQUENCY (Hz) 2636 G31 1M 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5.5 2634 G33 2636 G32 0.1Hz to 10Hz Voltage Noise 5 DAC-to-DAC Crosstalk (Dynamic) Gain Error vs Temperature 1.0 VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF GAIN ERROR (%FSR) CS/LD 5V/DIV 1 DAC SWITCH 0-FS 2V/DIV 10μV/DIV VOUT 1mV/DIV 1s/DIV 0 –0.5 LTC2634-H12, VCC = 5V 2.4nV•s TYP CREF = 0.1μF 2μs/DIV 2634 G34 0.5 2634 G35 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G36 2634fb 15 LTC2634 PIN FUNCTIONS (QFN/MSOP) VOUTA to VOUTD (Pins 1-2, 11-12/Pins 2-3, 8-9): DAC Analog Voltage Outputs. LDAC (Pin 3, QFN Only): Asynchronous DAC Update Pin. If CS/LD is high, a falling edge on LDAC immediately updates the DAC registers with the contents of the input registers (similar to a software update). If CS/LD is low when LDAC goes low, the DAC registers are updated after CS/LD returns high. A low on the LDAC pin powers up the DACs. A software power-down command is ignored if LDAC is low. CS/LD (Pin 4/Pin 4): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the 32-bit shift register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 5/Pin 5): Serial Interface Clock Input. CMOS and TTL compatible. DNC (Pins 6, 15, QFN Only): Do not connect these pins. SDO (Pin 7, QFN Only): Serial Interface Data Output. The serial output of the 32-bit shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation, it is always driven and never goes high impedance, even when CS/LD is high. See the Daisy-Chain Operation section. SDI (Pin 8/Pin 6): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2634 accepts input word lengths of either 24 or 32 bits. CLR (Pin 9, QFN Only): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage output to reset to zero (LTC2634-Z) or mid-scale (LTC2634-MI/-MX). CMOS and TTL compatible. REF (Pin 10/Pin 7): Reference Voltage Input or Output. When external reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When internal reference is selected, the 10ppm/°C 1.25V (LTC2634-L) or 2.048V (LTC2634-H) internal reference (half full-scale) is available at REF. This output may be bypassed to GND with up to 10μF and must be buffered when driving external DC load current. REFLO (Pin 13, QFN only): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin must be tied to GND. GND (Pin 14/Pin 10): Ground. VCC (Pin 16/Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2634-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2634-H). Bypass to GND with a 0.1μF capacitor. Exposed Pad (Pin 17/Pin 11): Ground. Must be soldered to PCB ground. 2634fb 16 LTC2634 BLOCK DIAGRAM INTERNAL REFERENCE GND SWITCH REF VREF VCC REGISTER REGISTER DAC A REGISTER VOUTA REGISTER (REFLO) DAC D VREF REGISTER REGISTER REGISTER DAC B REGISTER VREF VOUTB VOUTD DAC C CS/LD SDI CONTROL LOGIC SCK (LDAC) VOUTC DECODE 32-BIT SHIFT REGISTER POWER-ON RESET (CLR) (SDO) 2634 BD ( ) QFN PACKAGE ONLY 2634fb 17 LTC2634 TIMING DIAGRAMS t1 t2 SCK t3 1 t6 t4 2 3 23 24 t10 SDI t5 t7 CS/LD t12 SDO t11 t9 LDAC 2634 F01a Figure 1a CS/LD t11 LDAC 2634 F01b Figure 1b 2634fb 18 LTC2634 OPERATION The LTC2634 is a family of quad voltage output DACs in 16-lead QFN and 10-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10- and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and fullscale voltage (2.5V or 4.096V) are available. The LTC2634 is controlled using a 3-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2634-HZ/LTC2634-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2634 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2634-HMI/LTC2634-HMX/LTC2634-LMI/ LTC2634-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2634-LMI and LTC2634-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2634-LMX and LTC2634-HMX power up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 10, QFN/Pin 7, MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is: ⎛ k ⎞ VOUT(IDEAL) = ⎜ N ⎟ ( VREF – VREFLO ) + VREFLO ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2634-LMI/LTC2634-LMX/LTC2634-LZ) or 4.096V (LTC2634-HMI/LTC2634-HMX/LTC2634-HZ) when in internal reference mode, and the voltage at REF when in external reference mode. The resulting DAC output span is 0V to VREF , as it is necessary to tie REFLO to GND. Serial Interface The CS/LD input is level-triggered. When this input is taken low, it acts as a chip-select signal, enabling the SDI and SCK buffers and the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 12-, 10- or 8-bit input code, ordered MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2634-12/LTC2634-10/LTC2634-8 respectively; see Figure 2). Data can only be transferred to the device when the CS/LD signal is low, beginning on the first rising edge of SCK. SCK may be high or low at the falling edge 2634fb 19 LTC2634 OPERATION of CS/LD. The rising edge of CS/LD ends the data transfer and causes the device to execute the command specified in the 24-bit input sequence. The complete sequence is shown in Figure 3a. The command (C3-C0) and address (A3-A0) assignments are shown in Tables 1 and 2. The first four commands in Table 1 consist of write and update operation. A write operation loads a 16-bit data word from the 24-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10- or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and update combines the first two commands. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Input Word (LTC2634-12) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (12 BITS + 4 DON’T CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 X X X X X X X X X X X LSB Input Word (LTC2634-10) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (10 BITS + 6 DON’T CARE BITS) A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB Input Word (LTC2634-8) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (8 BITS + 8 DON’T CARE BITS) A0 D7 D6 D5 D4 D3 D2 D1 MSB D0 X X X X X 2634 F02 LSB Figure 2. Command and Data Input Format Table 1. Command Codes Table 2. Address Codes COMMAND* ADDRESS (n)* C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 Write to Input Register n 0 0 0 0 DAC A 0 0 0 1 Update (Power Up) DAC Register n 0 0 0 1 DAC B 0 0 1 0 Write to Input Register n, Update (Power Up) All 0 0 1 0 DAC C 0 0 1 1 Write to and Update (Power Up) DAC Register n 0 0 1 1 DAC D 0 1 0 0 Power-Down DAC n 1 1 1 1 All DACs 0 1 0 1 Power-Down Chip (All DACs and Reference) 0 1 1 0 Select Internal Reference (Power-Up Reference) 0 1 1 1 Select External Reference (Power-Down Internal Reference) 1 1 1 1 No Operation * Address codes not shown are reserved and should not be used. *Command codes not shown are reserved and should not be used. 2634fb 20 LTC2634 OPERATION While the minimum input sequence is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). To use the 32-bit width, 8 don’t care bits must be transferred to the device first, followed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence. The 16-bit data word is ignored for all commands that do not include a write operation. Daisy-Chain Operation (QFN Package) The serial output of the shift register appears at the SDO pin on the QFN package. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge, therefore, daisy chaining multiple LTC2634 DACs requires 32-bit data write cycles. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a “daisy-chain” series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. Figure 5 shows a block diagram for daisy-chain operation. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2634 has a low noise, user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2634-LMI/LTC2634-LMX/LTC2634-LZ provides a full-scale DAC output of 2.5V. The LTC2634HMI/LTC2634-HMX/LTC2634-HZ provides a full-scale DAC output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2634-HZ/LTC2634-LZ, as well as for LTC2634-HMI/ LTC2634-LMI. The 10ppm/°C, 1.25V (LTC2634-LMI/LTC2634-LMX/ LTC2634-LZ) or 2.048V (LTC2634-HMI/LTC2634-HMX/ LTC2634-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; 0.1μF is recommended, and up to 10μF can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in external reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External reference mode is the power-on default for LTC2634-HMX/LTC2634-LMX. The reference mode of LTC2634-HZ/LTC2634-LZ/ LTC2634-HMI/LTC2634-LMI (internal reference power-on default), can be changed by software command after power up. The same is true for LTC2634-HMX/-LMX (external reference power-on default). The LTC2634’s QFN package offers a REFLO pin for the negative reference. REFLO must be connected to GND. 2634fb 21 LTC2634 OPERATION Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 200k resistors. Input- and DAC-register contents are not disturbed during power down. Any DAC channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 20% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into powerdown mode using power-down chip command 0101b. When the integrated reference and all DAC channels are in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1) or pulling the asynchronous LDAC pin low. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 10μs. However, if all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power-up delay time is 12μs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). However, if the reference was powered down using power-down chip command (0101b), then in addition to select internal reference command (0110b), any command (in software or using the LDAC pin) that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2634’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph “Headroom at Rails vs Output Current” in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. 2634fb 22 LTC2634 OPERATION Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2634 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2634 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2634 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. 2634fb 23 24 X X SDI SDO SCK CS/LD 1 X X 2 X X 3 X 4 X X DON’T CARE X 5 C3 SDI C2 2 C1 3 X X 6 X X 7 4 7 A1 ADDRESS A2 6 A0 8 D11 9 D10 10 D9 D8 12 D7 13 D6 14 24-BIT INPUT WORD 11 D5 15 D3 17 DATA WORD D4 16 D2 18 D1 C3 C3 C2 10 C1 11 C2 C1 COMMAND WORD 9 C0 C0 A3 A3 A2 14 A1 15 A2 A1 ADDRESS WORD 13 A0 A0 16 17 D11 D11 PREVIOUS 32-BIT INPUT WORD 12 D10 D10 18 t2 t4 t12 D5 D5 23 PREVIOUS D11 t3 17 D6 D6 22 SDO t1 D7 D7 21 D11 D8 D8 20 SDI SCK D9 D9 19 D3 25 X 21 D10 D4 18 D3 DATA WORD D4 24 D0 20 PREVIOUS D10 19 Figure 3a. LTC2634-12 24-Bit Load Sequence (Minimum Input Word) LTC2634-10 SDI Data Word: 10-Bit Input Code + 6 Don’t Care Bits LTC2634-8 SDI Data Word: 8-Bit Input Code + 8 Don’t Care Bits A3 5 D2 D2 26 X 22 D1 D1 27 X 23 D0 D0 28 X 24 X X 29 2634 F03a X X 30 X X 31 X X 2634 F03b CURRENT 32-BIT INPUT WORD 32 OPERATION Figure 3b. LTC2634-12 32-Bit Load Sequence (Required for Daisy-Chain Operation) LTC2634-10 SDI Data Word: 10-Bit Input Code + 6 Don’t Care Bits LTC2634-8 SDI Data Word: 8-Bit Input Code + 8 Don’t Care Bits X 8 C0 X COMMAND WORD 1 SCK CS/LD LTC2634 2634fb LTC2634 OPERATION POSITIVE FSE VREF = VCC VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE 2634 F04 (4c) OUTPUT VOLTAGE 0V 0 2,048 INPUT CODE 4,095 (4a) 0V NEGATIVE OFFSET INPUT CODE (4b) Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown in 12 Bits) (4a) Overall Transfer Function (4b) Effect of Negative Offset for Codes Near Zero (4c) Effect of Postitive Full-Scale Error for Codes Near Full-Scale SCK CS/LD SDI 4 CS/LD 5 SCK 6 SDI LTC2634UD SDO 7 4 CS/LD 5 SCK 6 SDI 4 CS/LD 5 SCK 6 SDI LTC2634UD SDO 7 LTC2634UD SDO 7 DATA OUTPUT • • • 2634 F05 Figure 5. Daisy-Chain Operation (QFN Only) 2634fb 25 0.1μF 7 0.1μF + 30k –15V – OUTC –15V 4 1/2 LT1469 8 6 5 + – 0.1μF 5V VDD 62 REFA DAC C DAC D 63 RCOM1 64 RIN1 61 ROFSA 15 RFBA 60 GND 19 RVOSA 58 IOUT2A 2 IOUT1A 59 DAC B DAC A LTC2755 + – 15V 8 15V 30k OUTB –15V 4 1/2 LT1469 –15V 3 2 + 26 – 0.1μF OUTA 30k SERIAL BUS –15V 0.1μF 1 0.1μF 6 5 4 3 2 7 SDI SCK CS/LD REF DAC B DAC A DAC C DAC D LTC2634MSE-LMI12 GND VCC 10 8 9 1 LTC2634 DACs Adjusts LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 2634 TA02 0.1μF 5V 1k 2k 15V –15V 0.1μF 0.1μF 8 7 M9 9 M3 VCC 10 M1 6 OUT LT1991 1 REF P1 2 P3 VEE 5 3 4 P9 0.1μF VOUT ±5V LTC2634 TYPICAL APPLICATION 2634fb LTC2634 PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 p0.05 3.50 p 0.05 1.45 p 0.05 2.10 p 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 p0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 s 45o CHAMFER R = 0.115 TYP 0.75 p 0.05 15 PIN 1 TOP MARK (NOTE 6) 16 0.40 p 0.10 1 1.45 p 0.10 (4-SIDES) 2 (UD16) QFN 0904 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 p 0.05 0.50 BSC 2634fb 27 LTC2634 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 p 0.102 (.110 p .004) 5.23 (.206) MIN 0.889 p 0.127 (.035 p .005) 1 0.05 REF 10 3.00 p 0.102 (.118 p .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 10 9 8 7 6 DETAIL “A” 0o – 6o TYP 1 2 3 4 5 GAUGE PLANE 0.53 p 0.152 (.021 p .006) DETAIL “A” 0.18 (.007) 0.497 p 0.076 (.0196 p .003) REF 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) 0.254 (.010) 0.29 REF 1.83 p 0.102 (.072 p .004) 2.083 p 0.102 3.20 – 3.45 (.082 p .004) (.126 – .136) 0.50 0.305 p 0.038 (.0197) (.0120 p .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 2.06 p 0.102 (.081 p .004) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 p 0.0508 (.004 p .002) MSOP (MSE) 0908 REV C 2634fb 28 LTC2634 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/09 Changes to Electrical Characteristics Maximum Limits B 12/09 Change Pin Name to DNC 5, 6, 8, 9 2, 16 2634fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LTC2634 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1663 Single 10-Bit VOUT DAC in SOT-23 VCC = 2.7V to 5.5V, 60μA, Internal Reference, SMBus Interface LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1669 Single 10-Bit VOUT DAC in SOT-23 VCC = 2.7V to 5.5V, 60μA, Internal reference, I2C Interface LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step LTC2600/LTC2610/ LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2601/LTC2611/ LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2602/LTC2612/ LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2604/LTC2614/ LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2605/LTC2615/ LTC2625 Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface LTC2606/LTC2616/ LTC2626 Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface LTC2609/LTC2619/ LTC2629 Quad 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC LTC2630 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in SC70 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SPI Serial Interface LTC2631 Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference in ThinSOT™ 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, I2C Interface LTC2636 Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface LTC2640 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in ThinSOT 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface ThinSOT is a trademark of Linear Technology Corporation 2634fb 30 Linear Technology Corporation LT 1209 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009