OKI MSM514800C 524,288-word x 8-bit dynamic ram : fast page mode type Datasheet

E2G0024-17-42
¡ Semiconductor
MSM514800C/CSL
¡ Semiconductor
This MSM514800C/CSL
version: Jan. 1998
Previous version: May 1997
524,288-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514800C/CSL is a 524,288-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514800C/CSL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM514800C/CSL is available in a 28-pin plastic SOJ or 28pin plastic TSOP. The MSM514800CSL (the self-refresh version) is specially designed for lowerpower applications.
FEATURES
• 524,288-word ¥ 8-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• CAS before RAS self-refresh capability (SL version)
• Package options:
28-pin 400 mil plastic SOJ
(SOJ28-P-400-1.27)
(Product : MSM514800C/CSL-xxJS)
28-pin 400 mil plastic TSOP
(TSOPII28-P-400-1.27-K)
(Product : MSM514800C/CSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
Power Dissipation
Cycle Time
(Min.)
Operating (Max.) Standby (Max.)
MSM514800C/CSL-60
60 ns 30 ns 20 ns 20 ns
110 ns
660 mW
MSM514800C/CSL-70
70 ns 35 ns 20 ns 20 ns
130 ns
605 mW
MSM514800C/CSL-80
80 ns 40 ns 20 ns 20 ns
150 ns
550 mW
5.5 mW/
1.1 mW (SL version)
1/16
¡ Semiconductor
MSM514800C/CSL
PIN CONFIGURATION (TOP VIEW)
VCC 1
28 VSS
VCC 1
28 VSS
DQ1 2
27 DQ8
DQ1 2
27 DQ8
DQ2 3
26 DQ7
DQ2 3
26 DQ7
DQ3 4
25 DQ6
DQ3 4
25 DQ6
DQ4 5
24 DQ5
DQ4 5
24 DQ5
NC 6
23 CAS
NC 6
23 CAS
WE 7
22 OE
WE 7
22 OE
RAS 8
21 NC
RAS 8
21 NC
A9R 9
20 A8
A9R 9
20 A8
A0 10
19 A7
A0 10
19 A7
A1 11
18 A6
A1 11
18 A6
A2 12
17 A5
A2 12
17 A5
A3 13
16 A4
A3 13
16 A4
VCC 14
15 VSS
VCC 14
15 VSS
28-Pin Plastic SOJ
28-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A8, A9R
Function
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 - DQ8
Data Input / Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
Note: The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/16
¡ Semiconductor
MSM514800C/CSL
BLOCK DIAGRAM
RAS
Timing
Generator
Timing
Generator
CAS
9
Column
Address
Buffers
9
Write
Clock
Generator
Column
Decoders
WE
OE
8
Internal
Address
Counter
A0 - A8
Refresh
Control Clock
Sense
Amplifiers
8
I/O
Selector
A9R
1
Row
Address
Buffers
10
Row
Decoders
Word
Drivers
8
8
8
8
9
Output
Buffers
Input
Buffers
DQ1 - DQ8
8
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/16
¡ Semiconductor
MSM514800C/CSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A8, A9R)
CIN1
—
7
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 - DQ8)
CI/O
—
8
pF
4/16
¡ Semiconductor
MSM514800C/CSL
DC Characteristics
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
MSM514800 MSM514800 MSM514800
C/CSL-70
C/CSL-60
C/CSL-80 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
120
—
110
—
100
mA 1, 2
—
2
—
2
—
2
—
1
—
1
—
1
—
200
—
200
—
—
120
—
110
—
5
—
—
120
—
0 V £ VI £ 6.5 V;
Input Leakage Current
ILI
All other pins not
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
DQ disable
0 V £ VO £ 5.5 V
RAS, CAS cycling,
tRC = Min.
RAS, CAS = VIH
Power Supply
Current (Standby)
ICC2 RAS, CAS
≥ VCC –0.2 V
1
200
mA
1, 5
—
100
mA 1, 2
5
—
5
—
110
—
100
mA 1, 2
110
—
100
—
90
mA 1, 3
—
300
—
300
—
300
mA
—
300
—
300
—
300
mA
RAS cycling,
Average Power
Supply Current
mA
ICC3 CAS = VIH,
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5 CAS = VIL,
ICC6
(CAS before RAS Refresh)
RAS cycling,
CAS before RAS
RAS = VIL,
Average Power
Supply Current
ICC7 CAS cycling,
(Fast Page Mode)
tPC = Min.
Average Power
tRC = 125 ms,
Supply Current
1
DQ = enable
Average Power
Supply Current
mA
ICC10 CAS before RAS,
tRAS £ 1 ms
(Battery Backup)
1, 4,
5
Average Power
Supply Current
(CAS before RAS
ICCS
RAS £ 0.2 V,
CAS £ 0.2 V
1, 5
Self-Refresh)
Notes:
1.
2.
3.
4.
5.
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
SL version.
5/16
¡ Semiconductor
MSM514800C/CSL
AC Characteristics (1/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Symbol
MSM514800 MSM514800 MSM514800
C/CSL-70
C/CSL-60
C/CSL-80 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
—
tRWC
110
155
—
—
—
—
40
—
—
—
150
205
tPC
130
185
45
50
—
ns
ns
tPRWC
85
—
100
—
105
—
ns
Access Time from RAS
tRAC
—
60
—
70
—
80
ns
4, 5, 6
Access Time from CAS
tCAC
—
20
—
20
—
20
ns
4, 5
Access Time from Column Address
Access Time from CAS Precharge
tAA
tCPA
—
—
30
35
—
—
35
40
—
—
40
45
ns
ns
4, 6
4
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
20
—
—
0
20
—
—
0
20
—
ns
ns
4
4
CAS to Data Output Buffer Turn-off Delay Time
OE to Data Output Buffer Turn-off Delay Time
Transition Time
Refresh Period
Refresh Period (SL version)
tOFF
tOEZ
tT
tREF
tREF
0
0
3
—
—
15
15
50
16
128
0
0
3
—
—
20
20
50
16
128
0
0
3
—
—
20
20
50
16
128
ns
ns
ns
ms
ms
7
7
3
RAS Precharge Time
tRP
40
—
50
—
60
—
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100,000
70
100,000
80
100,000
ns
RAS Hold Time
RAS Hold Time referenced to OE
tRSH
tROH
15
15
—
—
20
20
—
—
20
20
—
—
ns
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
20
10,000
20
10,000
20
10,000
ns
CAS Hold Time
tCSH
CAS to RAS Precharge Time
tCRP
60
10
—
—
70
10
—
—
80
10
—
—
ns
ns
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
tRHCP
tRCD
tRAD
—
40
30
40
20
15
—
50
35
45
20
15
—
60
40
ns
ns
RAS to Column Address Delay Time
35
20
15
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
10
—
15
—
15
—
ns
tAR
tRAL
50
—
55
—
60
—
ns
30
—
35
—
40
—
ns
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
8
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
8
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
tRC
ns
ns
11
5
6
6/16
¡ Semiconductor
MSM514800C/CSL
AC Characteristics (2/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Symbol
MSM514800 MSM514800 MSM514800
C/CSL-60
C/CSL-70
C/CSL-80 Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
Write Command Hold Time
tWCH
15
—
15
—
15
—
ns
Write Command Hold Time from RAS
tWCR
50
—
55
—
60
—
ns
Write Command Pulse Width
tWP
15
—
15
—
15
—
ns
OE Command Hold Time
tOEH
15
—
20
—
20
—
ns
Write Command to RAS Lead Time
tRWL
15
—
20
—
20
—
ns
Write Command to CAS Lead Time
tCWL
15
—
20
—
20
—
ns
Data-in Set-up Time
tDS
0
—
0
—
0
—
ns
10
Data-in Hold Time
tDH
15
—
15
—
15
—
ns
10
Data-in Hold Time from RAS
tDHR
50
—
55
—
60
—
ns
OE to Data-in Delay Time
tOED
15
—
20
—
20
—
ns
CAS to WE Delay Time
tCWD
40
—
50
—
50
—
ns
9
Column Address to WE Delay Time
tAWD
60
—
65
—
70
—
ns
9
RAS to WE Delay Time
tRWD
90
—
100
—
110
—
ns
9
CAS Precharge WE Delay Time
tCPWD
65
—
70
—
75
—
ns
9
CAS Active Delay Time from RAS Precharge
tRPC
10
—
10
—
10
—
ns
RAS to CAS Set-up Time (CAS before RAS)
tCSR
10
—
10
—
10
—
ns
RAS to CAS Hold Time (CAS before RAS)
tCHR
15
—
15
—
15
—
ns
RAS Pulse Width
(CAS before RAS Self-Refresh)
tRASS
100
—
100
—
100
—
ms
11
RAS Precharge Time
(CAS before RAS Self-Refresh)
tRPS
110
—
130
—
150
—
ns
11
CAS Hold Time
(CAS before RAS Self-Refresh)
tCHS
–40
—
–50
—
–60
—
ns
11
9
7/16
¡ Semiconductor
Notes:
MSM514800C/CSL
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. Only SL version.
8/16
E2G0096-17-41I
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,,
,
,,,,
¡ Semiconductor
MSM514800C/CSL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
VIH –
VIL –
tRSH
tCAS
tRAD
tASR
Address
tCRP
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
VIH –
VIL –
tAA
tROH
tOEA
VIH –
OE
VIL –
tCAC
tRAC
DQ
tRCH
tRRH
VOH –
tOEZ
Open
VOL –
tOFF
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
VIH –
CAS
VIL –
WE
VIH –
VIL –
tCSH
tRCD
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
tWCH
VIH –
tRWL
VIH –
VIL –
tDS
DQ
tCWL
tWP
VIL –
tWCR
OE
tRAL
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
9/16
,
,,
¡ Semiconductor
MSM514800C/CSL
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH –
VIL –
tRP
tAR
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
10/16
,,,
,
,,,
¡ Semiconductor
MSM514800C/CSL
Fast Page Mode Read Cycle
tRASP
VIH –
RAS V –
IL
VIH –
CAS
VIL –
Address
WE
VIH –
VIL –
tRP
tAR
tCRP
tRHCP
tPC
tRCD
tCP
tASR
tCP
tCAS
tCAS
tRAD
tRAH tASC
tCSH
tCAH
tASC
Column
Row
VIH –
VIL –
tCAC
VOH –
DQ
VOL –
Column
tRCS
tRCH
tRRH
tCPA
tOEA
tOFF
tOEZ
tRCH
tAA
tAA
tCAC
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
tCLZ
tRCS
tCPA
tOEA
tRAC
tRAL
tCAH
tASC
Column
tAA
VIH –
OE
VIL –
tCAS
tCAH
tRCH
tRCS
tCRP
tRSH
tCLZ
tOFF
tOEZ
Valid
Data-out
Valid
Data-out
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tAR
VIH –
RAS V –
IL
tCRP
VIH –
CAS
VIL –
Address
VIH –
VIL –
tRAH tASC
Row
tWCS
tDS
VIH –
VIL –
tCSH
tCAH
Column
tCWL
tWCH
tWP
tRAD
tRHCP
tRSH
tRCD
VIH –
WE
VIL –
DQ
tPC
tCAS
tASR
tRP
tWCR
tDH
Valid Data-in
tDHR
tCP
tCRP
tCP
tCAS
tASC
tCAH
tASC
Column
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
tCAS
tCAH
tRAL
Column
tRWL
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
Note: OE = "H" or "L"
"H" or "L"
11/16
¡ Semiconductor
MSM514800C/CSL
,,,,
,,
,
Fast Page Mode Read Modify Write Cycle
tRASP
VIH –
RAS
VIL –
tAR
tRP
tCSH
tPRWC
tRCD
VIH –
CAS
VIL –
tASC
tCAH
tRAH
VIH –
VIL –
tCRP
tCAS
tASC
tCAH
tCAH
Column
Column
tASC
Column
Row
tRCS
tCPWD
tCWD
tRWD
tCWD
tRCS
V
WE IH –
VIL –
tCWL
tAWD
tCWL
tWP
tDH
VI/OH–
VI/OL –
Out
tCLZ
tOEA
tOED
tOEZ
tCAC
In
tDH
tDS
tOEA
tOEZ
tCAC
tWP
tCPA
tAA
tOED
VIH –
OE V –
IL
tCWL
tROH
tWP
tDH
tDS
tOEA
tRWL
tAWD
tCPA
tAA
tAA
tRAL
tRCS
tCPWD
tCWD
tAWD
tDS
tRAC
DQ
tCP
tCAS
tRAD
tASR
Address
tCP
tCAS
tRSH
Out
tOED
In
tCLZ
tOEZ
tCAC
Out
In
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
RAS
VIL –
CAS
Address
VIH –
VIL –
VIH –
VIL –
tRP
tRAS
VIH –
tCRP
tASR
tRPC
tRAH
Row
tOFF
DQ
VOH –
VOL –
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/16
,,
,
,,
¡ Semiconductor
MSM514800C/CSL
CAS before RAS Refresh Cycle
tRC
tRP
RAS
VIH –
VIL –
DQ
tRP
tRPC
tRPC
tCSR
tCP
CAS
tRAS
VIH –
VIL –
tCHR
tOFF
VOH –
VOL –
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRAS
RAS
VIH –
tRP
tAR
VIH –
VIL –
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
tRAH
tASR
Address
tRAS
tRP
VIL –
tCRP
CAS
tRC
Row
tCHR
tCAH
Column
tRCS
tRAL
VIH –
WE V
IL –
tRRH
tAA
tROH
tOEA
VIH –
OE V
IL –
tRAC
DQ
VOH –
VOL –
tCAC
tCLZ
tOFF
tOEZ
Valid Data-out
"H" or "L"
13/16
¡ Semiconductor
MSM514800C/CSL
,,,
,
Hidden Refresh Write Cycle
tRC
tRAS
VIH –
RAS
VIL –
CAS
tRP
tAR
tCRP
tRCD
VIH –
VIL –
tCAH
tRAH
Row
tWCS
V
WE IH –
VIL –
tCHR
tRSH
tRAD
tASC
tASR
Address VIH –
VIL –
tRC
tRAS
tRP
tRAL
Column
tRWL
tWCH
tWP
tWCR
VIH –
OE
VIL –
tDS
DQ VIH –
VIL –
tDH
Valid Data-in
tDHR
"H" or "L"
CAS before RAS Self-Refresh Cycle
tRASS
tRP
RAS
VIH –
VIL –
tRPC
tCP
CAS
tRPS
tRPC
tCSR
tCHS
VIH –
VIL –
tOFF
DQ VOH –
VOL –
Open
Note: WE, OE, Address = "H" or "L"
Only SL version
"H" or "L"
14/16
¡ Semiconductor
MSM514800C/CSL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ28-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.30 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/16
¡ Semiconductor
MSM514800C/CSL
(Unit : mm)
TSOPII28-P-400-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.51 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/16
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