Single-chip Type with Built-in FET Switching Regulator Series Low Noise High Efficiency Step-down Switching Regulator with Built-in Power MOSFET No.09027EAT22 BD8961NV ●Description ROHM’s high efficiency step-down switching regulator BD8961NV is a power supply designed to produce a low voltage including 3.3 volts from 5 volts power supply line. Offers high efficiency with synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) 3) Incorporates soft-start function. 4) Incorporates thermal protection and ULVO functions. 5) Incorporates short-current protection circuit with time delay function. 6) Incorporates shutdown function 7) Employs small surface mount package : SON008V5060 ●Use Power supply for LSI including DSP, Micro computer and ASIC ●Line up Parameter Symbol VCC -0.3～+7 PVCC -0.3～+7 ＊1 EN Voltage SW,ITH Voltage Unit ＊1 VCC Voltage PVCC Voltage Limits V V VEN -0.3～+7 V VSW,VITH -0.3～+7 V Pd1 900＊2 mW Power Dissipation 1 ＊3 Power Dissipation 2 Pd2 Operating temperature range Topr -25～+105 ℃ Tstg -55～+150 ℃ Tjmax +150 ℃ Storage temperature range Maximum junction temperature ＊1 ＊2 ＊3 3900 mW Pd should not be exceeded. Derating in done 7.2mW/℃ for temperatures above Ta=25℃, Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB (the density of copper:3%) Derating in done 31.2mW/℃ for temperatures above Ta=25℃, Mounted on JESD51-7. ●Operating Conditions (Ta=25℃) Parameter Symbol Limits Min. Typ. Max. Unit VCC Voltage VCC *4 4.5 5.0 5.5 V PVCC Voltage PVCC *4 4.5 5.0 5.5 V VEN 0 - VCC V Isw *4 - - 2.0 A EN Voltage SW average output current ＊4 Pd should not be exceeded. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/13 2009.05 - Rev.A Technical Note BD8961NV ●Electrical Characteristics ◎(Ta=25℃, VCC=PVCC=3.3V, EN=VCC.) Parameter Symbol Standby current Bias current EN Low voltage EN High voltage EN input current Oscillation frequency Pch FET ON resistance Nch FET ON resistance Output voltage ITH SInk current ITH Source Current UVLO threshold voltage UVLO release voltage Soft start time Timer latch time Output Short circuit Threshold Voltage ISTB ICC VENL VENH IEN FOSC RONP RONN VOUT ITHSI ITHSO VUVLO1 VUVLO2 TSS TLATCH VSCP Limits Typ. 0 250 GND VCC 1 1 200 150 3.300 20 20 3.8 3.90 1 2 1.65 Min. 2.0 0.8 3.250 10 10 3.6 3.65 0.5 1 - Unit Max. 10 450 0.8 10 1.2 320 270 3.350 4.0 4.2 2 3 2.31 μA μA V V μA MHz mΩ mΩ V μA μA V V ms ms VOUT Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V VOUT=3.6V VOUT=3.0V VCC=5→0V VCC=0→5V SCP/TSD operated VOUT=3.3→0V ●Block Diagram, Application Circuit VCC EN D8961 8 2 VREF Input Lot No. Current Comp R Q SLOPE Gm Amp. OSC Current Sense/ Protect S + CLK Driver Logic 7 PVCC Output 6 SW VCC UVLO Soft Start TSD SCP 1 3 VOUT 5 PGND 4 GND ITH RITH Fig.1 BD8961NV TOP View ●Pin No. & function table Pin No. 1 2 3 4 5 6 7 8 VCC CITH Fig.2 BD8961NV Block Diagram Pin name VOUT VCC ITH GND PGND SW PVCC EN www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. PIN function Output voltage pin VCC power supply input pin GmAmp output pin/Connected phase compensation capacitor Ground Nch FET source pin Pch/Nch FET drain output pin Pch FET source pin Enable pin (Active High) 2/13 2009.05 - Rev.A Technical Note BD8961NV ●Characteristics data (Reference data) 2.0 OUTPUT VOLTAGE:VOUT[V] 4.0 OUTPUT VOLTAGE:VOUT[V] Ta=25℃ Io=2A 4.5 3.5 3.0 2.5 2.0 1.5 1.0 5.0 1.5 1.0 VCC=5V Ta=25℃ Io=0A 0.5 0.5 0.0 0.0 0 1 2 3 4 INPUT VOLTAGE:VCC[V] 0 5 1 Fig.3 Vcc-Vout VCC=5V Io=0A 3.32 3.31 3.30 3.29 3.28 0 1.15 70 60 50 40 30 10 VCC=5V Ta=25℃ 50 75 100 1000 OUTPUT CURRENT:IOUT[mA] Fig. 6 Ta-VOUT 1.05 1.00 0.95 0.90 10000 -25 400 CIRCUIT CURRENT:I CC [μA] 1.6 EN VOLTAGE:VEN[V] PMOS 0.20 0.15 NMOS 1.4 1.2 1.0 0.8 0.6 0.4 0.05 25 50 75 TEMPERATURE:Ta[℃] 100 Fig.9 Ta-RONN, RONP www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 75 100 75 100 VCC=5V 350 300 250 200 150 100 0 0.0 0 50 50 0.2 0.00 25 Fig.8 Ta-FOSC VCC=5V 1.8 0.30 -25 0 TEMPERATURE:Ta[℃] 2.0 VCC=5V 0.10 VCC=5V 1.10 Fig.7 Efficiency 0.40 5 0.80 10 100 TEMPERATURE:Ta[℃] 0.25 2 3 4 OUTPUT CURRENT:IOUT [A] 0.85 0 0.35 1 Fig.5 Iout-Vout 1.20 3.26 25 VCC=5V Ta=25℃ 1.0 90 20 0 2.0 100 3.27 -25 3.0 0.0 5 80 3.25 ON [Ω] 4 FREQUENCY:FOSC[MHz] 3.33 EFFICIENCY:η[%] OUTPUT VOLTAGE:VOUT[V] 3.34 2 3 EN VOLTAGE:VEN[V] 4.0 Fig.4 Ven-Vout 3.35 ON RESISTANCE:R OUTPUT VOLTAGE:VOUT[V] 5.0 -25 0 25 50 75 TEMPERATURE:Ta[℃] Fig.10 Ta-VEN 3/13 100 -25 0 25 50 TEMPERATURE:Ta[℃] Fig.11 Ta-ICC 2009.05 - Rev.A Technical Note BD8961NV 1.2 FREQUENCY:FOSC[MHz] Ta=25℃ SW VCC=PVCC =EN 1.1 1msec 1 VOUT VOUT 0.9 VCC=5V Ta=25℃ Io=0A 0.8 2.7 3.1 3.5 3.9 4.3 4.7 INPUT VOLTAGE:VCC [V] 5.1 VCC=5V Ta=25℃ 5.5 Fig.13 Soft start waveform Fig.12 Vcc-Fosc VOUT VOUT Fig.14 SW waveform Io=10mA 110mV 100mV IOUT IOUT VCC=5V Ta=25℃ Fig. 16 Transient response Io=1A→2A(10μs) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. VCC=5V Ta=25℃ Fig.17 Transient response Io=2A→1A(10μs) 4/13 2009.05 - Rev.A Technical Note BD8961NV ●Information on advantages Advantage 1：Offers fast transient response with current mode control system. Conventional product (Load response IO=0.1A→0.6A) BD8961NV (Load response IO=1A→2A) VOUT VOUT 100mV 160mV IOUT IOUT Voltage drop due to sudden change in load was reduced by about 50%. Fig.18 Comparison of transient response Advantage 2： Offers high efficiency with synchronous rectifier ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. 100 90 EFFICIENCY:η[%] 80 ON resistance of P-channel MOS FET : 200mΩ(Typ.) ON resistance of N-channel MOS FET : 160mΩ(Typ.) 70 60 50 40 30 VCC=5V 20 10 0 10 100 1000 10000 OUTPUT CURRENT:IOUT[mA] Fig.19 Efficiency Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated. ・Output capacitor Co required for current mode control: 22μF ceramic capacitor ・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor Reduces a mounting area required. VCC 15mm Cin CIN RITH DC/DC Convertor Controller L RITH L VOUT 10mm CITH Co CO CITH Fig.20 Example application www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/13 2009.05 - Rev.A Technical Note BD8961NV ●Operation BD8961NV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. SENSE Current Comp RESET VOUT Level Shift R Q FB SET Gm Amp. ITH S IL Driver Logic VOUT SW Load OSC Fig.21 Diagram of current mode PWM control PVCC Current Comp SENSE FB SET GND RESET GND SW GND IL IL(AVE) VOUT VOUT(AVE) Fig.22 PWM switching timing chart www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/13 2009.05 - Rev.A Technical Note BD8961NV ●Description of operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 100mV (Typ.) is provided to prevent output chattering. Hysteresis 100mV VCC EN VOUT Tss Tss Tss Soft start Standby mode Operating mode Standby mode Standby mode Operating mode UVLO UVLO Operating mode Standby mode EN UVLO Fig.23 Soft start, Shutdown, UVLO timing chart ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. EN Output OFF latch Output Short circuit Threshold Voltage VOUT IL Limit IL t1<TLATCH Standby mode t2=TLATCH Operating mode Standby mode Timer latch EN Operating mode EN Fig.24 Short-current protection circuit with time delay timing chart www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/13 2009.05 - Rev.A Technical Note BD8961NV ●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: POUT η= VOUT×IOUT ×100[%]= POUT ×100[%]= Vin×Iin Pin POUT+PDα ×100[%] Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FET：PD(I R) 2) Gate charge/discharge dissipation：PD(Gate) 3) Switching dissipation：PD(SW) 4) ESR dissipation of capacitor：PD(ESR) 5) Operating current dissipation of IC：PD(IC) 2 2 1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.) 2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[Hz]：Switching frequency, V[V]：Gate driving voltage of FET) 2 Vin ×CRSS×IOUT×f (CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.) 3)PD(SW)= IDRIVE 2 4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.) 5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.) ●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. ①3.9W Power dissipation:Pd [W] 4.0 ①for SON008V5060 JEDEC 4 layer board 76.2×114.3×1.6mm θj-a=32.1℃/W ②for SON008V5060 ROHM standard 1 layer board 70×70×1.6mm θj-a=138.9℃/W ③ IC only θj-a=195.3℃/W 3.0 P=IOUT2×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RCOIL：DC resistance of coil RONP：ON resistance of P-channel MOS FET RONN：ON resistance of N-channel MOS FET IOUT：Output current 2.0 1.0 ②0.90W ③0.64W 0 0 25 50 75 100105 125 150 Ambient temperature:Ta [℃] Fig.25 Thermal derating curve (SON008V5060) If VCC=5V, VOUT=3.3V, RONP=0.2Ω, RONN=0.16Ω IOUT=2A, for example, D=VOUT/VCC=3.3/5.0=0.66 RON=0.66×0.20+(1-0.66)×0.16 =0.132+0.0544 =0.1864[Ω] P=22×0.1864＝0.7456W] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/13 2009.05 - Rev.A Technical Note BD8961NV ●Selection of components externally connected 1. Selection of inductor (L) IL The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. ΔIL VCC ΔIL= IL (VCC-VOUT)×VOUT L×VCC×f [A]・・・(1) Appropriate ripple current at output should be 20% more or less of the maximum output current. VOUT L ΔIL=0.3×IOUTmax. [A]・・・(2) Co L= Fig.26 Output ripple current (VCC-VOUT)×VOUT ΔIL×VCC×f [H]・・・(3) (ΔIL: Output ripple current, and f: Switching frequency) * Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×2A=0.6A, for example,(BD8961NV) L= (5.0-3.3)×3.3 0.6×5.0×1M =1.87μ → 2.2[μH] *Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) VCC Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)： VOUT L ESR ΔVOUT=ΔIL×ESR [V]・・・(4) Co (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) *Rating of the capacitor should be determined allowing sufficient margin against output voltage. Less ESR allows reduction in output ripple voltage. 22µF to 100µF ceramic capacitor is recommended. Fig.27 Output capacitor 3. Selection of input capacitor (Cin) VCC Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. ripple current IRMS is given by the equation (5): Cin VOUT L Co IRMS=IOUT× √VOUT(VCC-VOUT) VCC The [A]・・・(5) < Worst case > IRMS(max.) When Vcc is twice the VOUT, IRMS= Fig.28 Input capacitor IOUT 2 If VCC=5.0V, VOUT=3.3V, and IOUTmax.=2A, (BD8961NV) IRMS=2× √3.3(5.0-3.3) 5.0 =0.947[ARMS] A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/13 2009.05 - Rev.A Technical Note BD8961NV 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) 1 2π×RO×CO 1 fz(ESR)= 2π×ESR×CO A fp= fp(Max.) Gain [dB] 0 fz(ESR) IOUTMin. Phase [deg] IOUTMax. Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. 0 -90 fp(Min.)= 1 2π×ROMax.×CO [Hz]←with lighter load fp(Max.)= 1 2π×ROMin.×CO [Hz] ←with heavier load Fig.29 Open loop gain characteristics A fz(Amp.) Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) Gain [dB] 0 0 Phase [deg] -90 fz(Amp.)= 1 2π×RITH×CITH Fig.30 Error amp phase compensation characteristics Cin VCC EN VOUT L VCC,PVCC SW ESR VOUT ITH VOUT GND,PGND RO CO RITH CITH Fig.31 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. = 1 2π×ROMax.×CO 10/13 2009.05 - Rev.A Technical Note BD8961NV ●BD8961NV Cautions on PC Board layout VCC 1 2 3 RITH ③ CITH 4 VOUT EN VCC PVCC ITH SW GND PGND 8 EN 7 L 6 ① VOUT CIN ② 5 Co GND Fig.32 Layout diagram ① ② ③ ※ For the sections drawn with heavy line, use thick conductor pattern as short as possible. Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring. SON008V5060 (BD8961NV) has thermal FIN on the reverse of the package. The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of PCB. ●Recommended components Lists on above application Symbol L CIN CO CITH RITH Part Coil Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistance Value 2.2uH 22uF 22uF 680pF 12kΩ Manufacturer TDK Kyocera Kyocera murata Rohm Series LTF5022-2R2N3R2 CM32X5R226M10A CM316B226M06A MCH03Serise *The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins. ●I/O equivalence circuit ・EN pin PVCC ・SW pin PVCC PVCC EN SW ・ITH pin ・VOUT pin VCC VCC 10kΩ ITH VOUT Fig.33 I/O equivalence circuit www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/13 2009.05 - Rev.A Technical Note BD8961NV ●Notes of use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4.Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 34. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A Pin B C Pin B B E Pin A N P+ N P+ P N Parasitic element N P + P substrate Parasitic element GND B N P+ P N C E Parasitic element P substrate Parasitic element GND GND GND Other adjacent elements Fig.34 Simplified structure of monorisic IC 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 9 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/13 2009.05 - Rev.A Technical Note BD8961NV ●Ordering part number B D 8 Part No. 9 6 1 N Part No. V - E 2 Package Packaging and forming specification NV : SON008V5060 E2: Embossed tape and reel SON008V5060 <Tape and Reel information> 6.0 ± 0.15 5.0±0.15 4.2±0.1 1.27 2 3 4 0.59 8 7 5 2000pcs Direction of feed S E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 3.6 ± 0.1 1 0.8 ± 0.1 C0.25 Embossed carrier tape Quantity (0.22) 0.08 S +0.03 0.02 -0.02 1.0MAX 1PIN MARK Tape 6 +0.05 0.4 -0.04 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 13/13 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A