M29F800AT M29F800AB 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory PRELIMINARY DATA ■ SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 70ns ■ PROGRAMMING TIME – 8µs per Byte/Word typical ■ 44 19 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 16 Main Blocks ■ PROGRAM/ERASE CONTROLLER – Embedded Byte/Word Program algorithm 1 TSOP48 (N) 12 x 20mm SO44 (M) – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin ■ ERASE SUSPEND and RESUME MODES Figure 1. Logic Diagram – Read and Program another Block during Erase Suspend ■ TEMPORARY BLOCK UNPROTECTION MODE ■ LOW POWER CONSUMPTION VCC 19 – Standby and Automatic Standby ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK ■ 20 YEARS DATA RETENTION ■ 15 A0-A18 DQ0-DQ14 W – Defectivity below 1 ppm/year E ELECTRONIC SIGNATURE G – Manufacturer Code: 0020h RP DQ15A–1 M29F800AT M29F800AB BYTE RB – M29F800AT Device Code: 00ECh – M29F800AB Device Code: 0058h VSS AI02198B January 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/21 M29F800AT, M29F800AB Figure 2A. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 12 13 Figure 2B. SO Connections 48 M29F800AT M29F800AB 24 37 36 25 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29F800AT 34 12 M29F800AB 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC AI02101B AI02199 Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply Voltage VSS Ground NC Not Connected Internally 2/21 SUMMARY DESCRIPTION The M29F800A is an 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. M29F800AT, M29F800AB Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to 6 V VCC Supply Voltage –0.6 to 6 V VID Identification Voltage –0.6 to 13.5 V TA Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm) and SO44 packages. Access times of 70ns and 90ns are available. The memory is supplied with all the bits erased (set to ’1’). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, V IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 3/21 M29F800AT, M29F800AB Table 3A. M29F800AT Block Addresses Table 3B. M29F800AB Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16) Size (Kbytes) Address Range (x8) Address Range (x16) 16 FC000h-FFFFFh 7E000h-7FFFFh 64 F0000h-FFFFFh 78000h-7FFFFh 8 FA000h-FBFFFh 7D000h-7DFFFh 64 E0000h-EFFFFh 70000h-77FFFh 8 F8000h-F9FFFh 7C000h-7CFFFh 64 D0000h-DFFFF h 68000h-6FFFFh 32 F0000h-F7FFFh 78000h-7BFFFh 64 C0000h-CFFFF h 60000h-67FFFh 64 E0000h-EFFFF h 70000h-77FFFh 64 B0000h-BFFFFh 58000h-5FFFFh 64 D0000h-DFFFFh 68000h-6FFFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 B0000h-BFFFF h 58000h-5FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 A0000h-AFFFF h 50000h-57FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 80000h-8FFFFh 40000h-47FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 60000h-6FFFFh 30000h-37FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 40000h-4FFFFh 20000h-27FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 30000h-3FFFFh 18000h-1FFFFh 32 08000h-0FFFFh 04000h-07FFFh 64 20000h-2FFFFh 10000h-17FFFh 8 06000h-07FFFh 03000h-03FFFh 64 10000h-1FFFFh 08000h-0FFFFh 8 04000h-05FFFh 02000h-02FFFh 64 00000h-0FFFFh 00000h-07FFFh 16 00000h-03FFFh 00000h-01FFFh Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at V ID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. 4/21 The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteristics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. M29F800AT, M29F800AB Table 4A. Bus Operations, BYTE = VIL Operation E G Address Inputs DQ15A–1, A0-A18 W Data Inputs/Outpu ts DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL V IH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input X VIH V IH X Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z ECh (M29F800AT) 58h (M29F800AB) Output Disable Note: X = VIL or VIH. Table 4B. Bus Operations, BYTE = VIH Operation Address Inputs A0-A18 Data Inputs/Outpu ts DQ15A–1, DQ14-DQ0 E G W Bus Read VIL VIL V IH Cell Address Bus Write VIL VIH VIL Command Address X VIH V IH X Hi-Z Standby V IH X X X Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL V IH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 00ECh (M29F800AT) 0058h (M29F800AB) Output Disable Data Output Data Input Note: X = VIL or VIH. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4. VSS Ground. The VSS Ground is the reference for all voltage measurements. BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad5/21 M29F800AT, M29F800AB dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level. When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, I CC2. To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4A and 4B, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Block Unprotection operations must only be performed on programming equipment. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash. 6/21 COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. In this case, after at least 50ns, an address transition or Chip Enable going Low is required before reading correct data. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5A, or 5B, depending on the configuration that is being used, for a summary of the commands. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F800AT is 00ECh and for the M29F800AB is 0058h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to either V IL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- M29F800AT, M29F800AB Command Length Table 5A. Commands, 16-bit mode, BYTE = VIH Bus Write Operations 1st Addr 2nd Data 3rd 4th Addr Data Addr Data 5th Addr Data 6th Addr Data Addr Data 1 X F0 3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read/Reset Table 5B. Commands, 8-bit mode, BYTE = VIL Length Bus Write Operations Addr Data 1 X F0 3 AAA Auto Select 3 Program Command 1st 2nd 3rd 4th Addr Data Addr Data AA 555 55 X F0 AAA AA 555 55 AAA 90 4 AAA AA 555 55 AAA Chip Erase 6 AAA AA 555 55 Block Erase 6+ AAA AA 555 55 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read/Reset 5th Addr Data A0 PA PD AAA 80 AAA AAA 80 AAA 6th Addr Data Addr Data AA 555 55 AAA 10 AA 555 55 BA 30 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout Bit is set. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. quires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 7/21 M29F800AT, M29F800AB Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) Typ (1) Typical after 100k W/E Cycles (1) Chip Erase (All bits in the memory set to ‘0’) 3 3 Chip Erase 8 8 30 sec Block Erase (64 Kbytes) 0.6 0.6 4 sec Program (Byte or Word) 8 8 150 µs Chip Program (Byte by Byte) 9 9 35 sec 4.5 4.5 18 sec Parameter Min Chip Program (Word by Word) Program/Erase Cycles (per Block) 100,000 Max Unit sec cycles Note: 1. TA = 25°C, VCC = 5V. Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase 8/21 Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. M29F800AT, M29F800AB Table 7. Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Any Address DQ7 Toggle 0 – – 0 Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 1 Toggle 1 Block Erase Erase Suspend Non-Erasing Block Data read as normal 1 Good Block Address 0 Toggle 1 1 No Toggle 0 Faulty Block Address 0 Toggle 1 1 Toggle 0 Erase Error Note: Unspecified data bits should be ignored. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Sus- pend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 3, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. 9/21 M29F800AT, M29F800AB Figure 3. Data Polling Flowchart Figure 4. Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 DQ7 = DATA DQ6 = TOGGLE YES NO NO YES NO DQ5 =1 YES READ DQ7 READ DQ6 DQ6 = TOGGLE YES NO FAIL NO YES PASS AI01369 Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 4, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Pro- 10/21 DQ5 =1 YES DQ7 = DATA NO FAIL PASS AI01370 gram, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. M29F800AT, M29F800AB Table 8. AC Measurement Conditions M29F800A Parameter 70 90 High Speed Standard 30pF 100pF Input Rise and Fall Times ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0.45 to 2.4V 1.5V 0.8V and 2.0V AC Test Conditions Load Capacitance (CL) Input and Output Timing Ref. Voltages Figure 5. AC Testing Input Output Waveform Figure 6. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL = 30pF or 100pF 2.0V 0.8V 0.45V AI01275B CL includes JIG capacitance AI03027 Table 9. Capacitance (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit V IN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. 11/21 M29F800AT, M29F800AB Table 10. DC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) ICC2 Supply Current (Standby) TTL ICC3 Supply Current (Standby) CMOS E = VCC ± 0.2V, RP = VCC ± 0.2V ICC4 (1) Supply Current (Program/Erase) Program/Erase Controller active Min Typ. (2) Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ V CC ±1 µA 20 mA 1 mA 150 µA 20 mA E = V IL, G = VIH, f = 6MHz 10 E = VIH 35 VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.45 V Output High Voltage TTL IOH = –2.5mA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.4 V VOH VID Identification Voltage IID Identification Current VLKO (1) IOL = 5.8mA 11.5 A9 = VID Program/Erase Lockout Supply Voltage 3.2 12.5 V 100 µA 4.2 V Note: 1. Sampled only, not 100% tested. 2. TA = 25 °C, VCC = 5V. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the 12/21 blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. M29F800AT, M29F800AB Table 11. Read AC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) M29F800A Symbol Alt Parameter Test Condition Unit 70 90 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 70 90 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 70 90 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 20 20 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 20 20 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns tELBL tELBH tELFL tELFH Chip Enable to BYTE Low or High Max 5 5 ns tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 20 20 ns tBHQV t FHQV BYTE High to Output Valid Max 30 40 ns Note: 1. Sampled only, not 100% tested. Figure 7. Read Mode AC Waveforms tAVAV A0-A18/ A–1 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGHQZ tGLQV DQ0-DQ7/ DQ8-DQ15 VALID tBHQV BYTE tELBL/tELBH tBLQZ AI02981 13/21 M29F800AT, M29F800AB Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F800A Symbol Alt Parameter Unit 70 90 tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH t WP Write Enable Low to Write Enable High Min 45 45 ns tDVWH tDS Input Valid to Write Enable High Min 30 45 ns t WHDX tDH Write Enable High to Input Transition Min 0 0 ns t WHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns Output Enable High to Write Enable Low Min 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 8. Write AC Waveforms, Write Enable Controlled tAVAV A0-A18/ A–1 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL 14/21 AI02183 M29F800AT, M29F800AB Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F800A Symbol Alt Parameter Unit 70 90 tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns tWLEL t WS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns tDVEH tDS Input Valid to Chip Enable High Min 30 45 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns t EHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns Output Enable High Chip Enable Low Min 0 0 ns tGHEL tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A18/ A–1 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL AI02184 15/21 M29F800AT, M29F800AB Table 14. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) M29F800A Symbol tPHWL (1) tPHEL Alt Parameter Unit 70 90 tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 ns tPLPX tRP RP Pulse Width Min 500 500 ns tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns (1) tPHGL tRHWL (1) tRHEL (1) tRHGL (1) Note: 1. Sampled only, not 100% tested. Figure 10. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931 16/21 M29F800AT, M29F800AB Table 15. Ordering Information Scheme Example: M29F800AB 70 N 1 T Device Type M29 Operating Voltage F = VCC = 5V ± 10% Device Function 800A = 8Mbit (1Mb x8 or 512Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 90 = 90 ns Package N = TSOP48: 12 x 20 mm M = SO44 Temperature Range 1 = 0 to 70 °C 3 = –40 to 125 °C 6 = –40 to 85 °C Optio n T = Tape & Reel Packing Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 17/21 M29F800AT, M29F800AB Table 16. Revision History Date Revision Details July 1999 First Issue 09/21/99 Removed 55ns speed option ICC1 Typ. specification added (Table 10) ICC3 Typ. specification added (Table 10) 10/04/99 ICC3 Test Condition change (Table 10) 11/12/99 Block Protection and Unprotection paragraph changed 01/14/00 Command Interface paragraph changed 18/21 M29F800AT, M29F800AB Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data mm inches Symbol Typ Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 11.90 12.10 0.469 0.476 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 48 e 0.50 0.020 48 CP 0.10 0.004 Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 19/21 M29F800AT, M29F800AB Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data mm inches Symbol Typ Min Max A 2.42 A1 A2 Min Max 2.62 0.095 0.103 0.22 0.23 0.009 0.010 2.25 2.35 0.089 0.093 B Typ 0.50 0.020 C 0.10 0.25 0.004 0.010 D 28.10 28.30 1.106 1.114 E 13.20 13.40 0.520 0.528 – – – – 15.90 16.10 0.626 0.634 e 1.27 H 0.050 L 0.80 – – 0.031 – – α 3° – – 3° – – N 44 CP 44 0.10 0.004 Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A2 A C B CP e D N E H 1 A1 SO-b Drawing is not to scale. 20/21 α L M29F800AT, M29F800AB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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