Revised August 2000 DM93L38 8-Bit Multiple Port Register General Description Features The DM93L38 is an 8-bit multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable. A common use would be as a register bank in a three address computer. Data can be written into any one of the eight bits and read from any two of the eight bits simultaneously. The circuit uses TTL technology and is compatible with all TTL families. ■ Master/slave operation permitting simultaneous write/ read without race problems ■ Simultaneously read two bits and write one bit in any one of eight bit positions ■ Readily expandable to allow for larger word sizes Ordering Code: Order Number Package Number DM93L38N N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names Description A0–A2 Write Address Inputs DA Data Input B0–B2 B Read Address Inputs C0–C2 C Read Address Inputs CP Clock Pulse Input (Active Rising Edge) SLE Slave Enable Input (Active LOW) ZB B Output ZC C Output © 2000 Fairchild Semiconductor Corporation DS010202 www.fairchildsemi.com DM93L38 8-Bit Multiple Port Register March 1989 DM93L38 Functional Description The DM93L38 8-bit multiple port register can be considered a 1-bit slice of eight high speed working registers. Data can be written into any one and read from any two of the eight locations simultaneously. Master/slave operation eliminates all race problems associated with simultaneous read/write activity from the same location. When the clock input (CP) is LOW data applied to the data input line (DA) enters the selected master. This selection is accomplished by coding the three write input select lines (A0–A2) appropriately. Data is stored synchronously with the rising edge of the clock pulse. The signals are available on the output pins (ZB and ZC). The input bit selection and the two output bit selections can be accomplished independently or simultaneously. The data flows into the device, is demultiplexed according to the state of the write address lines and is clocked into the selected latch. The eight latches function as masters and store the input data. The two output latches are slaves and hold the data during the read operation. The state of each slave is determined by the state of the master selected by its associated set of read address inputs. The method of parallel expansion is shown in Figure 1. One DM93L38 is needed for each bit of the required word length. The read and write input lines should be connected in common on all of the devices. This register configuration provides two words of n-bits each at one time, where n devices are connected in parallel. The information for each of the two slaved (output) latches is selected by two sets of read address inputs (B0–B2 and C0–C2). The information enters the slave while the clock is HIGH and is stored while the clock is LOW. If Slave Enable is LOW (SLE), the slave latches are continuously enabled. FIGURE 1. Parallel Expansion www.fairchildsemi.com 2 DM93L38 Logic Diagram 3 www.fairchildsemi.com DM93L38 Absolute Maximum Ratings(Note 1) Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IOH HIGH Level Output Current Min Norm Max Units 4.5 5 5.5 V 2 IOL LOW Level Output Current TA Free Air Operating Temperature −55 tS (H) Setup Time HIGH or LOW 30 tS (L) DA to CP 22 tH (H) Hold Time HIGH or LOW tH (L) DA to CP V 0.7 V −400 µA 4.8 mA 125 °C ns 0 ns −4.0 tS (H) Setup Time HIGH or LOW 0 tS (L) An to CP 0 tH (H) Hold Time HIGH or LOW 0 tH (L) An to CP 0 tW (H) CP Pulse Width HIGH or LOW 40 tW (L) ns ns ns 30 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −10 mA VOH HIGH Level VCC = Min, IOH = Max, Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min IOL = Max Output Voltage VIH = Min, VIL = Max Min Typ (Note 2) Max Units −1.5 V 2.4 V 0.3 V mA II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 IIH HIGH Level Input Current VCC = Max, VI = 2.4V 50 µA IIL LOW Level Input Current VCC = Max, VI = 0.3V −2 mA IOS Short Circuit Output Current VCC = Max (Note 3) −25 mA ICC Supply Current VCC = Max (Note 4) 70 mA −2.5 Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN and all input grounded. www.fairchildsemi.com 4 VCC = +5.0V, TA = +25°C Symbol CL = 15 pF Parameter Min Units Max tPLH Propagation Delay 68 tPHL Bn or Cn or Zn 95 tPLH Propagation Delay 70 tPHL DA to Zn 92 tPLH Propagation Delay 65 tPHL CP to Zn 57 5 ns ns ns www.fairchildsemi.com DM93L38 Switching Characteristics DM93L38 8-Bit Multiple Port Register Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6