To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. HM6216514I Series Wide Temperature Range Version 8 M SRAM (512-kword × 16-bit) ADE-203-1303B (Z) Rev. 1.0 Oct. 23, 2002 Description The Hitachi HM6216514I Series is 8-Mbit static RAM organized 524,288-word × 16-bit. HM6216514I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII. Features • • • • • • • • Single 5.0 V supply: 5.0V ± 10 % Fast access time: 55 ns (Max) Power dissipation: Active: 10 mW/MHz (Typ) Standby: 7.5 µW (Typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. Temperature range: –40 to +85°C HM6216514I Series Ordering Information Type No. HM6216514LTTI-5SL 2 Access time 55 ns Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DE) HM62162514I Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 (Top view) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O15 Data input/output CS Chip select WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC Power supply VSS Ground 3 HM6216514I Series Block Diagram LSB A5 A6 A7 A4 A3 A8 A9 A10 A11 A12 MSB A13 V CC V SS Row decoder I/O0 • • • • • Memory matrix 2,048 x 2,048 Column I/O • • Input data control Column decoder I/O15 LSB A15 A16 A17 A18 A0 A1 A2 A14MSB • • CS LB UB WE OE 4 Control logic • • HM62162514I Series Operation Table CS WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × High-Z High-Z Standby × × × H H High-Z High-Z Standby L H L L L Dout Dout Read L H L H L Dout High-Z Lower byte read L H L L H High-Z Dout Upper byte read L L × L L Din Din Write L L × H L Din High-Z Lower byte write L L × L H High-Z Din Upper byte write L H H × × High-Z High-Z Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to V SS VCC –0.5 to + 7.0 1 V 2 Terminal voltage on any pin relative to V SS VT –0.5* to V CC + 0.3* V Power dissipation PT 1.0 W Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –40 to +85 °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +7.0 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input high voltage VIH 2.2 — VCC + 0.3 V Input low voltage VIL –0.3 — 0.8 V Ambient temperature range Ta –40 — 85 °C Note: Note 1 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns. 5 HM6216514I Series DC Characteristics Parameter Symbol Min Typ* 1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL or, LB = UB =VIH , VI/O = VSS to V CC Operating current I CC — — 20 mA CS = VIL, Others = VIH/VIL, I I/O = 0 mA Average operating current I CC1 — 16 35 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS = VIL, Others = VIH/VIL I CC2 — 2 5 mA Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS ≤ 0.2 V, VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V Standby current I SB — 0.1 0.3 mA CS = VIH Standby current I SB1 — 0.8 10 µA 0 V ≤ Vin (1) CS ≥ V CC – 0.2 V or (2) LB = UB ≥ V CC – 0.2 V, CS ≤ 0.2 V Output high voltage VOH 2.4 — — V I OH = –1 mA Output low voltage VOL — — 0.4 V I OL = 2.1 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin — — 8 pF Vin = 0 V 1 Input/output capacitance CI/O — — 10 pF VI/O = 0 V 1 Note: 6 1. This parameter is sampled and not 100% tested. HM62162514I Series AC Characteristics (Ta = –40 to +85°C, VCC = 5.0 V ± 10 %, unless otherwise noted.) Test Conditions • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (50 pF) (Including scope and jig) Read Cycle HM6216514I -5 Parameter Symbol Min Max Unit Notes Read cycle time t RC 55 — ns Address access time t AA — 55 ns Chip select access time t ACS — 55 ns Output enable to output valid t OE — 35 ns Output hold from address change t OH 10 — ns LB, UB access time t BA — 55 ns Chip select to output in low-Z t CLZ 10 — ns 2, 3 LB, UB enable to low-z t BLZ 5 — ns 2, 3 Output enable to output in low-Z t OLZ 5 — ns 2, 3 Chip deselect to output in high-Z t CHZ 0 20 ns 1, 2, 3 LB, UB disable to high-Z t BHZ 0 20 ns 1, 2, 3 Output disable to output in high-Z t OHZ 0 20 ns 1, 2, 3 7 HM6216514I Series Write Cycle HM6216514I -5 Parameter Symbol Min Max Unit Notes Write cycle time t WC 55 — ns Address valid to end of write t AW 50 — ns Chip selection to end of write t CW 50 — ns 5 Write pulse width t WP 40 — ns 4 LB, UB valid to end of write t BW 50 — ns Address setup time t AS 0 — ns 6 Write recovery time t WR 0 — ns 7 Data to write time overlap t DW 25 — ns Data hold from write time t DH 0 — ns Output active from end of write t OW 5 — ns 2 Output disable to output in high-Z t OHZ 0 20 ns 1, 2 Write to output in high-Z t WHZ 0 20 ns 1, 2 Notes: 1. t CHZ, tOHZ , t WHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS, a low WE and a low LB or a low UB. A write begins at the latest transition among CS going low, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS going high, WE going high and LB going high or UB going high. t WP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS going low to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS or WE going high to the end of write cycle. 8 HM62162514I Series Timing Waveform Read Cycle t RC Address Valid address tAA tACS CS tCLZ*2, 3 tCHZ*1, 2, 3 tBHZ*1, 2, 3 tBA LB, UB tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE tOLZ*2, 3 Dout High impedance tOH Valid data 9 HM6216514I Series Write Cycle (1) (WE Clock) tWC Valid address Address tWR*7 tCW*5 CS tBW LB, UB tAW tWP*4 WE tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout 10 HM62162514I Series Write Cycle (2) (CS Clock, OE = VIH) tWC Valid address Address tAW tAS*6 tWR*7 tCW*5 CS tBW LB, UB tWP*4 WE tDW tDH Valid data Din High impedance Dout 11 HM6216514I Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Valid address Address tAW tCW*5 tWR*7 CS tAS*6 tBW LB, UB tWP*4 WE tDW Valid data Din High impedance Dout 12 tDH HM62162514I Series Low VCC Data Retention Characteristics (Ta = –40 to +85°C) Parameter Symbol Min Typ* 2 Max Unit Test conditions*1 VCC for data retention VDR 2.0 — — V Vin ≥ 0V (1) CS ≥ V CC – 0.2 V or (2) LB = UB ≥ V CC – 0.2 V CS ≤ 0.2 V Data retention current I CCDR — 0.8 10 µA VCC = 3.0 V, Vin ≥ 0V (1) CS ≥ V CC – 0.2 V or (2) LB = UB ≥ V CC – 0.2 V CS ≤ 0.2 V — — ns See retention waveform — — ns Chip deselect to data retention time t CDR Operation recovery time tR 0 t RC* 3 Notes: 1. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If LB, UB controls data retention mode, LB, UB must be LB = UB ≥ V CC – 0.2 V, CS must be CS ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 2. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed. 3. t RC = read cycle time. 13 HM6216514I Series Low V CC Data Retention Timing Waveform (1) (CS Controlled) t CDR Data retention mode tR V CC 4.5 V 2.2 V V DR CS 0V CS ≥ VCC – 0.2 V Low V CC Data Retention Timing Waveform (2) (LB, UB Controlled) t CDR Data retention mode V CC 4.5 V 2.2 V V DR LB, UB 0V 14 LB, UB ≥ VCC – 0.2 V tR HM62162514I Series Package Dimensions HM6216514LTTI Series (TTP-44DE) As of January, 2002 Unit: mm 18.41 18.81 Max 23 10.16 44 0.80 *0.27 ± 0.07 0.25 ± 0.05 22 0.80 0.13 M 11.76 ± 0.20 1.005 Max *Dimension including the plating thickness Base material dimension 0.13 ± 0.05 0.10 *0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0˚ – 5˚ 0.50 ± 0.10 Hitachi Code JEDEC JEITA Mass (reference value) 0.68 1 TTP-44DE — — 0.43 g 15 HM6216514I Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright C Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 16