HI-8685, HI-8686 February 2001 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data PIN CONFIGURATIONS (Top View) DESCRIPTION The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology. Both products incorporate the digital logic and analog line receiver circuitry in a single device. The receivers on the HI-8685 and the HI-8686 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. The -10 version of the HI-8685 allows the incorporation of an external 10KΩ resistance in series with each ARINC input for lightning protection without affecting ARINC level detection. Both products offer high speed 16-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. A reset pin is also provided for power-on initialization. DATARDY 1 28 Vcc D15 2 27 GAPCLK D14 3 26 TESTA D13 4 25 TESTB D12 5 24 RESET D11 6 D10 7 D9 8 D8 9 HI-8685PSI 23 HI-8685PST 22 & 21 HI-8685PSI-10 HI-8685PST-10 20 D7 10 19 READ D6 11 18 D0 D5 12 17 D1 D4 13 16 D2 GND 14 15 D3 RINB (-10) RINA (-10) ERROR PARITY ENB HI-8685 28-Pin Plastic SOIC - WB Package FEATURES ! Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data ! High speed parallel 16-bit data bus ! Error detection - word length and parity ! Reset input for power-on initialization ! On-chip line receiver ! Input hysteresis of at least 2 volts ! Test lnputs bypass analog inputs ! Simplified lightning protection with the ability to add 10 Kohm external series resistors N/C - 1 24 - RESET D12 - 2 23 - RINB-10 D11 - 3 D10 - 4 D9 - 5 HI-8686PQI HI-8686PQT 22 - RINB 21 - RINA 20 - RINA-10 D8 - 6 19 - ERROR D7 - 7 18 - PARITY ENB D6 - 8 17 - N/C ! Small, surface mount, plastic package options: SOIC, TQFP and PLCC ! Military processing available HI-8686 32-Pin PlasticTQFP Package (See page 8 for additional pin configurations) (DS8685 Rev. G) HOLT INTEGRATED CIRCUITS 1 02/01 HI-8685, HI-8686 PIN DESCRIPTIONS SIGNAL FUNCTION DESCRIPTION DATA RDY OUTPUT Receiver data ready flag. A high level indicates data is available in the receive buffer. Flag goes low when the first 16-bit byte is read. D0 to D15 OUTPUT 16-bit parallel data bus (tri-state) GND POWER 0V READ INPUT Read strobe. A low level transfers receive buffer data to the data bus PARITY ENB INPUT Parity Enable - A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged ERROR OUTPUT Error Flag. A high level indicates a bit count error (number of ARINC bits was less than or greater than 32) and/or a parity error if parity detection was enabled (PARITY ENB high) RINA/RINA-10 INPUT Positive direct ARINC serial data input (both RINA and RINA-10 on HI-8686) RINB/RINB-10 INPUT Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686) RESET INPUT Internal logic states are initialized with a low level TESTA INPUT Used in conjunction with the TESTB input to bypass the built-in analog line receiver circuitry TESTB INPUT Used in conjunction with the TESTA input to bypass the built-in analog line receiver circuitry GAPCLK INPUT Gap Clock. Determines the minimum time required between ARINC words for detection. The minimum word gap time is between 16 and 17 clock cycles of this signal. Vcc POWER +5V ±10% supply FUNCTIONAL DESCRIPTION The HI-8685 and HI-8686 are serial to 16-bit parallel converters. The incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. The receive data can be accessed using two 16-bit parallel read operations while the next serial data steam is being received. lation, the buffered inputs drive a differential amplifier. The differential signal is compared to levels derived from a divider between VCC and GND. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A valid ARINC One/Zero input sets a latch and a Null input resets the latch. RECEIVER INPUTS HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10) The block diagram for both the HI-8685 and HI-8685-10 products is found in Figure 1. Both have built-in receivers eliminating the need for additional external ARINC level detection circuitry. The only difference between the two products is the amount of internal resistance in series with each ARINC input. Since any added external series resistance will affect the voltage translation, the HI-8685-10 product has only 25KΩ of the 35KΩ series resistance required for proper ARINC 429 level detection. The remaining 10KΩ required is available to the user for incorporation in external circuitry such as for lightning protection. HI-8685 ARINC INPUTS (RINA & RINB) HI-8686 ARINC INPUTS Typically 35KΩ resistors are in series with both the RINA and RINB ARINC 429 inputs. They connect to level translators whose resistance to GND is typically 10KΩ. After level trans- The HI-8686 has both sets of ARINC inputs, RINA/RINA-10 and RINB/RINB-10 available to the user. HOLT INTEGRATED CIRCUITS 2 HI-8685, HI-8686 PARITY ENB ERROR ERROR DETECT CLK PARITY DETECT 10KΩ 25KΩ RINA RINB 10KΩ 25KΩ ESD PROTECTION & LINE RECEIVER RXA CLOCK & DATA DETECT RXB BIT 32 BIT 32 DATA RINA-10 32-BIT SHIFT REG. BIT COUNT 32 32-BIT RECEIVE 32 BUFFER 32-BIT TO 16-BIT 16 MUX D0 - D15 RINB-10 TESTA TESTB GAP DETECT BYTE COUNT DATA RDY GAPCLK RESET READ Figure 1. Block Diagram FUNCTIONAL DESCRIPTION (cont.) PROTOCOL DETECTION GAP DETECTION The ARINC clock and One/Zero data that are derived from the digital outputs of the built-in line receiver is illustrated in Figure 3. The resulting steam of digital data is shifted into a 32-bit input register. The end of a data word is detected by an internal counter that times out when a data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK is a function of the mininum gap time specified for the type of ARINC data being received. Table 1 indicates typical frequencies that may be used for the various data rates normally encountered. The ARINC clock and One/Zero data can also be created from the TESTA and TESTB inputs as shown in Figure 4. When either test input is high, the built-in analog line driver is disabled. For ARINC 561 operation, the TESTA and TESTB digital input data streams must be derived from the ARINC 561 data, clock and sync with external logic. DATABUS TYPE BIT PERIOD (µs) MINIMUM GAP (µs) GAP CLOCK MHz GAP DETECTION TIME (µs) 429 10 45 0.75 1.0 1.5 21.3 - 22.7 16 - 17 10.7 - 11.3 429 69 - 133 310 - 599 0.1 160 - 170 575 69 - 133 310 - 599 0.1 160 - 170 561 69 - 133 103 - 200 0.2 80 - 85 Table 1 - Typical Gap Detection Times HOLT INTEGRATED CIRCUITS 3 HI-8685, HI-8686 FUNCTIONAL DESCRIPTION (cont.) ERROR CHECKING Once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. When parity detection is enabled (PARITY ENB high), the received word is checked for odd parity. If there is a parity error, the 32nd bit of the received data word is set high. If parity checking is disabled (PARITY ENB low) the 32nd bit of the data word is always the 32nd ARINC bit received. The ERROR flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. The ERROR flag is reset low when the next valid ARINC word is written into the receive buffer or when RESET is pulsed low. READING RECEIVE BUFFER When the data word is transferred to the receive buffer, the DATA RDY pin goes high. The data word can then be read in two 16-bit bytes by pulsing the READ input low as indicated in Figure 5. The first read cycle resets DATA RDY low and increments an internal counter to the second 16-bit byte. The relationship between each bit of an ARINC word received and each bit of the two 16-bit data bus bytes is specified in Figure 2. When a new ARINC word is received it always overwrites the receive buffer. If the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new ARINC word. However, if the DATA RDY pin goes high between the reading of the first and second bytes, the first byte is no longer valid because the corresponding second byte has been overwritten by the new ARINC word. Also, the next read will be of the first byte of the new ARINC word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. Read Byte Data Bus Bits ARINC Bits 1st Byte 1 D0 - D15 ARINC 1 - ARINC 16 2nd Byte 2 D0 - D15 ARINC 17 - ARINC 32 FIGURE 2. ORDER OF RECEIVED DATA RESET A low on the RESET input sets a flip-flop which initializes the internal logic. When RESET goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. TEST MODE The built-in differential line receiver can be disabled allowing the data and clock detection circuitry to be driven directly with digital signals. The logical OR function of the TESTA and TESTB is defined in Truth Table 1. The two inputs can be used for testing the receiver logic and for inputting ARINC 429 type data derived from another source/ protocol. See Figure 4 for typical test input timing. The device should always be initialized with RESET immediately after entering the test mode to clear a partial word that may have been received since the last word gap. Otherwise, an ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after RESET goes high. When exiting the test mode, both test inputs should be held low and the device initialized with RESET. TRUTH TABLE 1. RINA (-10) RINB (-10) TESTA TESTB RXA RXB -1.50V to +1.50V -1.50V to +1.50V 0 0 0 0 -3.25V to -6.50V +3.25V to +6.50V 0 0 0 1 +3.25V to +6.50V -3.25V to -6.50V 0 0 1 0 X X 0 1 0 1 X X 1 0 1 0 X X 1 1 0 0 X = don't care HOLT INTEGRATED CIRCUITS 4 HI-8685, HI-8686 TIMING DIAGRAMS ARINC Data Bits 29 30 31 28 Word Gap 4 Bit Periods Min. 32 1 2 +10V VDIFF RINA - RINB 0V -10V DERIVED DATA DERIVED CLOCK FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429 ARINC Data Bits 29 30 31 28 Word Gap 4 Bit Periods Min. 32 1 2 +5V TESTA 0V +5V TESTB 0V DERIVED DATA DERIVED CLOCK FIGURE 4 - TEST INPUT TIMING FOR ARINC 429 DERIVED DATA 32nd ARINC bit tDRDY tRDYCLR DATA RDY tRDPW tRR 1st 16-bits READ tRD D0 - D15 2nd 16-bits tFD VALID VALID FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING HOLT INTEGRATED CIRCUITS 5 HI-8685, HI-8686 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND Supply voltages VCC ....................................................... +7.0V Supply Voltages VCC .................................................+5V ± 10% Voltage on inputs RINA (-10) to RINB (-10) ......... +29V to - 29V All other input pins..................-0.3 to Vcc +0.3 Temperature Range Industrial Screening .............. -40°C to +85°C Hi-Temp Screening .............. -55°C to +125°C Military Screening..................-55°C to +125°C DC current per input pin ....................... +10mA Junction Temperature, Tj .................... ≤+175°C Power dissipation at 25°C plastic 28-pin SO..... 1.8W, derate 14.1mW/°C plastic 28-pin PLCC .2.3W, derate 18.2mW/°C plastic 32-pin SO......1.6W, derate 15.4mW/°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. Solder Temperature Leads ............................. +280°C for 10 sec Package body ..................................+220°C Storage Temperature ............. -65°C to +150°C DC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 10.0 13.0 2.75 5.0 ARINC Bus Inputs (RINA, RINB, RINA-10 & RINB-10) Differential input voltage one or zero null common mode VDIN VNIN VCOM differential voltage " " " " with respect to GND 6.5 - Input resistance RINA (-10) to RINB(-10) RINA (-10) or RINB(-10) to GND or VCC RDIFF RSUP supplies floating " " " ' 30 19 75 40 - Kohm Kohm Input capacitance (Guaranteed but not tested) differential to GND to VCC CDIFF CG CH RINA (-10) to RINB (-10) - - 20 20 20 pF pF pF HOLT INTEGRATED CIRCUITS 6 volts volts volts HI-8685, HI-8686 DC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 2.0 0.0 - VCC 0.8 volts volts -1.0 - 1.0 - µA µA - - 8.0 pF IOH = -1.0 mA IOL = 1.6 mA 2.7 - - 0.4 volts volts VOH = 5.0V VOL = 0.0V -1.0 - 1.0 - µA µA - - 15 pF - - 6.5 mA MIN TYP Digital Inputs (RESET, GAPCLK, READ, PARITY ENA, TESTA & TESTB) Input voltage high low VIH VIL Input current source sink IIH IIL Input capacitance CI VIN = 5.0V VIN = 0.0V Outputs (D0 to D15, ERROR & DATA RDY) Output voltage high low VOH VOL Output tri-state current (D0 - D15 only) IIH IIL Output capacitance CO Operating Supply Current VCC ICC VIN = 0.0V, outputs open AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS READ pulse width SYMBOL TEST CONDITIONS tRDPW MAX UNITS 50 ns Data delay from READ tRD 20 ns READ to data floating tFD 20 ns tRDYCLR 25 ns READ to DATA RDY clear READ pulse to next READ pulse tRR GAPCLK frequency fGC 32nd ARINC bit to DATA RDY tDRDY HOLT INTEGRATED CIRCUITS 7 25 ns 1 16 MHz 17 clocks HI-8685, HI-8686 ADDITIONAL HI-8685 PIN CONFIGURATION (See page 1 for additional pin configurations) 4 D12 5 D11 6 D10 7 D9 8 D8 9 D7 10 D6 11 3 2 1 28 27 26 HI-8685PJI HI-8685PJT & HI-8685PJI-10 HI-8685PJT-10 12 13 14 15 16 17 25 TESTB 24 RESET 23 RINB (RINB-10) 22 RINA (RINA-10) 21 ERROR 20 PARITY ENB 19 READ 18 HI-8685 28-Pin Plastic PLCC ORDERING INFORMATION BUILT-IN LINE EXT. 10KΩ TEMPERATURE RECV'R REQUIRED RANGE PART NUMBER PACKAGE DESCRIPTION FLOW BURN IN LEAD FINISH HI-8685PJI 28 PIN PLASTIC PLCC YES NO -40°C TO +85°C I NO SOLDER HI-8685PJT 28 PIN PLASTIC PLCC YES NO -55°C TO +125°C T NO SOLDER HI-8685PSI 28 PIN PLASTIC SOIC - WB YES NO -40°C TO +85°C I NO SOLDER HI-8685PST 28 PIN PLASTIC SOIC - WB YES NO -55°C TO +125°C T NO SOLDER HI-8686PQI 32 PIN PLASTIC TQFP YES OPTIONAL -40°C TO +85°C I NO SOLDER HI-8686PQT 32 PIN PLASTIC TQFP YES OPTIONAL -55°C TO +125°C T NO SOLDER HI-8685PJI-10 28 PIN PLASTIC PLCC YES YES -40°C TO +85°C I NO SOLDER HI-8685PJT-10 28 PIN PLASTIC PLCC YES YES -55°C TO +125°C T NO SOLDER HI-8685PSI-10 28 PIN PLASTIC SOIC - WB YES YES -40°C TO +85°C I NO SOLDER HI-8685PST-10 28 PIN PLASTIC SOIC - WB YES YES -55°C TO +125°C T NO SOLDER Legend: WB - Wide Body HOLT INTEGRATED CIRCUITS 8 HI-8685, HI-8686 PACKAGE DIMENSIONS inches (millimeters) 28-PIN PLASTIC PLCC Package Type: 28J PIN NO. 1 IDENT .026 ± .003 x 30° (.660 ± .076 x 30°) .045 x 45° .490 ± .005 (12.446 ± .127) SQ. .050 ± .005 (1.27 ± .127) .454 ± .002 (11.532 ± .051) SQ. .029 ± .003 (.737 ± .076) .017 ± .004 (.432 ± .102) SEE DETAIL A .152 ± .002 (3.861 ± .051) .010 ± .0003 (.256 ± .0076) DETAIL A .020 MIN (.508 MIN) .420 ± .010 (10.668 ± .254) .015 ± .002 (.381 ± .051) .020 MIN (.508 ΜΙΝ) .035 R TYP (.889 R) 28-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) Package Type: 28HW .7055 ± .0045 (17.920 ± .114) .0105 ± .0015 (.2667 ± .0381) .295 ± .004 (7.493 ± .102) .4065 ± .0125 (10.325 ± .318) SEE DETAIL A .018 TYP (.457) .095 ± .005 (2.413 ± .127) 0° to 8° .050 TYP (1.27) .0075 ± .0035 (.191 ± .089) .033 ± .017 DETAIL A (.838 ± .432) HOLT INTEGRATED CIRCUITS 9 HI-8685, HI-8686 PACKAGE DIMENSIONS inches (millimeters) 32 PIN PLASTIC THIN QUAD FLAT PACK (TQFP) Package Type: 32PTQS .00057 ± .00022 (0.0145 ± .0055) .3543 BSC SQ. (9.00 BSC) .0315 BSC (0.80 BSC) .2755 BSC SQ. (7.00 BSC) .0148 ± .0030 (0.375 ± .075) .0236 ± .0059 (0.60 ± .15) .0551 ± .002 (1.4 ± .05) .0055R ± .0024 (0.14R ± .06) See Detail A .063 MAX. (1.60 MAX.) 0° ≤ Θ ≤ 7° .0039 ± .002 (0.10 ± .05) .0031 R MIN. (0.08 R MIN.) Detail A HOLT INTEGRATED CIRCUITS 10