ON NCP1201 Pwm current−mode controller for universal off−line supplies featuring low standby power with fault protection mode Datasheet

NCP1201
PWM Current−Mode
Controller for Universal
Off−Line Supplies Featuring
Low Standby Power with
Fault Protection Modes
Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhances the
previous NCP1200 series by offering a reduced optocoupler current with
additional Brownout Detection Protection (BOK). Similarly, the circuit
allows the implementation of complete off−line AC−DC adapters, battery
chargers or Switchmode Power Supplies (SMPS) where standby power is
a key parameter.
The NCP1201 features efficient protection circuitry. When in the
presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.)
the control permanently disables the output pulses to avoid subsequent
damage to the system. The IC only restarts when the user cycles the
mains power supply.
With the low power internal structure, operating at a fixed
60 or 100 kHz, the controller supplies itself from the high−voltage rail,
avoiding the need of an auxiliary winding. This feature naturally eases
the designer’s task in battery charger applications. Finally, current−mode
control provides an excellent audio−susceptibility and inherent
pulse−by−pulse control.
When the load current falls down to a pre−defined setpoint (VSKIP)
value, e.g. the output power demand diminishes, the IC automatically
enters the skip cycle mode and can provide excellent efficiency under
light load conditions. The skip mode is designed to operate at relatively
lower peak current so that acoustic noise that commonly takes place will
not happen with NCP1201.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
AC Line Brownout Detect Protection, BOK Function
Latchoff Mode Fault Protection
No Auxiliary Winding Operation
Internal Output Short−Circuit Protection
Extremely Low No−Load Standby Power
Current−Mode with Skip−Cycle Capability
Internal Overtemperature Shutdown
Internal Leading Edge Blanking
250 mA Gate Peak Current Driving Capability
Internally Fixed Switching Frequency at 60 or 100 kHz
Built−in Frequency Jittering for EMI Reduction
Direct Optocoupler Connection
Pb−Free Packages are Available
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
201Dx
ALYW
G
1
8
PDIP−8
P SUFFIX
CASE 626
8
1201Py0
AWL
YYWWG
1
1
x
y
y
xx
A
L
Y, YY
W, WW
G or G
= Device Code: 6 for 60 kHz
1 for 100 kHz
= Device Code: 6 for 60 kHz
10 for 100 kHz
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
BOK
1
8
HV
FB
2
7
NC
CS
3
6
VCC
GND
4
5
DRV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Typical Applications
• AC−DC Adapters
• Offline Battery Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 4
1
Publication Order Number:
NCP1201/D
NCP1201
C3
R3
470 p 100 k
250 V 1.0 W
L1
DF06S
BR1
U1
1
4
6.5 V, 600 mA
*
R1
195.7 k
L3
1N5819
47 mH
1.0 A
8
3
1N4937
2
2
90X264
Vac
D2
D1
C1
4.7 m
400 V
+
C2
4.7 m
400 V
+ C5
10 m
6
3
+
4
5
NCP1201
Q1
MTD1N60E
C7
1.0 n
250 VAC Y1
+ C4
10 mF
SFH6156−2
4
R2
4.3 k
R4
2.7
0.5 W
L2
470 mH
0.2 A
* Please refer to the application information section.
Figure 1. Typical Application Example
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2
1
2
3
+
−
1
470 mH
0.2 A
T1
U2
D3
5V1
+ C6
10 m
NCP1201
Iref
BOK
8
1
+
+
−
−
50 mA
+
10.5 V/12.5 V
1.92 V
−
−
80 K 1.07 V
Skip Cycle
Comparator
+
Set
Output
−
Reset
Reset
24 K
GND
NC
Maximum 83%
Duty Cycle
Output
250 ns
L.E.B.
4
20 k
+
−
57 k
25 k
Vref
6
VCC
Q
TSD
+
−
Enable
+
CS
7
−
Oscillator
60 or 100 kHz Clock
+
3
−
HV Current
Source
Reset
FB
2
+ Output
HV
Startup
Blanking
Output
0.9 V
Overload
Figure 2. Simplified Functional Block Diagram
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3
5
250 mA
Internal
Regulator
Vref
DRV
NCP1201
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
BOK
Bulk OK
This pin detects the input line voltage by sensing the bulk capacitor, and
disables the PWM when line voltage is lower than normal.
2
FB
Sets the Peak Current Setpoint
By connecting an optocoupler to this pin, the peak current setpoint is adjusted according to the output power demand. Internal monitoring of this
pin level triggers the fault management circuitry.
3
CS
Current Sense Input
This pin senses the primary inductor current and routes it to the internal
comparator via an LEB circuit.
4
GND
The IC Ground
−
5
DRV
Driving Pulses
The driver’s output to an external MOSFET.
6
VCC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10 mF.
7
NC
No Connection
This unconnected pin ensures adequate creepage distance between High
Voltage pin to other pins.
8
HV
Generates the VCC from the Line
Connected to the high−voltage rail, this pin injects a constant current into
the VCC capacitor.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Power Supply Voltage, Pin 6
Rating
VCC
−0.3, 16
V
Input/Output Pins
Pins 1, 2, 3, 5
VIO
−0.3, 6.5
V
Maximum Voltage on Pin 8 (HV)
VHV
500
V
Thermal Resistance, Junction−to−Air, PDIP−8 Version
Thermal Resistance, Junction−to−Air, SOIC Version
RqJA
RqJA
100
178
°C/W
°C/W
Operating Junction Temperature Range
TJ
−40 to +150
°C
Operating Ambient Temperature Range
TA
−25 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
ESD Capability, HBM (All pins except VCC and HV pins) (Note 1)
−
2.0
kV
ESD Capability, Machine Model (All pins except VCC and HV pins) (Note 1)
−
200
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) > 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) > 200 V per JEDEC standard: JESD22−A115.
2. Latchup Current Maximum Rating: ±150 mA per JEDEC standard: JESD78.
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NCP1201
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C,
VCC = 11 V unless otherwise noted)
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Current Source Turns−Off
VCCOFF
11.5
12.5
13.5
V
VCC Decreasing Level at which the Current Source Turns−On
VCCON
9.6
10.5
11.3
V
Internal IC Current Consumption, No Output Load on Pin 5
ICC1
440
905
1300
mA
Internal IC Current Consumption, 1.0 nF Output Load on Pin 5
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
ICC2
0.75
1.6
1.6
2.1
2.2
2.8
Internal IC Current Consumption, Latchoff Phase
ICC3
405
575
772
mA
High−Voltage Current Source at VCCON – 0.2 V
IC1
3.6
5.3
7.1
mA
High−Voltage Current Source at VCC = 0 V
IC2
7.5
11.1
15
mA
ILEAK
−
30
70
mA
Output Voltage Rise−Time (CL = 1.0 nF, 10 V Output)
Tr
−
116
−
ns
Output Voltage Fall−Time (CL = 1.0 nF, 10 V Output)
Tf
−
41
−
ns
Characteristic
DYNAMIC SELF−SUPPLY
mA
INTERNAL STARTUP CURRENT SOURCE
HV Pin Leakage Current @ 450 V, VCC Pin Connected to Ground
OUTPUT SECTION
Source Resistance (VDRV = )
ROH
26
38
60
W
Sink Resistance (VDRV = )
ROL
4.0
10
22
W
CURRENT SENSE SECTION (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
IIB−CS
−
10
100
nA
Maximum Current Sense Input Threshold
VILIMIT
0.8
0.9
1.0
V
Default Current Sense Threshold for Skip Cycle Operation
VILSKIP
250
325
390
mV
Propagation Delay from Current Detection to Gate OFF State
TDEL
35
65
160
ns
Leading Edge Blanking Duration
TLEB
150
260
400
ns
52
92
60
100
72
117
−
−
493
822
−
−
74
83
87
%
OSCILLATOR SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 KW)
Oscillation Frequency
FOSC
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
Built−in Frequency Jittering (as a function of Vcc voltage)
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
Fjitter
Maximum Duty Cycle
Dmax
kHz
Hz/V
FEEDBACK SECTION (VCC = 11 V, Pin 5 Unloaded)
Internal Pullup Resistor
RUP
10
17
24
kW
Feedback Pin to Pin 3 Current Setpoint Division Ratio
Iratio
2.9
3.3
4.0
−
BROWNOUT DETECT SECTION
BOK Input Threshold Voltage
BOK Input Bias Current (VBOK < Vth)
Source Bias Current (Turn on After VBOK > Vth)
Vth
1.75
1.92
2.05
V
IIB−BOK
−
11
100
nA
ISC
40
50
58
mA
VSKIP
0.96
1.07
1.18
V
TSD
−
145
−
°C
THYST
−
25
−
°C
FREQUENCY SKIP CYCLE SECTION
Built−in Frequency Skip Cycle Comparator Voltage Threshold
THERMAL SHUTDOWN
Thermal Shutdown Trip Point, Temperature Rising (Note 3)
Thermal Shutdown Hysteresis
3. Verified by design.
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NCP1201
VCCON, VCC ON THRESHOLD VOLTAGE (V)
VCCOFF, VCC OFF THRESHOLD VOLTAGE (V)
TYPICAL CHARACTERISTICS
12.9
12.7
12.5
12.3
12.1
11.9
11.7
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
10.8
10.6
10.4
10.2
10
9.8
−25
Figure 3. VCC OFF Threshold Voltage
vs. Junction Temperature
ICC2, CURRENT CONSUMPTION (mA)
ICC1, CURRENT CONSUMPTION
WITH NO LOAD (mA)
1000
900
800
700
600
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
2.6
1 nF Load
2.4
2.2
100 KHz
2.0
1.8
60 KHz
1.6
1.4
125
−25
Figure 5. IC Current Consumption, ICC1
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 6. IC Current Consumption, ICC2
vs. Junction Temperature
700
8.0
IC1, HV PIN STARTUP CURRENT
SOURCE (mA)
ICC3, IC CURRENT CONSUMPTION
AT LATCHOFF PHASE (mA)
125
Figure 4. VCC ON Threshold Voltage
vs. Junction Temperature
1100
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
600
500
400
300
VCC = 11 V
6.5
5.0
3.5
2.0
0.5
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 7. IC Current Consumption at Latchoff Phase
vs. Junction Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. HV Pin Startup Current Source
vs. Junction Temperature
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125
NCP1201
TYPICAL CHARACTERISTICS
80
ILEAK, LEAKAGE CURRENT (mA)
IC2, HV PIN STARTUP CURRENT
SOURCE (mA)
14
12
10
8
6
VCC = 0 V
60
40
20
0
4
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
−25
Figure 9. HV Pin Startup Current Source
vs. Junction Temperature
20
60
ROL, SINK RESISTANCE (W)
ROH, SOURCE RESISTANCE (W)
125
Figure 10. Leakage Current vs.
Junction Temperature
70
50
40
30
20
10
0
16
12
8
4
0
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
−25
12
11
10
9
8
7
6
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 12. Output Sink Resistance
vs. Junction Temperature
VILIMIT, MAXIMUM CURRENT SENSE THRESHOLD (V)
Figure 11. Output Source Resistance
vs. Junction Temperature
IIB−CS, CS PIN INPUT BIAS CURRENT (nA)
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 13. CS Pin Input Bias Current @ 1.0 V
vs. Junction Temperature
1.00
0.96
0.92
0.88
0.84
0.80
−25
Figure 14. Maximum Current Sense Threshold
vs. Junction Temperature
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0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
NCP1201
340
100
TDEL, PROPAGATION DELAY (nS)
VILSKIP, DEFAULT CURRENT SENSE
THRESHOLD FOR SKIP CYCLE (mV)
TYPICAL CHARACTERISTICS
330
320
310
300
290
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
40
25
350
300
250
200
150
100
50
0
125
120
100 KHz
100
80
60 KHz
60
40
20
0
125
−25
Figure 17. Leading Edge Blanking Duration
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 18. Oscillator Frequency
vs. Junction Temperature
1400
85
Dmax, MAXIMUM DUTY CYCLE (%)
Fjitter, FREQUENCY JITTER (Hz/V)
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Propagation Delay from Current Detection to
Gate Driver vs. Junction Temperature
FOSC, OSCILLATOR FREQUENCY (kHz)
TLEB, LEADING EDGE BLANKING
DURATION (nS)
55
−25
400
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
70
10
125
Figure 15. Default Current Setpoint for Skip Cycle
vs. Junction Temperature
−25
85
1200
1000
100 KHz
800
600
60 KHz
400
200
0
84
83
82
81
80
79
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. Maximum Duty Cycle
vs. Junction Temperature
Figure 19. Frequency Jittering
vs. Junction Temperature
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125
NCP1201
3.40
Iratio, FEEDBACK PIN TO PIN 3
CURRENT RATIO
RUP, INTERNAL PULLUP RESISTOR (kW)
TYPICAL CHARACTERISTICS
19
18
17
16
15
14
3.30
3.25
3.20
3.15
3.10
3.05
3.00
13
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
−25
125
2.00
1.95
1.90
1.85
1.80
1.75
1.70
−25
125
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
12
11
10
9
8
7
VBOK < Vth
6
125
−25
Figure 23. BOK Threshold Voltage
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 24. BOK Input Bias Current
vs. Junction Temperature
1.15
VSKIP, SKIP CYCLE COMPARATOR
THRESHOLD VOLTAGE (V)
51
ISC, BOK BIAS CURRENT (mA)
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Feedback Pin to Pin 3 Current Setpoint Ratio
vs. Junction Temperature
IIB−BOK, BOK INPUT BIAS CURRENT (nA)
Figure 21. FB Pin Pullup Resistor
vs. Junction Temperature
Vth, BOK INPUT THRESHOLD VOLTAGE (V)
3.35
50
49
48
47
46
VBOK < Vth
1.10
1.05
1.00
0.95
45
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
−25
125
Figure 25. BOK Source Bias Current
vs. Junction Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 26. Skip Mode Threshold Voltage
vs. Junction Temperature
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125
NCP1201
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1201 implements a standard current mode
architecture where the switch−off time is dictated by the peak
current setpoint. This component represents the ideal
candidate where low part−count is the key criteria,
particularly in low−cost AC−DC adapters, auxiliary supplies
etc. Due to its high−performance High−Voltage technology,
the NCP1201 incorporates all the necessary components
normally needed in UC384X based supplies: timing
components, feedback devices, low−pass filter and
self−supply. This later point emphasizes the fact that
ON Semiconductor’s NCP1201 does NOT need an auxiliary
winding to operate: the device is self supplied from the
high−voltage rail and delivers a VCC to the IC. This system
is named the Dynamic Self−Supply (DSS).
Vripple = 2 V
Dynamic Self−Supply
The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation following
simple logic equations:
POWER−ON: IF VCC < VCCOFF THEN
Current Source is ON, no output pulses
IF VCC decreasing > VCCON THEN
Current Source is OFF, output is pulsing
IF VCC increasing < VCCOFF THEN
Current Source is ON, output is pulsing
Typical values are: VCCOFF = 12.5 V, VCCON = 10.5 V
To better understand the operation principle, Figure 27
sketch offers the necessary explanation,
VCCOFF = 12.5 V
VCC
VCCON = 10.5 V
ON
OFF
Current
Source
Output Pulses
10 mS
30 mS
50 mS
70 mS
90 mS
Figure 27. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg max equals
22 nC. With a maximum switching frequency of 70 kHz for
the oscillator 60 kHz, the average power necessary to drive
the MOSFET (excluding the driver efficiency and
neglecting various voltage drops) is:
Pdriver + Fsw(max)
Qg
VCC
The total standby power consumption at no−load will
therefore heavily rely on the internal IC current
consumption plus the driving current (altered by the driver’s
efficiency). Suppose that the IC is supplied from a 350 VDC
line. The current flowing through pin 8 is a direct image of
the NCP1201 current consumption (neglecting the
switching losses of the HV current source). If ICC2 equals
2.1 mA @ TA = 25°C, then the power dissipated (lost) by the
IC is simply: 350 V x 2.1 mA = 735 mW. For design and
reliability reasons, it would be interesting to reduce this
source of wasted power. In order to achieve that, different
methods can be used.
1. Use a MOSFET with lower gate charge Qg;
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes:
(eq. 1)
Where,
Pdriver = Average Power to drive the MOSFET
Fsw(max) = Maximum switching frequency
Qg = MOSFET’s gate charge
VCC = VGS level applied to the gate of the MOSFET
To obtain an estimation of the driving current, simply
divide Pdriver by VCC,
Idriver + Fsw(max)
VmainsPEAK
p
Qg + 1.54 mA (eq. 2)
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2
(eq. 3)
NCP1201
Skipping Cycle Mode
The NCP1201 automatically skips switching cycles when
the output power demand drops below a preset level. This is
accomplished by monitoring the FB pin. In normal
operation, FB pin imposes a peak current according to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this set−point reaches the
skip mode threshold level, 1.07 V, the IC prevents the
current from decreasing further down and starts to blank the
output pulses, i.e. the controller enters the so−called Skip
Cycle Mode, also named Controlled Burst Operation. The
power transfer now depends upon the width of the pulse
bunches, Figure 29.
Suppose we have the following component values:
Lp, primary inductance = 1.0 mH
Fsw, switching frequency = 60 kHz
Ip (skip) = 200 mA (or 333 mV/Rsense)
The theoretical power transfer is therefore:
Our power contribution example drops to 223 V x 2.1 m
= 468.3 mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to migrate from
the package to the resistor. The resistor value should be
carefully selected to account for low−line startup.
HV
Mains
Cbulk
1
8
2
7
3
6
4
5
Figure 28. A Simple Diode Naturally Reduces the
Average Voltage on Pin 8
1
2
3. Permanently force the VCC level above VCCOFF
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self−supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. By using this approach,
user need to make sure the auxiliary voltage never
exceeds the 16 V limit for all line conditions.
Lp
Ip2
Fsw + 1.2 W
(eq. 4)
If the controller enters Skip Cycle Mode with a pulse packet
length of 20 ms over a recurrent period of 100 ms, then the
total power transfer reduced to 1.2 W x 0.2 = 240 mW.
To better understand how this Skip Cycle Mode takes
place, a look at the operation mode versus the FB pin voltage
level shown below, immediately gives the necessary insight.
FB
4.2 V, FB Pin Open
2.97 V, Upper Dynamic Range
Normal Current Mode Operation
Skip Cycle Operation
Ip(min) = 333 mV / Rsense
1.07 V
Figure 29. Feedback Pin Voltage and Modes of Operation
When FB pin voltage level is above the skip cycle threshold
(1.07 V by default), the peak current cannot exceed
0.9 V/Rsense. When the IC enters the skip cycle mode, the
peak current cannot go below VSKIP/3.3. By using the peak
current limit reduction scheme, the skip cycle takes place at
a lower peak current, which guarantees noise free operation.
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NCP1201
P1 = 0.4 W
P2 = 1.8 W
P3 = 3.6 W
Figure 30. MOSFET VDS at Various Power Levels, P1<P2<P3
Max peak
current
300.0M
200.0M
Skip Cycle
current limit
100.0M
0
315.4uS
882uS
1.450mS
2.017mS
2.585mS
Figure 31. The Skip Cycle Takes Place at Low Peak Current
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NCP1201
VBULK
Brownout Detect Protection
In order to avoid output voltage bouncing during
electricity brownout, a Bulk Capacitor Voltage Comparator
with programmable hysteresis is included in this device. The
non−inverting input, pin 1, is connected to the voltage
divider comprised of RUpper and RLower as shown in
Figure 32, monitoring the bulk capacitor voltage level. The
inverting input is connected to a threshold voltage of 1.92 V
internally. As bulk capacitor voltage drops below the
pre−programmed level, i.e. Pin 1 voltage drops below
1.92 V, a reset signal will be generated via internal
protection logic to the PWM Latch to turn off the Power
Switch immediately. At the same time, an internal current
source controlled by the state of the comparator provides a
mean to setup the voltage hysteresis through injecting
current into RLower. The equations below (Equations 5 and
6) show the relationship between VBULK levels and the
voltage divider network resistors.
Equations for resistors selection are:
RUpper ) RLower +
RLower +
(VBULK_H * VBULK_L)
50 mA
[1.92 V(VBULK_H * VBULK_L)]
(50 mA VBULK_H)
VREF
RUpper
BOK
50 mA
+
1.92 V
−
UVLO
RLower
Figure 32. Brown−Out Protection Operation
(eq. 5)
(eq. 6)
Assume VBULK_H = 90 Vdc and VBULK_L = 80 Vdc, by
using 4.3 kW for RLower then RUpper is about 195.7 kW.
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NCP1201
APPLICATION INFORMATION
MOSFET’s Qg which ICC2 ≈ ICC1 + Fsw x Qg. Final
calculation should thus account for the total gate−charge Qg
your MOSFET will exhibit.
If the power estimation is beyond the limit, supply to the
VCC with a series diode as suggested in Figure 28 can be
used. As a result, it will drop the average input voltage and
Power Dissipation
The NCP1201 can be directly supplied from the DC rail
through the internal DSS circuitry. The average current
flowing through the DSS is therefore the direct image of the
NCP1201 current consumption. The total power dissipation
can be evaluated using: (VHVDC * 11 V) ICC2. If the
device operates on a 250 VAC rail, the maximum rectified
voltage can go up to 350 VDC. At TA = 25°C, ICC2 = 2.1 mA
for the 60 kHz version over a 1.0 nF capacitive load. As a
result, the NCP1201 will dissipate 350 V x 2.1 mA =
735 mW (TA = 25_C). The SOIC−8 package offers a
junction−to−ambient thermal resistance RqJ−A of 178°C/W.
Adding some copper area around the device pins will help
to improve this number, 12mm x 12mm copper can drop
RqJ−A down to 100°C/W with 35 m copper thickness (1 oz.)
or 6.5mm x 6.5mm with 70 m copper thickness (2 oz.). With
this later number, we can compute the maximum power
dissipation the package accepts at an ambient of 50°C:
P max +
Tjmax−TAmax
RqJ−A
2 1.6 mA + 356.5 mW .
lower the dissipation to 350 V
p
Alternatively, an auxiliary winding can be used to disable
the DSS and hence reduce the power consumption down to
VCC x ICC2. By using the auxiliary winding supply method,
the rectified auxiliary voltage should permanently stays
above the VCCOFF threshold voltage, keeping DSS off and
is safely kept well below the 16 V maximum rating for
whole operating conditions.
Non−Latching Shutdown
In some cases, it might be desirable to shut off the device
temporarily and authorize its restart once the control signal
has disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB pin voltage below the VSKIP
level, the output pulses are disabled as long as FB pin
voltage is pulled below the skip mode threshold voltage. As
soon as FB pin is released, the the device resumes its normal
operation again. Figure 33 depicts an application example.
+ 750 mW (TJmax = 125_C),
which is acceptable with our previous thermal budget. For
the DIP8 package, adding a min−pad area of 80mm2 of 35 m
copper (1 oz.), RqJ−A drops from 100°C/W to about 75°C/W.
In the above calculations, ICC2 is based on a 1.0 nF output
capacitor. As seen before, ICC2 will depend on your
Q1
ON/OFF
1
8
2
7
3
6
4
5
Figure 33. A Method to Shut Down the Device Without a Definitive Latchoff State
Fault Protection
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
often required to permanently latchoff the power supply in
presence of a fault. This fault can be either a short−circuit on
the output or a broken optocoupler. In this later case, it is
important to quickly react in order to avoid a lethal output
voltage runaway. The NCP1201 includes a circuitry tailored
to tackle both events. A short−circuit forces the output
voltage to be at a low level, preventing a bias current to
circulate in the optocoupler LED. As a result, the FB pin
level is pulled up to 4.2 V, as internally imposed by the IC.
The peak current set−point goes to the maximum and the
supply delivers a rather high power with all the associated
effects. However, this can also happen in case of feedback
loss, e.g. a broken optocoupler. To account for those
situations, NCP1201 included a dedicated overload
protection circuitry. Once the protection activated, the
circuitry permanently stops the pulses while the VCC moves
between 10−12 V to maintain this latchoff state. The system
resets when the user purposely cycles the VCC down below
3.0 V, e.g. when the power plug is removed from the mains.
In NCP1201, the controller stops all output pulses as soon
as the error flag is asserted, irrespective to the VCC level.
However, to avoid false triggers during the startup sequence,
NCP1201 purposely omits the very first VCC descent from
12 to 10 V. The error circuitry is actually armed just after this
sequence, e.g. VCC crossing 10 V. Figure 34 details the
timing sequence. The VCC capacitor should be calculated
carefully to offer a sufficient time out during the first startup
VCC descent.
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NCP1201
As shown below, the fault logic is armed once VCC crosses
10 V after startup phase. When powering the device from an
auxiliary winding, meeting this condition can sometimes be
problematic since upon startup, VCC naturally goes up and
not down as with a DSS. As a result, VCC never crosses 10 V
and the fault logic is not activated. If a short−circuit takes
place, the fault circuitry activates as soon as VCC collapses
below 10 V (because of the coupling between Vaux and
Vout), but in presence of a broken optocoupler, i.e. feedback
is open, VCC increases and the fault will never triggered! To
avoid this problem, the application note “Tips and Tricks
with NCP1200, AN8069/D” offers some possible solutions
where the DSS is kept for protection logic operation only but
all the driving power is derived from the auxiliary winding.
Some solutions even offer the ability to disable the DSS in
standby and benefit to low standby power.
VCC
Regulation
occurs here
12 V
10 V
No synchronization
between DSS and
fault event
Time
Drv
Overload is
not activated
Overload is
activated
Driver
Pulses
Latched−off
Time
FB
Open−loop
FB level
Regulation
Fault occurs here
Time
Figure 34. Fault Protection Timing Diagram
that this time corresponds to 6.0 ms. Therefore a VCC fall
time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level, i.e. how long does it take for the
VCC line to decrease from 12.5 V to 10.5 V. The required
time depends on the powerup sequence of your system, i.e.
when you first apply the power to the device. The
corresponding transient fault duration due to the output
capacitor charging must be less than the time needed to
discharge from 12.5 V to 10.5 V, otherwise the supply will
not properly startup. The test consists in either simulating or
measuring in the laboratory to determine time required for
the system to reach the regulation at full load. Let’s assume
capacitor using the following formula: Dt + DV
i
C , with
DV = 2.0 V. Then for a wanted Dt of 10 ms, C equals 9.0 mF
or 10 mF for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 575 mA typical. This explains the VCC
falling slope changes after latchoff in Figure 34.
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NCP1201
Protecting the Controller Against Negative
Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between VCC and GND. If the current sense
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user unplugs the power supply, the controller is still
fed by its VCC capacitor and keeps activating the MOSFET
ON and OFF with a peak current limited by Rsense.
Unfortunately, if the quality coefficient Q of the resonating
network formed by Lp and Cbulk is low (e.g. the MOSFET
Rdson + Rsense are small), conditions are met to make the
circuit resonate and thus negatively bias the controller. Since
we are talking about ms pulses, the amount of injected
charge (Q = I x t) immediately latches the controller which
brutally discharges its VCC capacitor. If this VCC capacitor
is of sufficient value, its stored energy damages the
controller. Figure 35 depicts a typical negative shot
occurring on the HV pin where the brutal VCC discharge
testifies for latchup.
Figure 35. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Another option (Figure 37) consists in wiring a diode from
VCC to the bulk capacitor to force VCC to reach UVLOlow
sooner and thus stops the switching activity before the bulk
capacitor gets deeply discharged. For security reasons, two
diodes can be connected in series.
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 36). Please note that the negative
spike is clamped to –2 x Vf due to the diode bridge. Please
refer to AND8069 for power dissipation calculations.
3
Rbulk
> 4.7 k
2
+
Cbulk
1
8
2
7
3
6
4
5
3
+
Cbulk
1 +
CVCC
Figure 36. A simple resistor in series avoids any
latchup in the controller
1
8
2
7
3
6
4
5
D3
1N4007
1 +
CVCC
Figure 37. or a diode forces VCC to reach
UVLOlow sooner
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16
NCP1201
ORDERING INFORMATION
Device
NCP1201P60
Package
PDIP−8
NCP1201P60G
PDIP−8
(Pb−Free)
NCP1201D60R2
SOIC−8
NCP1201D60R2G
NCP1201P100
SOIC−8
(Pb−Free)
50 Units / Rail
2500 Units / Tape & Reel
PDIP−8
NCP1201P100G
PDIP−8
(Pb−Free)
NCP1201D100R2
SOIC−8
NCP1201D100R2G
Shipping†
SOIC−8
(Pb−Free)
50 Units / Rail
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NCP1201
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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18
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1201
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
H
DIM
A
B
C
D
F
G
H
J
K
L
M
N
M
K
G
0.13 (0.005)
M
T A
M
B
M
The product described herein (NCP1201), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may
be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
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Phone: 81−3−5773−3850
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For additional information, please contact your
local Sales Representative.
NCP1201/D