Sony CXG1109EN Receive dual low noise amplifier/mixer Datasheet

CXG1109EN
Receive Dual Low Noise Amplifier/Mixer
Description
The CXG1109EN is a receive dual low noise amplifier/
mixer MMIC. This IC is designed using the Sony’s
GaAs J-FET process.
16 pin VSON (Plastic)
Features
• High conversion gain: Gp = 16.5 to 17dB (LNA Typ.)
Gc = 9.5 to 10dB (MIX Typ.)
• Low noise figure:
NF = 1.5dB (LNA Typ.)
NF = 4 to 5dB (MIX Typ.)
• Single 3V power supply operation
• Low LO input power operation PLO = –12.5dBm
• Single CTL pin achieved by the built-in inverter
circuit
• 16-pin VSON package
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
4.5
V
• Input power
PIN
+13
dBm
• Current consumption
IDD
15
mA
• Operating temperature Topr
–35 to +85
°C
• Storage temperature
Tstg
–65 to +150 °C
Applications
800MHz Japan digital cellular telephones (PDC)
Recommended Operating Voltages
2.7 to 3.3
• Supply voltage
VDD
• Control voltage
VCTL (H) 2.4 to 3.3
VCTL (L)
0 to 0.3
Structure
GaAs J-FET MMIC
Pin Configuration
Block Diagram
LNA RFIN1
9
8
LNA RFIN2
6
LNA RFOUT
3
IFOUT 16
V
V
V
1
9
8
LNA RFIN2
CAP 10
7
CAP
GND 11
6
LNA RFOUT/VDD1 (LNA)
CTL 12
5
GND
GND 13
4
OPT
GND 14
3
MIX RFIN
VDD2 (LO AMP) 15
2
GND
IFOUT/VDD3 (MIX) 16
1
LO IN
LNA RFIN1
MIX RFIN
LO IN
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00924A1Y-PS
CXG1109EN
Electrical Characteristics
Conditions: VDD = 3.0V, VCTL (H) = 3.0V, VCTL (L) = 0V, fRF1 = 885MHz, fRF2 = 810MHz, fLO = fRF – 130MHz,
PLO = –12.5dBm, Ta = 25°C, unless otherwise specified
Low Noise Amplifier Block
Item
Current
consumption
Control current
Symbol
Path
RF frequency VCTL Min. Typ. Max. Unit
—
IDD
—
ICTL
RFIN1 → RFOUT
Power gain
—
H
—
1.9
2.5
—
L
—
1.9
2.5
—
H
—
55
80
—
L
–1
0
—
H
15
16.5
19
L
—
–20 –15
H
—
–26 –21
L
15
17
19
fRF1
Gp
Noise figure
NF
Input IP3
IIP3
Isolation
ISO
RFIN2 → RFOUT
fRF2
RFIN1 → RFOUT
fRF1
H
—
1.5
2
RFIN2 → RFOUT
fRF2
L
—
1.5
2
RFIN1 → RFOUT
fRF1
H
–11 –7.5
—
RFIN2 → RFOUT
fRF2
L
RFOUT → RFIN1
fRF1
H
17
22
—
RFOUT → RFIN2
fRF2
L
18
23
—
–12.5 –9
—
Measurement
condition
mA
When no
signal
µA
dB
When a
small signal
dB
dBm ∗1
dB
When a
small signal
Mixer Block
Item
Symbol
Current consumption
IDD
Power gain
GC
Noise figure
NF
Input IP3
IIP3
LO to RF leak level
Plk
RF frequency
Min.
Typ.
Max.
Unit
—
—
4.5
6.2
mA
fRF1
9
10
11.5
fRF2
8.5
9.5
11
fRF1
—
5
6.5
fRF2
—
4
5.5
fRF1
–1
1.5
—
fRF2
–1.5
1.5
—
fRF1
—
–22
–17
fRF2
—
–24
–19
Measurement condition
When no signal
dB
When a small signal
dB
dBm ∗1
dBm
fLO = 755MHz
fLO = 680MHz
The values shown above are the specified values on the Sony’s recommended evaluation board.
∗1 Conversion from the IM3 suppression ratio for two-wave input: PRF = –30dBm (low noise amplifier block)/
–22.5dBm (mixer block) at fRFoffset = 100kHz.
–2–
CXG1109EN
Recommended Evaluation Circuit
LNA RFIN1
L5
50Ω
L13
L4
9
8
10
7
11
6
12
5
L14
C6
L6
50Ω
L15
C9
CTL
LNA RFIN2
L11
C8
LNA RFOUT
C10
50Ω
L12
13
4
14
3
15
2
16
1
VDD1 (LNA)
L3
VDD2 (LO AMP)
C5
IFOUT
50Ω
C4
C2
L1
L2
C7
R1
L8
MIX RFIN
L9
50Ω
L10
C1
L7
LOIN
VDD3 (MIX)
50Ω
C3
L1
220nH
L11
18nH
C6
18pF
L2
220nH
L12
12nH
C7
1000pF
L3
33nH
L13
22nH
C8
100pF
L4
18nH
L14
5.6nH
C9
47pF
L5
6.8nH
L15
27nH
C10
1000pF
L6
27nH
C1
5pF
R1
680Ω
L7
39nH
C2
1000pF
L8
22nH
C3
1000pF
L9
1.2nH
C4
100pF
L10
8.2nH
C5
1000pF
–3–
CXG1109EN
Example of Representative Characteristics (Ta = 25°C)
Low Noise Amplifier Block
Gp, NF vs. fRF
Gp, NF vs. fRF
Gp
17.5
Gp – Power gain [dB]
17
2.5
16.5
2
16
NF
15.5
15
1.5
3
VDD = 3V
VCTL = 0V
Gp
17
Gp – Power gain [dB]
VDD = 3V
VCTL = 3V
NF – Noise figure [dB]
17.5
18
3
2.5
16.5
16
2
15.5
15
1.5
NF – Noise figure [dB]
18
NF
14.5
14.5
1
14
800 810 820 830 840 850 860 870 880 890 900
1
14
800 810 820 830 840 850 860 870 880 890 900
fRF – RF frequency [MHz]
fRF – RF frequency [MHz]
POUT, IM3 vs. PIN
POUT, IM3 vs. PIN
20
20
10
10
–10
0
POUT
–20
–30
IM3
–40
–50
VDD = 3V
VCTL = 3V
fRF1 = 885MHz
fRF2 = 885.1MHz
–60
–70
–80
–40 –35 –30 –25 –20 –15 –10 –5 0
POUT – RF output power [dBm]
POUT – RF output power [dBm]
0
–10
POUT
–20
–30
–40
IM3
–50
VDD = 3V
VCTL = 0V
fRF1 = 810MHz
fRF2 = 810.1MHz
–60
–70
–80
–40 –35 –30 –25 –20 –15 –10 –5 0
5 10
PIN – RF input power [dBm]
PIN – RF input power [dBm]
–4–
5 10
CXG1109EN
Mixer Block
Gc, NF vs. fRF
12
7
Gc
6
10
9
8
VDD = 3V
fLO = fRF – 130MHz
PLO = –12.5dBm
5
7
4
6
NF – Noise figure [dB]
Gc – Conversion gain [dB]
11
NF
5
3
4
800 810 820 830 840 850 860 870 880 890 900
fRF – RF frequency [MHz]
POUT, IM3 vs. PIN
POUT, IM3 vs. PIN
20
20
10
10
–10
0
POUT
POUT
–20
–30
–40
–50
IM3
–60
VDD = 3V
fRF1 = 885MHz
fRF2 = 885.1MHz
fLO = 755MHz
–70
–80
–40 –35 –30 –25 –20 –15–10 –5
0
POUT – IF output power [dBm]
POUT – IF output power [dBm]
0
5 10
PIN – RF input power [dBm]
–10
–20
–30
–40
IM3
–50
–60
VDD = 3V
fRF1 = 810MHz
fRF2 = 810.1MHz
fLO = 680MHz
–70
–80
–40 –35 –30 –25 –20 –15 –10 –5
0
PIN – RF input power [dBm]
–5–
5 10
CXG1109EN
IIP3, PLK vs. PLO
IIP3, PLK vs. PLO
3
–10
3
2.5
1.5
–20
1
PLK
0.5
0
–25
VDD = 3V
fRF1 = 885MHz
fRF2 = 885.1MHz
fLO = 755MHz
–20
–10
–15
–5
1.5
1
–20
0.5
PLK
0
–30
–1
–25
0
–20
Gc, NF vs. PLO
8
6
6
5
NF
4
VDD = 3V
fRF1 = 885MHz
fRF2 = 885.1MHz
fLO = 755MHz
–15
–10
–5
Gc – Conversion gain [dB]
7
14
NF – Noise figure [dB]
Gc – Conversion gain [dB]
8
Gc
–20
–5
–30
0
10
16
9
10
0
–25
–10
Gc, NF vs. PLO
10
14
2
–15
PLO – LO input power [dBm]
16
4
–25
VDD = 3V
fRF1 = 810MHz
fRF2 = 810.1MHz
fLO = 680MHz
–0.5
PLO – LO input power [dBm]
12
–15
IIP3
12
VDD = 3V
fRF1 = 810MHz
fRF2 = 810.1MHz
fLO = 680MHz
10
7
8
6
6
5
NF
4
2
2
0
–25
PLO – LO input power [dBm]
8
Gc
3
0
9
4
3
2
–20
–15
–10
–5
PLO – LO input power [dBm]
–6–
0
NF – Noise figure [dB]
–0.5
2
PLK – LO leak power [dBm]
–15
IIP3 – Input power [dBm]
IIP3 – Input power [dBm]
2
PLK – LO leak power [dBm]
2.5
IIP3
–1
–25
–10
CXG1109EN
IDD3 – Mixer block current consumption (MIX) [mA]
Example of Characteristics for Option Resistance R1 Changed (Ta = 25°C)
IDD3 (MIX) vs. R1
8
VDD = 3V
7
6
5
4
3
2
1
0
OPEN 1200 820 680
470 390 270 220 150
R1 – Option resistance [Ω]
GC, NF vs. R1
GC, NF vs. R1
12
GC – Conversion gain, NR–Noise figure [dB]
GC
10
8
VDD = 3V
fRF = 885MHz
fLO = 755MHz
PLO = –12.5dBm
6
NF
4
2
OPEN 1200 820 680
GC
10
8
6
4
R1 – Option resistance [Ω]
4
–20
–21
3.5
–21
3
–22
2.5
–23
–22
2.5
–23
2
–24
IIP3
–25
1.5
1
VDD = 3V
fRF = 885MHz
fLO = 755MHz
PLO = –12.5dBm
0.5
0
OPEN 1200 820 680
–26
IIP3 – Input IP3 [dBm]
3
IIP3, PLK vs. R1
–20
PLK – LO leak power [dBm]
IIP3 – Input IP3 [dBm]
PLK
470 390 270 220 150
R1 – Option resistance [Ω]
IIP3, PLK vs. R1
3.5
NF
2
OPEN 1200 820 680
470 390 270 220 150
4
VDD = 3V
fRF = 810MHz
fLO = 680MHz
PLO = –12.5dBm
–27
2
IIP3
–25
1.5
PLK
1
0.5
0
OPEN 1200 820 680
–28
470 390 270 220 150
R1 – Option resistance [Ω]
–24
VDD = 3V
fRF = 810MHz
fLO = 680MHz
PLO = –12.5dBm
–27
–28
470 390 270 220 150
R1 – Option resistance [Ω]
–7–
–26
PLK – LO leak power [dBm]
GC – Conversion gain, NF–Noise figure [dB]
12
CXG1109EN
Recommended Evaluation Board
50mm
50mm
Front
LNA RFIN1
LNA RFIN2
IFOUT
LNA RFOUT
LO IN
MIX RFIN
CTL
VDD2
GND
VDD3
VDD1
Glass fabric-base 4-layer epoxy board (thickness: 0.2mm × 2)
GND for the whole 2nd and 3rd layers
Enlarged Diagram of Center Part
L6
L14
L5
L15
L4
L13
C6
C9
C7
L11
L12
C10
C5
C4
C8
L3
R1
L8
L7
C1
L1
L2
C3
C2
–8–
L9
L10
CXG1109EN
Package Outline
Unit: mm
16PIN VSON (PLASTIC)
0.9 MAX
0.6
3.5
0.05 S
A
0.5 ± 0.2
2.7
2.5
0.35 ± 0.1
S
B
2x
0.4
0.35 ± 0.1
0.2 S B
4x
1.4
0.2 S A B
0.03 ± 0.03
0.2 ± 0.01
0.23 ± 0.02
0.05 M S A-B
Soldrer Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02 g
SONY CODE
VSON-16P-01
Kokubu Ass’y
16PIN VSON (PLASTIC)
0.9 MAX
0.6
3.5
0.05 S
A
B
0.5 ± 0.2
2.5
2.7
0.35 ± 0.1
S
2x
0.4
0.35 ± 0.1
0.2 S B
4x
1.4
0.03 ± 0.03
0.2 ± 0.01
0.05 M S A-B
0.23 ± 0.02
0.2 S A B
Soldrer Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02 g
SONY CODE
VSON-16P-01
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
–9–
Sony Corporation
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