LINER LTC2450IDCTRMPBF Easy-to-use, ultra-tiny 16-bit adc Datasheet

LTC2450
Easy-to-Use, Ultra-Tiny
16-Bit DS ADC
Description
Features
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GND to VCC Single-Ended Input Range
0.02LSB RMS Noise
2LSB INL, No Missing Codes
2LSB Offset Error
4LSB Full-Scale Error
Single Conversion Settling Time for Multiplexed
Applications
Single Cycle Operation with Auto Shutdown
350µA Supply Current
50nA Sleep Current
30 Conversions Per Second
Internal Oscillator—No External Components
Required
Single Supply, 2.7V to 5.5V Operation
SPI Interface
Ultra-Tiny 2mm × 2mm DFN Package
Applications
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System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Industrial Process Control
Data Acquisition
Embedded ADC Upgrades
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Easy Drive is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The LTC®2450 is an ultra-tiny 16-bit analog-to-digital
converter. The LTC2450 uses a single 2.7V to 5.5V supply,
accepts a single-ended analog input voltage, and communicates through an SPI interface. It includes an integrated
oscillator that does not require any external components.
It uses a delta-sigma modulator as a converter core and
provides single-cycle settling time for multiplexed applications. The converter is available in a 6-pin, 2mm × 2mm
DFN package. The internal oscillator does not require any
external components. The LTC2450 includes a proprietary
input sampling scheme that reduces the average input
sampling current several orders of magnitude.
The LTC2450 is capable of up to 30 conversions per second and, due to the very large oversampling ratio, has
extremely relaxed antialiasing requirements. The LTC2450
includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring
accuracy over time and over the operating temperature
range. The converter uses its power supply voltage as the
reference voltage and the single-ended, rail-to-rail input
voltage range extends from GND to VCC.
Following a conversion, the LTC2450 can automatically
enter a sleep mode and reduce its power to less than
200nA. If the user samples the ADC once a second, the
LTC2450 consumes an average of less than 50µW from
a 2.7V supply.
Typical Application
Integral Nonlinearity, VCC = 3V
3.0
VCC = VREF = 3V
2.5
2.0
0.1µF
1.5
10µF
1k
SENSE
CLOSE TO
CHIP
0.1µF
VCC
VIN
LTC2450
CS
SCK
SDO
GND
3-WIRE SPI
INTERFACE
INL (LSB)
1.0
0.5
TA = –45°C, 25°C, 90°C
0
–0.5
–1.0
–1.5
2450 TA01
–2.0
–2.5
–3.0
0
0.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
2.5
3.0
2450 G02
2450fa
LTC2450
Absolute Maximum Ratings
(Notes 1, 2)
PIN CONFIGURATION
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage (VIN).............–0.3V to (VCC + 0.3V)
Digital Input Voltage.......................–0.3V to (VCC + 0.3V)
Digital Output Voltage....................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2450C................................................. 0°C to 70°C
LTC2450I.............................................. –40°C to 85°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10sec).................... 300°C
TOP VIEW
6 SCK
VCC 1
VIN 2
7
5 SDO
4 CS
GND 3
DC PACKAGE
6-LEAD (2mm x 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 102°C/W
EXPOSED PAD (PIN7) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REAL (MINI) TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2450CDC#TRMPBF
LTC2450CDC#TRPBF
LCTR
6-Lead (2mm × 2mm) Plastic DFN
0°C to 70°C
LTC2450IDC#TRMPBF
LTC2450IDC#TRPBF
LCTR
6-Lead (2mm × 2mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Resolution (No missing codes)
(Note 3)
●
MIN
Integral Nonlinearity
(Note 4)
Offset Error
TYP
MAX
●
2
10
LSB
●
2
8
LSB
16
Offset Error Drift
Bits
0.02
Gain Error
UNITS
0.01
●
LSB/°C
0.02
% of FS
Gain Error Drift
0.02
LSB/°C
Transition Noise
1.4
µVRMS
80
dB
Power Supply Rejection DC
100Hz-100kHz
ANALOG INPUT The ● denotes the specifications which apply over the full operating temperature range,otherwise
specifications are at TA = 25°C.
SYMBOL
PARAMETER
VIN
Input Voltage Range
CIN
IN Sampling Capacitance
IDC_LEAK (VIN)
IN DC Leakage Current
ICONV
Input Sampling Current (Note 9)
CONDITIONS
MIN
●
TYP
0
MAX
VCC
0.35
VIN = GND (Note 5)
VIN = VCC (Note 5)
●
●
–10
–10
UNITS
1
1
50
pF
10
10
nA
nA
nA
2450fa
LTC2450
Power Requirements The ● denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion
Sleep
CONDITIONS
MIN
●
CS = GND (Note 6)
CS = VCC (Note 6)
TYP
2.7
350
0.05
●
●
MAX
UNITS
5.5
V
600
0.5
µA
µA
DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specifications which apply over the full
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
●
VIL
Low Level Input Voltage
●
IIN
Digital Input Current
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –800mA
l
VOL
Low Level Output Voltage
IO = –1.6mA
l
IOZ
Hi-Z Output Leakage Current
TYP
MAX
UNITS
VCC – 0.3
V
–10
0.3
V
10
µA
10
l
pF
VCC – 0.5
V
–10
0.4
V
10
µA
TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
tCONV
Conversion Time
●
fSCK
SCK Frequency Range
●
tlSCK
SCK Low Period
●
250
ns
thSCK
SCK High Period
●
250
ns
t1
CS Falling Edge to SDO Low Z
(Notes 7, 8)
●
0
100
ns
t2
CS Rising Edge to SDO High Z
(Notes 7, 8)
●
0
100
ns
t3
CS Falling Edge to SCK Falling Edge
●
100
tKQ
SCK Falling Edge to SDO Valid
●
0
(Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
Note 3: Guaranteed by design, not subject to test.
Note 4: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band. Guaranteed by design, test correlation and 3 point transfer curve
measurement.
MIN
TYP
MAX
UNITS
29
33.3
42
ms
2
MHz
ns
100
ns
Note 5: CS = VCC. A positive current is flowing into the DUT pin.
Note 6: SCK = VCC or GND. SDO is high impedance.
Note 7: See Figure 3.
Note 8: See Figure 4.
Note 9: Input sampling current is the average input current drawn from the
input sampling network while the LTC2450 is actively sampling the input.
2450fa
LTC2450
Typical Performance Characteristics
VCC = VREF = 5V
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
TA = –45°C, 25°C, 90°C
–0.5
–1.0
–1.5
–2.0
–2.0
–2.5
–2.5
–3.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
4.0
3.5
TA = –45°C, 25°C, 90°C
0
–1.5
0
4.5
–0.5
–1.0
–3.0
3.0
2.5
0
0.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
2.5
0
–50
3.0
Gain Error vs Temperature
2.75
4.0
4.0
VCC = 4.1V
1.5
1.0
3.0
2.5
VCC = 4.1V
2.0
1.5
VCC = 5V
VCC = 3V
0.5
0.5
0
–50
3.5
1.0
VCC = 5V
TRANSITION NOISE RMS (µV)
4.5
GAIN ERROR (LSB)
4.5
2.0
50
25
0
TEMPERATURE (°C)
–25
75
100
0
–50
–25
75
50
25
0
TEMPERATURE (°C)
CONVERSION CURRENT (µA)
TRANSITION NOISE RMS (µV)
2.00
1.25
1.00
1.75
VCC = 5V
1.50 VCC = 4.1V
1.25
VCC = 3V
1.00
0.50
0.75
100
0
–50 –30
50
–10 10 30
TEMPERATURE (°C)
70
90
2450 G06
500
2.25
1.50
2.25
2.00
Conversion Mode Power Supply
Current vs Temperature
TA = 25°C
2.50
1.75
2.50
2450 G05
Transition Noise vs Output Code
2.75
100
0.25
2450 G04
3.00
75
Transition Noise vs Temperature
3.00
2.5
50
25
0
TEMPERATURE (°C)
–25
2450 G03
5.0
3.0
VCC = 3V
0.5
2450 G02
Offset Error vs Temperature
VCC = 3V
VCC = 4.1V
1.0
5.0
3.5
VCC = 5V
2.0
1.5
2450 G01
OFFSET (LSB)
Maximum INL vs Temperature
5.0
VCC = VREF = 3V
2.5
INL (LSB)
INL (LSB)
Integral Nonlinearity, VCC = 3V
3.0
INL (LSB)
Integral Nonlinearity, VCC = 5V
3.0
VCC = 5V
VCC = 3V
0.50
0.75
VCC = 5V
400
VCC = 3V
300
VCC = 4.1V
200
100
0.25
0
0.80
1.00
0.40
0.60
0
0.20
OUTPUT CODE (NORMALIZED TO FULL SCALE)
2450 G07
0
–45
–25
35
15
–5
55
TEMPERATURE (°C)
75
95
2450 G08
2450fa
LTC2450
Typical Performance Characteristics
Average Power Dissipation
vs Temperature, VCC = 3V
Sleep Mode Power Supply
Current vs Temperature
10000
AVERAGE POWER DISSIPATION (µW)
SLEEP MODE CURRENT (nA)
250
200
VCC = 5V
150
100
VCC = 4.1V
50
VCC = 3V
0
–45
–25
35
15
–5
55
TEMPERATURE (°C)
25Hz OUTPUT SAMPLE RATE
1000
75
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
10
–50
95
–25
0
25
50
TEMPERATURE (°C)
Power Supply Rejection vs
Frequency at VCC
Conversion Period vs
Temperature
0
42
–20
40
CONVERSION TIME (ms)
REJECTION (dB)
100
2450 G12
2450 G09
–40
–60
–80
–100
75
38
VCC = 5V, 4.1V, 3V
36
34
32
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
2450 G10
30
–45 –25
35
15
55
–5
TEMPERATURE (°C)
75
95
2450 G11
2450fa
LTC2450
Pin Functions
VCC (Pin 1): Positive Supply Voltage and Converter Reference Voltage. Bypass to GND (Pin 3) with a 10µF capacitor
in parallel with a low series inductance 0.1µF capacitor
located as close to the part as possible.
VIN (Pin 2): Analog Input Voltage.
GND (Pin 3): Ground. Connect to a ground plane through
a low impedance connection.
CS (Pin 4): Chip Select Active LOW Digital Input. A LOW on
this pin enables the SDO digital output. A HIGH on this pin
places the SDO output pin in a high impedance state.
SDO (Pin 5): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
SCK (Pin 6): Serial Clock Input. SCK synchronizes the serial
data output. While digital data is available (the ADC is not
in CONVERT state) and CS is LOW (ADC is not in SLEEP
state) a new data bit is produced at the SDO output pin
following every falling edge applied to the SCK pin.
Exposed Pad (Pin 7): Ground. The Exposed Pad must be
soldered to the same point as Pin 3.
FUNCTIONAL Block Diagram
VCC
VCC
VIN
GND
REF +
16 BIT DS
A/D
CONVERTER
REF –
CS
SDO
SCK
SPI
INTERFACE
INTERNAL
OSCILLATOR
2450 BD
Figure 1. Functional Block Diagram
2450fa
LTC2450
Applications Information
Converter Operation
Converter Operation Cycle
The LTC2450 is a low power, delta-sigma analog-todigital converter with a simple 3-wire interface (see
Figure 1). Its operation is composed of three successive
states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed
by the SLEEP state and ends with the DATA OUTPUT
state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK) and the
active low chip select input (CS).
The CONVERT state duration is determined by the LTC2450
conversion time (nominally 33.3 milliseconds). Once
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2450 enters
the SLEEP state and remains here until both the chip
select and clock inputs are low (CS = SCK = LOW). Following this condition the ADC transitions into the DATA
OUTPUT state.
POWER-ON RESET
CONVERT
SLEEP
NO
The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is
completed once all 16 data bits have been shifted out and
the clock then goes low, which corresponds to the 16th
falling edge of SCK. Second, the DATA OUTPUT state can
be aborted at any time by a LOW-to-HIGH transition on
the CS input. Following either one of these two actions,
the LTC2450 will enter the CONVERT state and initiate a
new conversion cycle.
When the power supply voltage VCC applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
SCK = LOW
AND
CS = LOW?
DATA OUTPUT
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
Upon entering the DATA OUTPUT state, SDO outputs the
most significant bit (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this result and
it corresponds to the last completed conversion. A new
bit of data appears at the SDO pin following each falling
edge detected at the SCK input pin. The user can reliably
latch this data on every rising edge of the external serial
clock signal driving the SCK pin (see Figure 3).
Power-Up Sequence
YES
NO
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2450’s power supply
current is reduced to less than 200nA. When the chip select
input is pulled low (CS = LOW), and SCK is maintained
at a HIGH logic level, the LTC2450 will return to a normal
power consumption level. During the SLEEP state, the
result of the last conversion is held indefinitely in a static
register.
YES
2450 F02
Figure 2. LTC2450 State Transition Diagram
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2450 starts
a conversion cycle and follows the succession of states
described in Figure 2. The first conversion result following POR is accurate within the specifications of the
device if the power supply voltage VCC is restored within
the operating range (2.7V to 5.5V) before the end of the
POR time interval.
2450fa
LTC2450
Applications Information
Ease of Use
The LTC2450 data output has no latency, filter settling delay
or redundant results associated with the conversion cycle.
There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple
analog input voltages requires no special actions.
this range. Thus the converter resolution remains at 1LSB
independent of the reference voltage. INL, offset, and fullscale errors vary with the reference voltage as indicated
by the Typical Performance Characteristics graphs. These
error terms will decrease with an increase in the reference
voltage (as the LSB size in µV increases).
The LTC2450 performs offset and full-scale calibrations
every conversion. This calibration is transparent to the
user and has no effect upon the cyclic operation described
previously. The advantage of continuous calibration is
extreme stability of the ADC performance with respect to
time and temperature.
Input Voltage Range
The LTC2450 includes a proprietary input sampling scheme
that reduces the average input current several orders of
magnitude as compared to traditional delta sigma architectures. This allows external filter networks to interface
directly to the LTC2450. Since the average input sampling
current is 50nA, an external RC lowpass filter using a 1kΩ
and 0.1µF results in <1LSB error.
The converter offset and gain error specifications ensure
that all 65536 possible codes will be produced within this
voltage range. In an under-range condition, for all input
voltages less than the voltage corresponding to output
code 0, the converter will generate the output code 0.
In an over-range condition, for all input voltages greater
than the voltage corresponding to output code 65535 the
converter will generate the output code 65535.
Reference Voltage Range
The converter uses the power supply voltage (VCC) as the
positive reference voltage (see Figure 1). Thus, the reference range is the same as the power supply range, which
extends from 2.7V to 5.5V. The LTC2450’s internal noise
level is extremely low so the output peak-to-peak noise
remains well below 1LSB for any reference voltage within
t1
The ADC is capable of digitizing true rail-to-rail input signals. Ignoring offset and full-scale errors, the converter
will theoretically output an “all zero” digital result when the
input is at ground (a zero scale input) and an “all one” digital
result when the input is at VCC (a full-scale input).
Output Data Format
The LTC2450 generates a 16-bit direct binary encoded
result. It is provided, MSB first, as a 16-bit serial stream
through the SDO output pin under the control of the SCK
input pin (see Figure 3).
t3
t2
CS
D15
SDO
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
MSB
D4
D3
D2
D1
D0
LSB
SCK
2450 F02
tKQ
tlSCK
thSCK
Figure 3. Data Output Timing
2450fa
LTC2450
Applications Information
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most significant bit of the result being present
at the SDO output pin (SDO = D15) once CS goes low. A
new data bit appears at the SDO output pin following every
falling edge detected at the SCK input pin. The output data
can be latched by the user using the rising edge of SCK.
Conversion Status Monitor
For certain applications, the user may wish to monitor
the LTC2450 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 4.
Conversion status monitoring, while possible, is not required for LTC2450 as its conversion time is fixed and equal
at approximately 33.3ms (42ms maximum). Therefore,
external timing can be used to determine the completion of a
conversion cycle.
Serial Interface
The LTC2450 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
t1
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
Serial Interface Operation Modes
The following are a few of the more common interface
operation examples. Many more valid control and serial
data output operation sequences can be constructed based
upon the above description of the function of the three
digital interface pins.
The modes of operation can be summarized as follows:
1) The LTC2450 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS = ↑). Second, one can use a high-low
transition on SCK (SCK = ↓).
3) In a similar vein, at any time during the Data Output
state, pulling CS high (CS = ↑) causes the part to leave
the I/O state, abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conversion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
t2
CS
SDO
SCK = HI
CONVERT
SLEEP
2450 F03
Figure 4. Conversion Status Monitoring Mode
2450fa
LTC2450
Applications Information
Serial Clock Idle-High (CPOL = 1) Examples
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
In Figure 5, following a conversion cycle the LTC2450
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 7, following a conversion cycle the LTC2450
automatically enters the low power sleep state. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
CS is pulled low to test whether or not the chip is in
the CONVERT state. While in the CONVERT state, SDO
is HIGH while CS is LOW. In the SLEEP state, SDO is
LOW while CS is LOW. These tests are not required operational steps but may be useful for some applications.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The timing diagram in Figure 8 is identical to that of Figure 7,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
The operation example of Figure 6 is identical to that of
Figure 5, except the new conversion cycle is triggered by
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
clk2
clk3
SLEEP
clk4
clk15
clk16
DATA OUTPUT
CONVERT
2450 F05
LOW ICC
Figure 5. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of `C`S Starts a New Conversion
CS
SD0
D15
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
SLEEP
clk2
clk3
clk4
clk15
clk16
DATA OUTPUT
LOW ICC
clk17
CONVERT
2450 F06
Figure 6. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
2450fa
10
LTC2450
Applications Information
CS
SD0
D15
D14
D13
clk1
clk2
clk3
D12
D2
D1
D0
clk15
clk16
SCK
CONVERT
SLEEP
clk4 clk14
DATA OUTPUT
CONVERT
2450 F07
LOW ICC
Figure 7. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
CS
SD0
D15
D14
clk1
clk2
D13
D12
D2
D1
clk15
clk15
D0
SCK
CONVERT
SLEEP
LOW ICC
clk3
clk4
DATA OUTPUT
clk16
CONVERT
2450 F08
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Examples of Aborting Cycle using CS
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450 is in the
data output state, a CS rising edge clears the remaining data
bits from memory, aborts the output cycle and triggers a
new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
conversion operation can be triggered by pulling CS low
and then high. When CS is pulled low (CS = LOW), SDO
will output the most significant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and CS is subsequently pulled high
(CS = HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal transitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
2450fa
11
LTC2450
Applications Information
CS
D15
SD0
D14
D13
SCK
clk1
CONVERT
SLEEP
clk2
clk2
clk4
DATA OUTPUT
CONVERT
2450 F09
LOW ICC
Figure 9. Idle-High (CPOL = 1) Clock and Aborted I/O Example
CS
SD0
D15
D14
clk1
clk2
D13
SCK
CONVERT
SLEEP
DATA OUTPUT
clk3
CONVERT
LOW ICC
2450 F10
Figure 10. Idle-Low (CPOL = 0) Clock and Aborted I/O Example
CS
SD0
D15
SCK = LOW
CONVERT
SLEEP
DATA OUTPUT
CONVERT
LOW ICC
2450 F11
Figure 11. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
2450fa
12
LTC2450
Applications Information
2-Wire Operation
Figure 13 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2450 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the most significant bit
(D15) of the conversion result. The user must use external
timing in order to determine the end of conversion and
result availability. Subsequently 16 clock pulses are applied
to SCK in order to serially shift the 16-bit result. The 16th
clock falling edge triggers a new conversion cycle.
The 2-wire operation modes, while reducing the number of
required control signals, should be used only if the LTC2450
low power sleep capability is not required. In addition the
option to abort serial data transfers is no longer available.
Hardwire CS to GND for 2-wire operation.
Figure 12 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Preserving the Converter Accuracy
The LTC2450 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line and frequency
perturbations. Nevertheless, in order to preserve the
very high accuracy capability of this part, some simple
precautions are desirable.
CS = LOW
SD0
D15
D14
D13
D12
D2
D1
D0
SCK
clk1
CONVERT
clk2
clk3
SLEEP
clk4
clk15
clk16
clk17
DATA OUTPUT
CONVERT
2450 F12
Figure 12. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
CS = LOW
SD0
D15
D14
D13
D12
D2
D1
D0
clk1
clk2
clk3
clk4 clk14
clk15
clk16
SCK
CONVERT
DATA OUTPUT
CONVERT
2450 F13
Figure 13. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
2450fa
13
LTC2450
Applications Information
Digital Signal Levels
The LTC2450’s digital interface is easy to use. Its digital
inputs (SCK and CS) accept standard CMOS logic levels
and the internal hysteresis receivers can tolerate edge
rates as slow as 100µs. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signal SDO is less of a concern because
it is not active during the conversion cycle.
While a digital input signal is in the range 0.5V to VCC
–0.5V, the CMOS input receiver may draw additional
current from the power supply. Due to the nature of CMOS
logic, a slow transition within this voltage range may cause
an increase in the power supply current drawn by the
converter, particularly in the low power operation mode
within the SLEEP state. Thus, for low power consumption
it is highly desirable to provide relatively fast edges for the
two digital input pins SCK and CS, and to keep the digital
input logic levels at VCC or GND.
At the same time, during the CONVERT state, undershoot
and/or overshoot of fast digital signals connected to the
LTC2450 pins may alter the conversion result. Undershoot and overshoot can occur because of an impedance
mismatch at the converter pin combined with very fast
transition times. This problem becomes particularly difficult
when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all
transmission lines close to their characteristic impedance.
Parallel termination is seldom an acceptable option in low
power systems so a series resistor between 27W and 56W
placed near the driver may eliminate this problem. The
actual resistor value depends upon the trace impedance
and connection topology. An alternate solution is to reduce
the edge rate of the control signals, keeping in mind the
concerns regarding slow edges mentioned above.
Particular attention should be given to configurations in
which a continuous clock signal is applied to SCK pin during
the CONVERT state. While LTC2450 will ignore this signal
from a logic point of view the signal edges may create
unexpected errors depending upon the relation between
its frequency and the internal oscillator frequency. In such
a situation it is beneficial to use edge rates of about 10ns
and to limit potential undershoot to less than 0.3V below
GND and overshoot to less than 0.3V above VCC.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2450 into an unknown state if an SCK pulse is
missed or noise triggers an extra SCK pulse. In this situation, it is impossible to distinguish SDO = 1 (indicating
conversion in progress) from valid “1” data bits. As such,
CPOL = 1 is recommended for the 2-wire mode. The user
should look for SDO = 0 before reading data, and look
for SDO = 1 after reading data. If SDO does not return a
“0” within the maximum conversion time (or return a “1”
after a full data read), generate 16 SCK pulses to force a
new conversion.
Driving VCC and GND
The VCC and GND pins of the LTC2450 converter are
directly connected to the positive and negative reference
voltages, respectively. A simplified equivalent circuit is
shown in Figure 14.
The power supply current passing through the parasitic
layout resistance associated with these common pins will
modify the ADC reference voltage and thus negatively affect
the converter accuracy. It is thus important to keep the
VCC and GND lines quiet, and to connect these supplies
through very low impedance traces.
In relation to the VCC and GND pins, the LTC2450 combines internal high frequency decoupling with damping
RSW (TYP)
15k
VCC
ILEAK
VCC
VCC
VIN
ILEAK
RSW (TYP)
15k
ILEAK
CEQ (TYP)
0.35pF
VCC
ILEAK
GND
RSW (TYP)
15k
2450 F14
INTERNAL SWITCHING FREQUENCY = 4 MHz
Figure 14. LTC2450 Analog Pins Equivalent Circuit
2450fa
14
LTC2450
Applications Information
elements which reduce the ADC performance sensitivity to
PCB layout and external components. Nevertheless, the very
high accuracy of this converter is best preserved by careful
low and high frequency power supply decoupling.
layout CPAR has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 15 includes the
converter equivalent internal resistor RSW and sampling
capacitor CEQ.
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
VCC and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC
package. It is also desirable to avoid any via in the circuit
path starting from the converter VCC pin, passing through
these two decoupling capacitors and returning to the
converter GND pin. The area encompassed by this circuit
path, as well as the path length, should be minimized.
There are some immediate trade-offs in RS and CIN without
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
1) Due to the LTC2450’s input sampling algorithm, the
input current drawn by VIN over a conversion cycle is
50nA. A high RS • CIN attenuates the high frequency
components of the input current, and RS values up to
1kΩ result in <1LSB error.
2) The bandwidth from VSIG is reduced at VIN.This bandwidth reduction isolates the ADC from high frequency
signals, and as such provides simple antialiasing and
input noise reduction.
Very low impedance ground and power planes and star
connections at both VCC and GND pins are preferable. The
VCC pin should have two distinct connections: the first to the
decoupling capacitors described above and the second to
the power supply voltage. The GND pin should have three
distinct connections: the first to the decoupling capacitors
described above, the second to the ground return for the
input signal source and the third to the ground return for
the power supply voltage source.
3) Noise generated by the ADC is attenuated before it goes
back to the signal source.
4) A large CIN gives a better AC ground at VIN, helping
reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition. RS can be
easily sized such as to protect against even extreme
fault conditions.
Driving VIN
The VIN input drive requirements can be best analyzed
using the equivalent circuit of Figure 15. The input signal
VSIG is connected to the ADC input pin VIN through an
equivalent source resistance RS. This resistor includes
both the actual generator source resistance and any
additional optional resistor connected to the VIN pin. An
optional input capacitor CIN is also connected to the ADC
VIN pin. This capacitor is placed in parallel with the ADC
input parasitic capacitance CPAR. Depending upon the PCB
+
–
VCC
RSW
15k
ILEAK (TYP)
ILEAK
CEQ
0.35pF
(TYP)
VCC
RS
VSIG
There is a limit to how large RS • CIN should be for a given
application. Increasing RS beyond a given point increases
the voltage drop across RS due to the input current, to
the point that significant measurement errors exist. Additionally, for some applications, increasing the RS • CIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
VIN
CIN
CPAR
ICONV
2450 F15
Figure 15. LTC2450 Input Drive Equivalent Circuit
2450fa
15
LTC2450
Applications Information
For most applications, it is desirable to implement CIN as
a high quality 0.1µF ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the
actual VIN package pin. Furthermore the area encompassed
by this circuit path as well as the path length should be
minimized.
In the case of a 2-wire sensor which is not remotely
grounded, it is desirable to split RS and place series
resistors in the ADC input line as well as in the sensor
ground return line which should be tied to the ADC GND
pin using a star connection topology.
Figure 16 shows the measured LTC2450 INL vs Input Voltage as a function of RS value with an input
capacitor CIN = 0.1µF.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≅ 1/(2p RS CIN).
Finally, if the recommended choice for CIN is unacceptable
for the user’s specific application, an alternate strategy is to
eliminate CIN and minimize CPAR and RS. In practical terms,
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measurements, low impedance voltage source monitoring and so
on. The resultant INL vs VIN is shown in Figure 17. The
measurements of Figure 17 include a CPAR capacitor corresponding to a minimum size layout pad and a minimum
width input trace of about 1 inch length.
16
8
12
6
8
4
4
RS = 1k
INL (LSB)
INL(LSB)
In some cases, RS can be increased above these guidelines.
In the case of the LTC2450, in the first half of the CONVERT
state, the internal calibration algorithm maintains IAV
strictly at zero. Each half of the CONVERT state is about
16.67ms. Additionally, the input current is zero while the
ADC is either in sleep or I/O modes. Thus, if the time
constant of the input R-C circuit t = RS • CIN is of the
same order magnitude or longer than the time periods
between actual conversions, then one can consider the
input current to be reduced correspondingly.
0
RS = 0
–4
RS = 10k
–8
RS = 1k
0
–2
RS = 0
–4
–12
–16
2
RS = 10k
–6
0
1
2
3
INPUT VOLTAGE (V)
4
5
2450 F16
Figure 16. Measured INL vs Input Voltage,
CIN = 0.1µF, VCC = 5V, TA = 25°C
–8
0
0.5
1
1.5 2 2.5 3 3.5
INPUT VOLTAGE (V)
4
4.5
5
2450 F17
Figure 17. Measured INL vs VIN, CIN = 0, VCC = 5V, TA = 25°C
2450fa
16
LTC2450
Applications Information
Signal Bandwidth and Noise Equivalent Input
Bandwidth
The LTC2450 includes a sinc1 type digital filter with the
first notch located at f0 = 60Hz. As such the 3dB input
signal bandwidth is 26.54Hz. The calculated LTC2450
input signal attenuation with frequency at low frequencies
is shown in Figure 18.
The LTC2450 input signal attenuation with frequency over
a wide frequency range is shown in Figure 19.
The converter noise level is about 1.4µVRMS and can be
modeled by a white noise source connected at the input
of a noise free converter.
For a simple system noise analysis the VIN drive circuit can
be modeled as a single pole equivalent circuit characterized by a pole location Fi and a noise spectral density ni.
If the converter has an unlimited bandwidth or at least
a bandwidth substantially larger than Fi, then the total
noise contribution of the external drive circuit would be
Vn = ni • √π/2 • Fi. Then, the total system noise level can
be estimated as the square root of the sum of (Vn2) and
the square of the LTC2450 noise floor (≈2mV2).
Aliasing
The LTC2450 signal acquisition circuit is a sampled data
system and as such suffers from input signal aliasing. As
can be seen from Figure 19, due to the very high oversample ratios the high frequency input signal attenuation
is reasonably good. Nevertheless a continuous time
antialiasing filter connected at the input will preserve
the converter accuracy when the input signal includes
undesirable high frequency components. The antialiasing function can be accomplished using the RS and CIN
components shown in Figure 15 sized such that t = RS
• CIN > 450ns.
0
INPUT SIGNAL ATTENUATION (dB)
INPUT SIGNAL ATTENUATIOIN (dB)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
0
60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (Hz)
2450 F18
Figure 18. Input Signal Attenuation vs Frequency
(Low Frequencies)
–20
–40
–60
–80
–100
0
2.5
5.0
7.5
10.0
12.5
15.0
INPUT SIGNAL FREQUENCY (MHz)
2450 F19
Figure 19. Input Signal Attenuation vs Frequency
2450fa
17
LTC2450
Typical Application
Thermistor Measurement
5V
VCC
10k
VIN
THERMISTOR
1k TO 10k
100nF
CS
SCK
LTC2450
SDO
GND
2450 TA02
2450fa
18
LTC2450
Package Description
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
0.675 ±0.05
2.50 ±0.05
1.15 ±0.05 0.61 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.56 ± 0.05
(2 SIDES)
0.38 ± 0.05
4
6
2.00 ±0.10
(4 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER OF
EXPOSED PAD
3
0.200 REF
0.75 ±0.05
1
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2450fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2450
Typical ApplicationS
Easy Active Input
Easy Passive Input
PRECONDITIONED SENSOR
WITH VOLTAGE OUTPUT
V+
VOUT
1k
RS < 10k
LTC2450
GND
LTC2450
100nF
100nF
2450 TA04
2450 TA05
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2450fa
20 Linear Technology Corporation
LT 0707 REV A • PRINTED IN USA
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