Cypress CY7C1061AV25-10BAC 1m x 16 static ram Datasheet

CY7C1061AV25
PRELIMINARY
1M x 16 Static RAM
Features
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
• High speed
— tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 2.5 ± 0.2V
• 1.5V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
Reading from the device is accomplished by enabling the chip
by taking CE1 LOW and CE2 HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
Functional Description
The CY7C1061AV25 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH / CE2 LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1061AV25 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Pin Configuration
Logic Block Diagram
TSOP II (Top View)
I/O12
VCC
I/O13
I/O14
VSS
I/O15
A4
A3
A2
A1
A0
BHE
CE1
VCC
WE
CE2
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
I/O2
VSS
I/O3
1M x 16
ARRAY
4096 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0–I/O7
I/O8–I/O15
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
COLUMN
DECODER
BHE
WE
CE2
CE1
OE
BLE
1
2
3
4
54
53
52
51
5
6
50
49
7
8
9
10
48
47
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O11
VSS
I/O10
I/O9
VCC
I/O8
A5
A6
A7
A8
A9
NC
OE
VSS
DNU (Do Not Use)
BLE
A10
A11
A12
A13
A14
I/O7
VSS
I/O6
I/O5
VCC
I/O4
Selection Guide
-8
-10
-12
Unit
8
10
12
ns
Commercial
300
275
260
mA
Industrial
300
275
260
Commercial/Industrial
50
50
50
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 38-05331 Rev. **
•
3901 North First Street
•
mA
San Jose, CA 95134
•
408-943-2600
Revised January 27, 2003
CY7C1061AV25
PRELIMINARY
Pin Configurations
48-ball FBGA
2
BLE
OE
A0
I/O8
BHE
I/O9
I/O10
5
6
A1
A2
CE2
A
A3
A4
CE1
I/O0
B
A5
A6
I/O1
I/O2
C
VSS
I/O11 A17
A7
I/O 3 VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15 DNU
A12
A13
WE
I/O7
G
A9
A10
A11
A19
H
A18
Document #: 38-05331 Rev. **
(Top View)
4
3
1
A8
Page 2 of 11
CY7C1061AV25
PRELIMINARY
Maximum Ratings
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +3.6V
Commercial
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
2.5V ± 0.2V
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
-8
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –1.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 1.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
-10
2.0
2.0
0.4
GND < VI < VCC
IOZ
Output Leakage Current GND < VOUT < VCC, Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX =
1/tRC
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 <= VIL
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 <= 0.2V
Max. VCC,
CE > VCC – 0.2V,
VIN > VCC – 0.2V,
or VIN < 0.2V, f = 0
-12
Min. Max. Min. Max. Min. Max. Unit
Industrial
Commercial/
Industrial
0.4
V
0.4
V
V
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
–1
+1
µA
+1
–1
+1
–1
–1
Commercial
2.0
300
275
+1
µA
260
mA
300
275
260
mA
100
100
100
mA
50
50
50
mA
Capacitance[2]
Parameter
CIN
Package
Z54
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 2.5V
BA48
COUT
Z54
I/O Capacitance
BA48
Max.
Unit
6
pF
8
pF
8
pF
10
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05331 Rev. **
Page 3 of 11
CY7C1061AV25
PRELIMINARY
AC Test Loads and Waveforms[3]
50Ω
VTH = VDD/2
OUTPUT
Z0 = 50Ω
OUTPUT
30 pF*
(a)
R1 1667 Ω
2.5V
R2
1538Ω
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
* Capacitive Load consists of all components of the test environment.
ALL INPUT PULSES
2.5V
90%
90%
10%
GND
10%
Fall time:
> 1V/ns
Rise time > 1V/ns
(c)
AC Switching Characteristics Over the Operating Range [4]
-8
Parameter
Description
Min.
-10
Max.
Min.
-12
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the first access[5]
1
1
1
ms
tRC
Read Cycle Time
8
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW/CE2 HIGH to Data Valid
8
10
12
ns
tDOE
OE LOW to Data Valid
5
5
6
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[6]
8
3
10
3
1
1
5
Low-Z[6]
tLZCE
CE1 LOW/CE2 HIGH to
tHZCE
CE1 HIGH/CE2 LOW to High-Z[6]
Power-up[7]
tPU
CE1 LOW/CE2 HIGH to
tPD
CE1 HIGH/CE2 LOW to Power-down[7]
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
3
3
3
0
8
0
5
1
5
ns
ns
12
ns
6
ns
1
5
ns
ns
6
10
5
1
ns
6
5
ns
ns
1
5
5
0
12
3
ns
6
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1 LOW / CE2 HIGH to Write End
6
7
8
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.5V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 2.5V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05331 Rev. **
Page 4 of 11
CY7C1061AV25
PRELIMINARY
AC Switching Characteristics Over the Operating Range (continued)[4]
-8
Parameter
Description
Min.
-10
Max.
Min.
-12
Max.
Min.
Max.
Unit
tAW
Address Set-up to Write End
6
7
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
ns
tSD
Data Set-up to Write End
5
5.5
6
ns
tHD
Data Hold from Write End
0
0
0
ns
[6]
tLZWE
WE HIGH to Low-Z
tHZWE
WE LOW to High-Z[6]
3
tBW
Byte Enable to End of Write
3
5
6
3
5
7
ns
6
8
ns
ns
Data Retention Waveform
DATA RETENTION MODE
2.3V
VCC
VDR > 1.5V
2.3V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH.
11. WE is HIGH for Read cycle.
Document #: 38-05331 Rev. **
Page 5 of 11
CY7C1061AV25
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
IICC
CC
50%
50%
ISB
[13, 14, 15]
Write Cycle No. 1 (CE Controlled)
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
DATAI/O
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
14. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.
Document #: 38-05331 Rev. **
Page 6 of 11
CY7C1061AV25
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Write Cycle No.3 (WE Controlled, OE LOW)
[13, 14, 15]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05331 Rev. **
Page 7 of 11
CY7C1061AV25
PRELIMINARY
Truth Table
CE1
CE2
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
X
L
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
H
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
H
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
H
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
H
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
H
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
H
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
8
10
12
Ordering Code[16]
CY7C1061AV25-8ZC
CY7C1061AV25-8ZI
CY7C1061AV25-8BAC
CY7C1061AV25-8BAI
CY7C1061AV25-10ZC
CY7C1061AV25-10ZI
CY7C1061AV25-10BAC
CY7C1061AV25-10BAI
CY7C1061AV25-12ZC
CY7C1061AV25-12ZI
CY7C1061AV25-12BAC
CY7C1061AV25-12BAI
Package
Name
Z54
BA48
Z54
BA48
Z54
BA48
Package Type
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
Operating Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Note:
16. Contact a Cypress Representative for availability of the 48-ball Mini BGA (BA48) package.
Document #: 38-05331 Rev. **
Page 8 of 11
PRELIMINARY
CY7C1061AV25
Package Diagrams
54-lead Thin Small Outline Package, Type II Z54-II
51-85160-**
Document #: 38-05331 Rev. **
Page 9 of 11
PRELIMINARY
CY7C1061AV25
Package Diagrams (continued)
48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G
51-85162-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05331 Rev. **
Page 10 of 11
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1061AV25
Document History Page
Document Title: CY7C1061AV25 1M x 16 Static RAM
Document Number: 38-05331
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
119624
01/30/03
DFP
Document #: 38-05331 Rev. **
Description of Change
New Data Sheet
Page 11 of 11
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