Anpec APA2057ARI-TRL 2.4w stereo audio power amplifier (with gain setting) & capfree headphone driver Datasheet

APA2057A
2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver
Features
•
General Description
Operating Voltage
The APA2057A is a monolithic integrated circuit, which
combines a stereo power amplifier and a stereo output
capacitor-less headphone amplifier. The stereo power
amplifier provides 19-steps gain setting for flexible
application. The headphone amplifier is ground-reference output, and no need the output capacitors for DC
blocking. The advantages of eliminating the output capacitor are saving the cost, PCB’s space and component
height.
– HVDD= 3.0~3.6V
•
•
•
– VDD= 4.5~5.5V
No Output Capacitor at Headphone Amplifier
Required
Meeting VISTA Requirement
Low Distortion
AMP mode
– THD+N=56dB, at VDD = 5V, RL = 4Ω, PO=1.5W
– THD+N=64dB, at VDD = 5V, RL = 8Ω, PO=0.9W
•
•
•
•
•
•
•
•
Both the de-pop circuitry and the thermal shutdown
protection circuitry are integrated in the APA2057A,
which reduces pops and clicks noise during power on/
off and in shutdown mode. Thermal shutdown protects
the chip from being destroyed by over-temperature
failure. To simplify the audio system design in notebook
computer applications, the APA2057A provides the internal gain setting, and these features can minimize
components and PCB area.
HP mode
– THD+N=73dB, at HVDD=3.3V, RL=16Ω
PO=125mW
– THD+N=77dB, at HVDD=3.3V, RL=32Ω,
PO=88mW
– THD+N=85dB, at HVDD=3.3V, RL=10kΩ,
VO=1.7Vrms
The APA2057A is available in both TSSOP-28P and
TQFN5x5-28 packages. Both packages are characterized by space saving and thermal efficiency.
Output Power at 1% THD+N
– 1.9W, at VDD = 5V, AMP mode, RL = 4Ω
– 1.2W, at VDD = 5V, AMP mode, RL = 8Ω
at 10% THD+N
–2.4W at VDD = 5V, AMP mode, RL = 4Ω
–1.5W at VDD = 5V, AMP mode, RL = 8Ω
Applications
•
•
Depop Circuitry Integrated
Internal 19-steps Gain Setting for Flexible Application
Note book PCs
LCD monitor
Thermal Shutdown Protection and Over Current
Protection Circuitry
High Supply Voltage Ripple Rejection
Surface-Mount Packaging
– TSSOP-28P (with enhanced thermal pad)
– TQFN5x5-28 (with enhanced thermal pad)
Lead Free Available (RoHS Compliant)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
1
www.anpec.com.tw
APA2057A
Ordering and Marking Information
Package Code
R : TSSOP-28P
QB : TQFN5x5-28
Operating Ambient Temperature Range
I : -40 to 85 ° C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
APA2057A
Lead Free Code
Handling Code
Temperature Range
Package Code
APA2057A R :
APA2057A QB :
APA2057A
XXXXX
XXXXX - Date Code
XXXXX - Date Code
APA2057A
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully
compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
22 SET
24 BEEP
23 AMP_EN
26 SET
INR_H 4
25 BIAS
INL_A 5
24 HP_EN
INL_H 6
23 PGND
PGND 7
22 ROUT+
LOUT+ 8
25 VDD
27 AMP_EN
INR_A 3
26 GND
28 BEEP
27 INR_A
VDD 1
GND 2
28 INR_H
Pin Configurations
APA2057A
INL_A 1
21 BIAS
INL_H 2
20 HP_EN
PGND 3
19 PGND
LOUT+ 4
21 ROUT-
18 ROUT+
APA2057A
CVDD 7
15 HVDD
CP+ 12
17 HP_R
CGND 13
16 HVSS
CP- 14
15 CVSS
(TSSOP-28P)
17 ROUT-
HP_L 14
HP_R 13
18 HP_L
HVSS 12
16 PVDD
CVDD 11
CVSS 11
PVDD 6
CP- 10
19 HVDD
CP+ 8
20 PVDD
PVDD 10
CGND 9
LOUT- 9
LOUT- 5
(TQFN5x5-28)
(Top view)
(Top view)
= ThermalPad (connected the ThermalPad to GND plane for better heat dissipation)
Absolute Maximum Ratings (Note 1)
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VDD
HVDD,
VSS
VSET, VAMP_EN, VHP_EN
Parameter
Rating
Supply Voltage (PVDD, CVDD, VDD)
Supply Voltage (HVDD)
Supply Voltage (VSS)
+0.3 to -6
Input Voltage
V
V
0 to VDD+0.3V
TA
Operating Ambient Temperature Range
TJ
Maximum Junction Temperature
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
-0.3 to 6
Unit
2
-40 to 85
°C
150
°C
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APA2057A
Absolute Maximum Ratings (Cont.)
(Note 1)
(Over operating free-air temperature range unless otherwise noted.)
Symbol
Parameter
Rating
Unit
TSTG
Storage Temperature Range
-65 to +150
°C
TSDR
Maximum Lead Soldering Temperature
260, 10 seconds
°C
Power Dissipation
Internally Limited
W
PD
Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
(Note 2)
Parameter
Value
Thermal Resistance - Junction to Ambient (Note 2)
TSSOP-28P
TQFN5x5-28
θJA
Unit
o
45
43
C/W
Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TSSOP-28P & TQFN-28
packages with solder on the printed circuit board.
Recommended Operating Conditions
Supply voltage, VDD
Supply voltage, HVDD
High level threshold voltage, VIH
AMP_EN, HP_EN
Low level threshold voltage, VIL
AMP_EN, HP_EN
Common mode input voltage, Vicm
Min.
Max.
Unit
4.5
5.5
V
3.0
3.6
V
for Amplifier
for Headphone Amplifier
Shutdown
Input Voltage (VSET)
V
2
0.8
V
VDD-1
V
HVDD-1
V
0.8
Gain Setting
Fix Gain
2
4.2
V
4.5
V
Electrical Characteristics
VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).
Symbol
VDD
HVDD
Parameter
Test Condition
APA2057A
Min.
Typ.
Max.
Supply Voltage
4.5
5.5
V
Headphone Amplifier
supply voltage
3.0
3.6
V
VDD Supply Current
Only Speaker mode,
17.5
IHVDD
HVDD Supply Current
AMP_EN = HP_EN = 0V
0.15
1
IVDD
VDD Supply Current
Only Headphone mode,
12
20
IHVDD
HVDD Supply Current
HP_EN = AMP_EN = 5V
3
5
IVDD
VDD Supply Current
35
HVDD Supply Current
All Enable, HP_EN=5V and
AMP_EN = 0V
20
IHVDD
3
5
IVDD
Unit
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
3
29
mA
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APA2057A
Electrical Characteristics (Cont.)
VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).
Symbol
Parameter
Test Condition
APA2057A
Min.
Typ.
Max.
50
90
1
10
ISD(HVDD)
HVDD Shutdown Current
ISD(VDD)
VDD Shutdown Current
IAMP_EN
Input current
AMP_EN
1
IHP_EN
Input current
HP_EN,
10
Output Power
THD+N =1%, Fin =1KHz
RL =4Ω
RL =8Ω
THD+N =10%, Fin =1KHz
RL =4Ω
RL =8Ω
SET = 0V
Unit
µA
µA
15
µA
Speaker mode
PO
VOS
THD+N
X’talk
PSRR
Output Offset Voltage
RL =8Ω, Gain =10.5dB
Total Harmonic Distortion
plus Noise
Fin =1KHz
PO = 1.5W, RL =4Ω
PO = 0.9W, RL =8Ω
Channel Separation
Power Supply Rejection
Ratio
S/N
Vn
Noise Output Voltage
1.0
1.9
1.2
1.3
2.4
1.5
W
10
0.15
0.06
mV
%
Fin =1KHz, CB=2.2µF, RL=8Ω, PO=0.92W
80
Fin =1KHz, CB=2.2µF, RL =4Ω, PO=1.5W
83
CB =2.2µF, RL =8Ω, Fin =120Hz
70
dB
PO =0.8W, RL =8Ω, A-weighted Filter
90
dB
Gain =10.5dB, RL =8Ω, CB =2.2µF
80
µV
(rms)
dB
Headphone mode
Po
Output Power
THD+N = 1%, Fin =1KHz
RL = 16Ω
RL = 32Ω
THD+N = 10%, Fin =1KHz
RL =16Ω
RL =32Ω
Vo
Output Voltage Swing
RL =10KΩ
Vos
Output Offset Voltage
RL =32Ω
100
160
120
150
200
165
THD+N=10%
2.9
THD+N=1%
2.4
mW
Vrms
-10
+10
mV
Fin = 1KHz
THD+N
X’talk
PSRR
Total Harmonic Distortion
plus Noise
Channel Separation
Power Supply Rejection
Ratio
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
PO = 125mW, RL =16Ω
PO = 88mW, RL =32Ω
0.02
0.02
VO=1.7Vrms, RL=10kΩ
0.005
Fin =1KHz, RL =16Ω, PO =125mW
80
Fin =1KHz, RL =32Ω, PO =88mW
85
Fin =1KHz, RL=10KΩ, VO =1.7Vrms
105
CB = 2.2µF, RL=32Ω, Fin =120Hz
80
4
%
dB
dB
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APA2057A
Electrical Characteristics (Cont.)
VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).
Symbol
Parameter
Test Condition
APA2057A
Min.
Typ.
Max.
Unit
Headphone mode (Cont.)
With A-weighted Filter
S/N
PO = 70mW, RL =32Ω
95
VO =1.2Vrms, RL=10kΩ
92
CB =2.2µF
30
dB
µV
(rms)
Vn
Noise Output
Voltage
Rf
Input Feedback
Resistance
38
40
42
kΩ
Fosc
Switching frequency
460
540
620
KHz
CVSS
Charge Dump
Output Voltage
(CVSS)
Req
Charge pump
requirement
resistance
9
Beep trigger level
3
VPP
Beep response time
4
ms
115
dB
RL = 10KΩ, VO = 1.1Vrms, Fin = 1KHz
85
dB
RL = 8Ω, VO = 2Vrms, Fin = 1KHz
112
dB
RL = 4Ω, VO = 2Vrms, Fin = 1KHz
112
dB
90
dB
100
dB
85
dB
80
dB
120
msec
Charge Pump
-0.98
VDD
No load
V
12
Ω
Beep
Vbeep
TRES
Attenuation
Att(HP_EN)
Att(AMP_EN)
HP disable
attenuation
AMP disable
attenuation
Att_SD(HP_EN)
Shutdown active
Att_SD(AMP_EN)
Shutdown active
RL = 32Ω, VO = 1.1Vrms, Fin = 1KHz
RL = 10KΩ on the Headphone Mode,
VO = 1.1Vrms, Fin = 1KHz
RL = 8Ω on the AMP Mode, VO = 1Vrms,
Fin = 1KHz
Headphone to Speaker Crosstalk
AMP_EN = 0V, RL = 8Ω
X’talk
Channel Separation
HP_EN = 5V, RL = 16Ω, Fin = 1KHz,
PO = 125mW
Speaker to Headphone Crosstalk
HP_EN = 5V, RL = 10KΩ
X’talk
Channel Separation
AMP_EN = 0V, RL = 4Ω, Fin = 1KHz,
PO = 1.5W
Amplifier Start up Time
Tstart-up
Start up time
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
5
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APA2057A
Gain Setting Table _AMP Mode
(VDD=5V)
Input Voltage (V SET )
Gain (dB)
Hysteresis (mV)
Recommended Voltage
(V)
Low (V)
H igh (V)
-70
0
2.00
SD
0.00
-7
2.04
2.12
47
2.08
-5
2.15
2.24
36
2.20
-3
2.28
2.35
41
2.31
-1
2.39
2.47
41
2.43
1
2.51
2.58
35
2.54
3
2.62
2.70
41
2.66
4
2.74
2.81
48
2.78
5
2.86
2.92
43
2.89
6
2.97
3.04
47
3.01
7
3.09
3.15
45
3.12
8
3.21
3.27
54
3.24
9
3.33
3.39
59
3.36
10
3.45
3.51
64
3.48
11
3.56
3.62
53
3.59
12
3.68
3.73
59
3.70
13
3.80
3.85
66
3.82
14
3.92
3.96
69
3.94
15
4.02
4.07
64
4.05
16
4.15
4.17
76
4.16
10.5
4.26
5.00
94
5.00
Recommend Resistance’s Value for Gain Setting
Gain (dB)
R1 (1%)
-70
10K
0
-7
18K
13K
-5
20K
16K
-3
18K
16K
-1
16K
15K
1
15K
16K
3
13K
15K
4
24K
30K
5
13K
18K
6
13K
20K
7
13K
22K
8
16K
30K
9
13K
27K
10
13K
30K
11
15K
39k
12
13K
39K
13
13K
43K
14
13K
50K
15
15K
68K
16
13K
68K
10.5
10K
>90K
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
6
R# (1%)
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APA2057A
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
VDD =5V
Fin=1KHz
Cin=2.2µF
BW<80KHz
AMP mode
VDD =5V
RL=4Ω
Cin=2.2µF
BW<80KHz
AMP mode
RL=8Ω
1
THD+N (%)
THD+N (%)
10
RL=4Ω
1
Fin=20KHz
Fin=20Hz
0.1
Fin=1KHz
0.05
0
0.5
1
1.5
2
2.5
0.1
0.01
3
0.1
Output Power (W)
5
Crosstalk vs. Frequency
+0
VDD =5V
RL=4Ω
Cin=2.2µF
PO=1.5W
BW<80KHz
AMP mode
-10
-20
-30
Crosstalk (dB)
THD+N (%)
2
Output Power (W)
THD+N vs. Frequency
10
1
1
VDD =5V
RL=4Ω
Cin=2.2µ
uF
PO=1.5W
AMP mode
-40
-50
-60
Right to Left
-70
Left to Right
-80
Right Channel
-90
Left Channel
0.1
20
100
1k
-100
20
10k 20k
100
Frequency (Hz)
10k 20k
1k
Frequency (Hz)
Output Noise Voltage vs. Frequency
Frequency Response
100µ
+11
+30
+25
10µ
+9
+8
Phase
+20
+15
+10
+5
VDD =5V
RL=4Ω
Cin=2.2µF
A-weighted
AMP mode
1µ
20
VDD =5V
Cin =2.2µF
RL=4Ω
PO=0.2W
AMP mode
Phase (deg)
+10
Gain (dB)
Output Noise Voltage (Vrms)
Gain
+7
+0
100
1k
+6
10
10k 20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
100
1k
10k
-5
100k 200k
Frequency (Hz)
7
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APA2057A
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
VDD =5V
RL=8Ω
Cin=2.2µF
BW<80KHz
AMP mode
THD+N (%)
THD+N (%)
10
1
Fin=20KHz
0.1
Fin=20Hz
VDD =5V
RL=8Ω
Cin=2.2µF
PO=0.92W
BW<80KHz
AMP mode
1
Left Channel
0.1
Fin=1KHz
Right Channel
0.05
0.01
0.1
0.05
20
5
1
100
Output Power (W)
Crosstalk vs. Frequency
Output Noise Voltage vs. Frequency
VDD =5V
RL=8 Ω
Cin=2.2µF
PO=0.92W
AMP mode
Output Noise Voltage (Vrms)
-20
Crosstalk (dB)
-30
-40
-50
-60
-70
Left to Right
-80
Right to Left
10µ
VDD =5V
RL=8Ω
Cin=2.2µF
A-weighted
AMP mode
-90
-100
20
1µ
100
10k 20k
1k
20
Frequency (Hz)
Frequency Response
Crosstalk vs. Frequency
+11
+0
+30
Gain
-10
+25
-20
-30
+20
+15
+10
+8
Crosstalk (dB)
VDD =5V
Cin =2.2µF
RL=8Ω
PO=0.13W
AMP mode
Phase (deg)
Gain (dB)
+10
+9
+5
1k
10k
-70
Right(AMP) to Right(HP)
Left(AMP) to Left(HP)
Left(AMP) to Right(HP)
-80
-110
-120
20
-5
100k 200k
Right(AMP) to Left(HP)
100
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
-50
-60
-100
+0
100
-40
VDD =5V
RL=4Ohm (AMP)
RL=10KΩ(HP)
Cin=2.2µF (AMP)
PO=1.5W(AMP)
AMP (active) mode
HP Mode
-90
Phase
+7
10k 20k
1k
100
Frequency (Hz)
+6
10
10k 20k
100µ
+0
-10
1k
Frequency (Hz)
8
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APA2057A
Typical Operating Characteristics (Cont.)
AMP Attenuation vs. Frequency
AMP Attenuation vs. Frequency
+0
AMP Attenuation (dB)
-20
-30
VDD =5V
RL=4Ω
Cin=2.2µF
VO=2Vrms(F in=1KHz, AMP enable)
AMP mode (disable)
-20
-40
-50
-60
-70
-80
-90
-100
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
20
VDD =5V
RL=8Ω
Cin=2.2µF
VO=2Vrms(Fin=1KHz,AMP enable)
AMP mode (disable)
-10
AMP Attenuation (dB)
-10
+0
-110
1k
100
-120
10k 20k
20
Frequency (Hz)
Shutdown Attenuation vs. Frequency
-20
-30
-40
Shutdown Attenuation vs. Frequency
+0
VDD =5V
VDD =5V
RL=4Ω
Cin=2.2µF
VO=1Vrms(F in=1KHz)
Shutdown active
AMP mode
Shutdown Attenuation (dB)
Shutdown Attenuation (dB)
+0
-10
-50
-60
-70
-80
-90
-100
-10 R =8Ω
L
-20 Cin=2.2µF
VO=1Vrms(F in=1KHz)
-30 Shutdown active
-40
AMP mode
-50
-60
-70
-80
-90
-100
-110
-110
-120
20
100
1k
-120
20
10k 20k
100
Input Voltage vs. Output Voltage
Input Voltage vs. Output Voltage
4
3.5
VDD =5V
RL=4Ω
Cin=2.2µF
Fin=1KHz
AMP mode
3.5
Output Voltage (Vrms)
Output Voltage (Vrms)
2.5
2
1.5
1
3
VDD =5V
RL=8Ω
Cin=2.2µF
Fin=1KHz
AMP mode
2.5
2
1.5
1
0.5
0.5
0
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
3
10k 20k
1k
100
Frequency (Hz)
0.3
0.6
0.9
1.2
0
1.5
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
0.3
0.6
0.9
1.2
1.5
Input Voltage (Vrms)
Input Voltage (Vrms)
9
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APA2057A
Typical Operating Characteristics (Cont.)
THD+N vs. Output Voltage
THD+N vs. Output Power
10 T
10
VDD =5V
HVDD=3.3V
RL=16Ω
Rin=39KΩ
Cin=3.3µF
BW<80KHz
HP mode
RL=300Ω
1
THD+N (%)
THD+N (%)
VDD =5V
HVDD=3.3V
Fin=1KHz
Cin=3.3µF
1 BW<80KHz
HP mode
RL=32Ω
0.1
RL=16Ω
Fin=20KHz
0.1
0.01
Fin=20Hz
RL=10KΩ
0.001
0
0.5
1
1.5
2
Fin=1KHz
0.01
1m
3
2.5
10m
Output Voltage (Volt)
100m
300m
Output Power (W)
THD+N vs. Output Power
THD+N vs. Frequency
10
10
VDD=5V
HVDD=3.3V
RL=16Ω
Rin=39KΩ
Cin=3.3µF
Fin=1KHz
BW<80KHz
HP mode
1
THD+N (%)
THD+N (%)
1
Stereo, in phase
0.1
VDD =5V
HVDD=3.3V
RL=16Ω
Rin=39KΩ
Cin=3.3µF
PO=125mW
HP mode
BW<80KHz
0.1
Stereo, 180O
out of phase
BW<22KHz
0.01
Mono
0.01
0
50m
100m
150m
200m
0.005
20
250m
100
Output Power (W)
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
VDD=5V
-10 HVDD=3.3V
RL=16Ω
Crosstalk (dB)
-20 Rin=39KΩ
Cin=3.3µF
-30 PO=125mW
HP mode
-40
-50
-60
-70
Right to Left
-80
Left to Right
-90
-100
20
100
1k
100µ
Right channel
Left channel
10µ
1µ
20
10k 20k
VDD =5V
HVDD =3.3V
RL=16Ω
Rin=39KΩ
Cin=3.3µF
A-wighted
HP mode
100
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
10k 20k
Frequency (Hz)
Crosstalk vs. Frequency
+0
1k
10
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APA2057A
Typical Operating Characteristics (Cont.)
Frequency Response
THD+N vs. Output Power
+0.2
+180
VDD=5V
HVDD=3.3V
RL=16Ω
Rin=39KΩ
Cin=3.3µF
PO=28mW
HP mode
-0.1
-0.2
10
1
THD+N (%)
Phase
-0
VDD=5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
BW<80KHz
HP mode
+185
Gain
Phase (deg)
+0.1
Gain(dB)
10
+190
Fin=20KHz
0.1
+175
Fin=20Hz
Fin=1KHz
1k
100
0.01
1m
+170
100k 200k
10k
Output Power (W)
Frequency (Hz)
THD+N (%)
1
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
Fin=1KHz
BW<80KHz
HP mode
1
THD+N (%)
10
Stereo, 180O
out of phase
0.1
100m 200m
10m
Stereo, in phase
VDD=5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
PO=88mW
HP mode
0.1
BW<80KHz
BW<22KHz
0.01
Mono
0.01 0
50m
100m
0.001
20
200m
150m
100
Output Power (W)
Crosstalk vs. Frequency
-30
100µ
VDD=5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
PO=88mW
HP mode
Output Noise Voltage (V)
Crosstalk (dB)
-20
-40
-50
-60
-70
Right to Left
-80
Right channel
Left channel
10µ
Left to Right
-90
-100
20
10k 20k
Output Noise Voltage vs. Frequency
+0
-10
1k
Frequency (Hz)
100
1k
1µ
20
10k 20k
100
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
VDD =5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
A-wighted
HP mode
11
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APA2057A
Typical Operating Characteristics (Cont.)
Frequency Response
+0.2
10
+185
1
+180
VDD =5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
PO=13mW
HP mode
-0.1
VDD=5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3.3µF
BW<80KHz
HP mode
0.1
Fin=20KHz
Fin=20Hz
0.01
+175
Fin=1KHz
-0.2
10
THD+N (%)
Phase
-0
Phase (deg)
+0.1
Gain (dB)
THD+N vs. Output Voltage
+190
Gain
100
1k
10k
0.001
+170
100k 200k
0
0.5
Frequency (Hz)
THD+N vs. Frequency
2
2.5
3
Crosstalk vs. Frequency
+0
10
VDD=5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3.3µF
VO=1.7Vrms
BW<80KHz
HP mode
-10
-20
-30
-40
Crosstalk (dB)
1
THD+N (%)
1.5
1
Output Voltage (Vrms)
0.1
-50
-60
-70
-80
Right to Left
-90
Right Channel
0.01
VDD=5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3.3µF
VO=1.7Vrms
BW<80KHz
HP mode
-100
Left Channel
0.001
-110
-120
20
100
1k
10k 20k
Left to Right
20
100
Frequency (Hz)
Frequency Response
Output Noise Voltage vs. Frequency
100µ
+195
+0.4
+0.2
Left channel
10µ
1µ
20
VDD =5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3.3µF
A-wighted
HP mode
+190
VDD =5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3.3µF
VO=240mVrms
HP mode
+0
+185
Phase (deg)
Gain
Right channel
Gain (dB)
Output Noise Voltage (Vrms)
10k 20k
1k
Frequency (Hz)
Phase
-0.2
100
1k
10k
-0.4
20k
10
100
1k
+175
100k 200k
10k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
+180
12
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APA2057A
Typical Operating Characteristics (Cont.)
THD+N vs. Output Voltage
THD+N (%)
1
THD+N vs. Frequency
10
VDD =5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
BW<80KHz
HP mode
VDD =5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
VO=1.7Vrms
BW<80KHz
HP mode
1
THD+N (%)
10
0.1
Fin=20Hz
Right channel
0.01
Fin=20KHz
0.01
0.1
Left channel
Fin=1KHz
0.001
0
0.5
1.5
1
2
2.5
0.001
20
3
100
Output Voltage (Volt)
Crosstalk vs. Frequency
+0
-10
Output Noise Voltage vs. Frequency
-40
-50
Output Noise Voltage (Vrms)
Crosstalk (dB)
-30
-60
-70
-80
Left to Right
-90
-100
Right to Left
-110
Right channel
Left channel
10µ
VDD=5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
A-wighted
HP mode
-120
-130
20
100
1k
1µ
10k 20k
20
100
Frequency (Hz)
+195
+0
-10
Gain
-20
+185
Crosstalk (dB)
+190
Phase (deg)
VDD=5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
VO=240mVrms
HP mode
+0
Phase
-0.2
10k 20k
Crosstalk vs. Frequency
Frequency Response
+0.2
1k
Frequency (Hz)
+0.4
Gain (dB)
10k 20k
100µ
VDD=5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
VO=1.7Vrms
BW<80KHz
HP mode
-20
1k
Frequency (Hz)
-30
-40
-50
-60
-70
+180
VDD =5V
HVDD=3.3V
RL=16Ω (HP)
RL=8Ω(AMP)
Rin=39KΩ(HP)
Cin=3.3µF (HP)
PO=125mW(HP)
AMP (active) mode
HP Mode
Left (HP) to Left (AMP)
Right (HP) to Left (AMP)
-80
-90
-0.4
10
100
1k
10k
+175
100k 200k
-100
20
100
Right (HP) to Right (AMP)
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
Left (HP) to Right (AMP)
13
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APA2057A
Typical Operating Characteristics (Cont.)
HP attenuation vs. Frequency
+0
-20
-30
VDD =5V
HVDD=3.3V
RL=10KΩ
Cin=3.3µF
VO=1Vrms(F in=1KHz HP enable)
HP mode (disable)
-10
-20
HP attenuation (dB)
-10
HP attenuation (dB)
HP attenuation vs. Frequency
+0
VDD =5V
HVDD=3.3V
RL=32Ω
Cin=3.3µF
VO=1Vrms(Fin=1KHz HP enable)
HP mode (disable)
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-110
Right channel
-100
20
1k
100
20
10k 20k
Frequency (Hz)
VDD =5V
HVDD=3.3V
RL=32Ω
Cin=3.3µF
VO=1Vrms(Fin=1KHz)
Shutdown active
HP mode
-30
-40
-50
-20
-60
-70
-80
-90
-100
Left channel
-110
-120
-30
-40
-50
-60
-70
-80
Left channel
-90
-100
-110
Right channel
-120
-130
Right channel
-130
-140
20
100
10k 20k
1k
20
1k
100
Frequency (Hz)
10k
20k
Frequency (Hz)
Input Voltage vs. Output Voltage
Input Voltage vs. Output Voltage
3
VDD =5V
HVDD=3.3V
RL=16Ω
Rin=39KΩ
Cin=3µF
Fin=1KHz
HP mode
2
Mono
Output Voltage (Vrms)
2.5
Stereo, in
phase
1.5
1
0.5
0
20k
VDD =5V
HVDD=3.3V
RL=10KΩ
Cin=3.3µF
VO=1Vrms(Fin=1KHz)
Shutdown active
HP mode
-10
Shutdown attenuation (dB)
-20
10k
Shutdown attenuation vs. Frequency
+0
-10
1k
100
Frequency (Hz)
Shutdown attenuation vs. Frequency
+0
Output Voltage (Vrms)
Left channel
-90
-120
Shutdown attenuation (dB)
Right channel
Left channel
-100
VDD =5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3µF
Fin=1KHz
HP mode
2.5
2
Mono
Stereo, in
phase
1.5
1
0.5
0
0.5
1
1.5
2
0
2.5
0.5
1
1.5
2
2.5
3
Input Voltage (Vrms)
Input Voltage (Vrms)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
0
14
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APA2057A
Typical Operating Characteristics (Cont.)
Input Voltage vs. Output Voltage
Output Voltage (Vrms)
2.5
2
Input Voltage vs. Output Voltage
3
VDD =5V
HVDD=3.3V
RL=300Ω
Rin=39KΩ
Cin=3µF
Fin=1KHz
HP mode
2.5
Stereo,
in phase
1.5
1
0.5
0
VDD =5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3µF
Fin=1KHz
HP mode
Mono
Output Voltage (Vrms)
3
2
Mono &
Stereo, in phase
1.5
1
0.5
0
0.5
1
1.5
2
2.5
0
3
0
0.5
1
Input Voltage (Vrms)
PSRR vs. Frequency
VDD=5V
-10 RL=4Ω
-10
Cin=2.2µF
-20 Vrr=200mVrms
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
AMP mode
-50
-60
Right channel
-50
-60
Right channel
100
1k
Left channel
-90
Vrr: Ripple Voltage on VDD
-100
20
-100
10k 20k
Vrr: Ripple Voltage on VDD
20
100
Frequency (Hz)
PSRR vs. Frequency
PSRR vs. Frequency
+0
VDD =5V
HVDD=3.3V
RL=32Ω
Rin=39KΩ
Cin=3.3µF
Vrr=200mVrms
HP mode
-10
-20
PSRR (dB)
PSRR (dB)
-30
-40
-50
-60
-70
-30
VDD =5V
HVDD=3.3V
RL=10KΩ
Rin=39KΩ
Cin=3.3µF
Vrr=200mVrms
HP mode
-40
-50
-60
-70
Left channel
-80
-90
-100
10k 20k
1k
Frequency (Hz)
-20
3
VDD =5V
RL=8Ω
Cin=2.2µF
Vrr=200mVrms
AMP mode
-80
Left channel
-90
-10
2.5
-70
-80
+0
2
PSRR vs. Frequency
+0
+0
-70
1.5
Input Voltage (Vrms)
Right channel
20
100
Left channel
-80
-90
Vrr: Ripple Voltage on HVDD
1k
Right channel
-100
10k 20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
20
100
Vrr: Ripple Voltage on HVDD
1k
10k 20k
Frequency (Hz)
15
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APA2057A
Typical Operating Characteristics (Cont.)
Supply Current vs. Supply Voltage
Shutdown Current vs. Supply Voltage
20
50
16
*HP Mode disable
HVDD=3.3V
IHVDD=0.15mA
14
12
10
8
**AMP Mode disable
VDD=5V
IVDD=12mA
6
4
Amp mode
HP mode
No Load
AMP Mode
No Load
Shutdown Current (µA)
Supply Current (mA)
18
40
ISD(VDD)
30
20
10
HP Mode
2
3.0
ISD(HVDD)
4.5
3.5
4.0
Supply Voltage (Volt)
5.0
0
5.5
3.0
Power Dissipation vs. Output Power
4.0
4.5
5.0
Supply Voltage (Volt)
5.5
Power Dissipation vs. Output Power
400
1.4
350
1.2
RL=16Ω
RL=4Ω
Power Dissipation (mW)
Power Dissipation (W)
3.5
1.0
0.8
0.6
RL=8Ω
0.4
VDD =5V
THD+N <1%
AMP mode
0.2
0.0
0.0
0.5
1.0
1.5
300
250
RL=32Ω
200
150
100
VDD =5V
HVDD=3.3V
THD+N <1%
HP mode
50
0
0
2.0
50
Output Power (W)
150
100
200
Output Power (mW)
Output Power vs Load Resistance &
Output Power vs Load Resistance
Output Power (mW)
250
Mono,
THD+N=10%
200
Charge Pump Capacitance
350
VDD =5V
HVDD=3.3V
Fin=1KHz
BW<80KHZ
HP mode
150
100
Mono,
THD+N=1%
50
250
CF=CCO=1µF
THD+N=1%; Mono
200
150
100
CF=CCO=1µF
THD+N=1%; Stereo, in phase
50
0
10
VDD =5V
Fin=1KHz
BW<80KHZ
HP mode
CF=CCO=2.2µF
THD+D=1%; Mono
& Stereo, in phase
300
Output Power (mW)
300
100
1000
10
Load Resistance (Ω)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
CF :Charge pump flying capacitor
CCO:Charge pump output capacitor
0
20
30
40
50
60
70
80
90 100
Load Resistance (Ω)
16
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APA2057A
Operating Waveforms
Output transient at Shutdown Release
Output Transient at Turn On
VDD
5V/div
HP_Out
5V/div
SD
10mV/div
HP_Out
10mV/div
AMP_Out
AMP_Out
20mV/div
((Out+)-(Out-))
20mV/div
((Out+)-(Out-))
20ms/div
20ms/div
Output Transient at Turn Off
Output transient at Shutdown Active
VDD
5V/div
HP_Out
5V/div
SD
HP_Out
10mV/div
10mV/div
AMP_Out
AMP_Out
20mV/div
((Out+)-(Out-))
200ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
20mV/div
((Out+)-(Out-))
20ms/div
17
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APA2057A
Pin Descriptions
TSSOP-28
TQFN-28
NO.
NO.
1
25
VDD
Power supply for control section
2
26
GND
Ground
3
27
INR_A
Right channel input terminal for speaker amplifier
4
28
INR_H
Right channel input terminal for headphone driver
5
1
INL_A
Left channel input terminal for speaker amplifier
6
2
INL_H
Left channel input terminal for headphone driver
7,23
3,19
PGND
Power ground
8
4
LOUT+
Left channel positive output for speaker
9
5
LOUT-
Left channel negative output for speaker
10,20
6,16
PVDD
Power amplifier power supply
11
7
CVDD
Charge pump power supply
12
8
CP+
13
9
CGND
14
10
CP-
15
11
CVSS
Charge pump output, connect to the “HVSS”
16
12
HVSS
Headphone amplifier negative power supply
17
13
HP_R
Right channel output for headphone
18
14
HP_L
19
15
HV DD
Headphone amplifier positive power supply
21
17
ROUT-
Right channel negative output for speaker
22
18
ROUT+
Right channel positive output for speaker
24
20
HP_EN
Headphone driver enable pin, pull high to enable headphone mode
25
21
BIAS
Bias voltage generator
It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix
gain and pull low to 0V, the APA2057A enter shutdown mode. ISD = 80µA
Name
26
22
SET
27
23
AMP_EN
28
24
BEEP
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
Function Description
Charge pump flying capacitor positive connection
Charge pump ground
Charge pump flying capacitor negative connection
Left channel output for headphone
Speaker driver enable pin, pull low to enable speaker mode
PC BEEP Trigger signal input
18
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APA2057A
Block Diagram
ROUT+
INR_A
ROUTInternal gain
setting
LOUT+
INL_A
LOUTSET
SET
BIAS
AMP_EN
SPK EN
Rf(HP_R)
HP_EN
HP EN
*40kΩ
INR_H
HP_R
Rf(HP_L)
*40kΩ
INL_H
HP_L
CVDD
HVDD
CP+
CP-
Charge
Pump
Power Mamagement
PVDD
VDD
CGND
CVSS
HVSS
PGND
GND
* The internal Rf's value has
10% variation by process
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
19
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APA2057A
Typical Application Circuit
ROUT+
R_CH
Ci(AMP_R)
R_ch
INR_A
4Ω
for AMP
2.2µF
ROUTInternal
gain
setting
LOUT+
Ci(AMP_L)
L_CH
L_ch
INL_A
for AMP
4Ω
2.2µF
VDD(5V)
LOUT-
10KΩ
R1
SET
10nF
SET
2.2µF
BIAS
Shutdown
R#
AMP_EN
SPK EN
CB
Rf(HP_R)
HP_EN
HP EN
SET
Recommended for
de-pop
51kΩ
Pull-high HP_EN to enable
headohone driver
Ring
*40KΩ
4.7nF
INR_H
HP_R
R_ch
39KΩ
3.3µF
for HP
Ci(HP_R)
Rf(HP_L)
Ri(HP_R)
Sleeve
Ci(HP_L)
Tip
Ri(HP_L)
L_ch
*40KΩ
INL_H
Headphone Jack
HP_L
for HP
3.3µF
39KΩ
CVDD
VDD(5V)
CVDD
HVDD(3.3V)
VDD(5V)
CCPB
CCPF
1µF
1µF
HVDD
CP+
CP-
Power
Management
Charge
Pump
PVDD
VDD
CGND
CS(PVDD)
10µF
CS(VDD)
R#: For the gain setting of speaker driver that
you need, refer to the Gain Setting Table’s
recommended voltage, and setting this voltage
at SET pin’s voltage =5R#/(R#+10K).
CVSS
CCPO
HVSS
PGND
GND
0.1µF
CS(HVDD)
0.1µF
0.1µF
VSS
1µF
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
20
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APA2057A
Application Information
Headphone Mode Operation
Amplifier Mode Operation
The APA2057A has two pairs of operational amplifiers
internally, which allows different amplifier configurations.
HVDD
VOUT
-
OUT+
+
Pre-amplifier
Output signal
HVDD/2
GND
OP1
Conventional Headphone amplifier
Vbias
HVDD
-
VOUT
DIFF_AMP_CONFIG
+
OUT-
GND
OP2
Figure 1: APA2057A internal configuration
(each channel)
The OP1 and OP2 are all differential drive configurations.
The differential drive configurations doubling the voltage
VSS
Cap-free Headphone amplifier
Figure 2: Cap-free Operation
swing on the load. Compare with the single-ending
configuration, the differential gain for each channel is 2X
The APA2057A’s headphone amplifiers uses a charge
pump to invert the positive power supply (CVDD) to negative
power supply (CV SS), see Figure2. The headphone amplifiers operate at this bipolar power supply (HVDD & VSS),
and the outputs reference refers to the ground. This feature eliminates the output capacitor that is using in conventional single-ended headphone amplifier. The headphone amplifier internal supply voltage comes from HVDD
and VSS. For good AC performance, the HVDD connected to
3.3V is recommended. It can avoid the output over voltage for line out application.
(Gain of SE mode).
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration commonly referred
to all differential mode is established. All differential mode
operation is different from the classical single-ended SE
amplifier configuration where one side of its load is connected to ground.
A differential amplifier design has a few distinct advantages over the SE configuration, as it provides differential
drive to the load, thus it is doubling the output swing
for a specified supply voltage. The output power can be
Charge Pump Flying Capacitor
4 times greater than the SE amplifier working under the
same condition. A differential configuration, similar as the
The flying capacitor (CCPF) affects the load transient of the
charge pump. If the capacitor’s value is too small, then
that will degrade the charge pump’s current driver capability and the performance of headphone amplifier.
one used in APA2057A, also creates a second advantage
over SE amplifiers. Since the differential outputs, ROUT+,
ROUT-, LOUT+, and LOUT-, are biased at half-supply,
there is no need for DC voltage across the load. This
Increasing the flying capacitor’s value will improve the
load transient of charge pump. It is recommend to use
the low ESR ceramic capacitors (X7R type is recommended)
above 1µf.
eliminates the need for an output coupling capacitor which
is required in a single supply, SE configuration.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
21
www.anpec.com.tw
APA2057A
Application Information (Cont.)
Charge Pump Output Capacitor
drive.
Both amplifier and headphone “ON” mode: Pull low
•
The output capacitor (C CPO)’s value affects the power
ripple directly at CVSS(VSS). Increasing the value of output
capacitor reduces the power ripple. The ESR of output
capacitor affects the load transient of CVSS(V SS ). Lower
ESR and greater than 1µf ceramic capacitor (X7R type
is recommended) is recommendation.
the AMP_EN and pull high the HP_EN control pins,
then turn on both speaker drivers and headphone
drivers
Both amplifier and headphone “OFF” mode: Pull
•
high the AMP_EN and pull low the HP_EN control
pins, then turn off both speaker drivers and head-
Charge Pump Bypass Capacitor
phone drivers
The bypass capacitor (CCPB) relates with the charge pump
switching transient. The capacitor’s value is same as
flying capacitor (1µf). Place it close to the CVDD and PGND.
If the AMP_EN and HP_EN are connected together, then
this pin will be connected to headphone jack’s control
pin (Figure 3), the APA2057A is switchable between “Amplifier mode (Headphone mute), or Headphone mode
Headphone Detection Input
HP_R
Control pin
HP_EN
(Amplifier mute).
Ring
1KΩ
Gain Setting
HPD_Switch
The gain for speaker drivers can be adjustable by applying DC voltage to SET pin. The APA2057A control con-
HP_L
sists 19 step gain settings from 2.0V~ 4.2V, and the gain
is from -7dB to 16dB. Each gain step corresponds to a
1KΩ
Sleeve
specific input voltage range, as shown in “Gain Setting
Table”. To minimize the effect of noise on the gain setting
Tip
Headphone Detection
Headphone Jack with swich
control, which can affect the selected gain level, hysteresis and clock delay are implemented. For the highest
Figure 3 HPD configurations
The HP_EN will detect the voltage. If the voltage is
accuracy, the voltage shown in the “recommended voltage” column of the table is used to select a desired gain.
less than 0.8V, the headphone amplifiers will be disabled;
if greater than 2V, then the headphone amplifier will be
This recommended voltage is exactly halfway between
the two nearest transitions. The amount of hysteresis
enabled.
corresponds to half of the step width, as shown in Figure 4. Apply 0V to SET pin will place the APA2057A into
In Figure 3, phone-jack with the control pin is used and
connected to HP_EN input from control pin. When a
headphone plug is inserted, the HP_EN will pull high
shutdown mode, and when SD =5V, it allows the speaker
driver at a fixed gain (AV=10.5dB).
internally which enables headphone amplifiers; without headphone plug, the HP_EN is pulled to GND.
20
10
Operation Mode
Gain (dB)
The APA2057A amplifier has two pairs of independent
amplifier. One for stereo speaker is BTL structure, and
the other for headphone is cap-less structure. Each pair
has independent input pin; INR_A and INA_L are for stereo speaker drivers, and INR_H and INL_H are for
•
-10
-20
-30
-50
-60
Amplifier mode operation: Pull low the AMP_EN
control pin can enable the stereo speaker driver.
-70
0.0
Headphone mode operation: Pull high the HP_EN
control pin can enable the cap-less headphone
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
Backward
-40
stereo headphone drivers.
•
Forward
0
1.0
2.0
3.
0
4.0
5.0
DC Volume (V)
Figure 4: APA2057A Gain setting vs. SET pin Voltage
22
www.anpec.com.tw
APA2057A
Application Information (Cont.)
Please note that it is important to confirm the capacitor polarity in the application.
Gain Setting (Cont.)
For headphone driver, the internal feedback resistor is
40kΩ (Rf(HP) external, 10% variation by process), so the
headphone driver’s gain is set by the input resistor (Ri(HP)
external), the Table 1 lists the reference gain settings
with external resistor for headphone driver (HP Mode).
Note: The headphone dirver’s input is ground reference,
so please check the C ’s polarized at design.
i(HP)
Effective Bias Capacitor, CB
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
HP Mode Gain Setting Table for Reference
Ri(HP),external *Rf(HP),internal
HP OUT (V/V) HP Gain(dB)
(kΩ)
(kΩ)
62
40
0.65
-3.8
50
40
0.80
-1.9
39
40
1.03
0.2
30
40
1.33
2.5
24
40
1.67
4.4
20
40
2.00
6.0
*The internal Rf's value has 10% variation by process.
rejection.
The capacitor location on both the bypass and power
supply pins should be as close to the device as possible.
The effect of a larger bypass capacitor is improved PSRR
due to increased 1.8V bias voltage stability. Typical
applications employ a 5V regulator with 2.2µF and a
0.1µF bypass capacitor, which aids in supply filtering.
Table 1: Gain Setting Table for Reference
Input Capacitor, Ci
This does not eliminate the need for bypassing the
supply nodes of the APA2057A. The selection of by-
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
pass capacitors, especially C B, is thus dependent upon
desired PSRR requirements and click-and-pop
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri from a high-pass filter with
performance.
the corner frequency are determined by the following
equation:
The APA2057A is a high-performance CMOS audio amplifier
that requires adequate power supply decoupling to
F C (highpass) =
1
(2 πR i(MIN) ×C i )
Power Supply Decoupling, Cs
(1)
ensure the output total harmonic distortion (THD+N)
is as low as possible. Power supply decoupling also
The value of Ci is important to consider as it directly
prevents the oscillations causing by long lead length
between the amplifier and the speaker. The optimum
affects the low frequency performance of the circuit.
Consider the example where R i is 10kΩ and the
decoupling is achieved by using two different types
of capacitor that target on different types of noise on the
specification calls for a flat bass response down to
10Hz. Equation is reconfigured as below:
1
(2)
Ci =
(2 πR iFc)
power supply leads. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically
0.1µF, is placed as close as possible to the device VDD
Consider to input resistance variation, the Ci is 1.6µF, so
one would likely choose a value in the range of 2.2µF
to 3.3µF. A further consideration for this capacitor is
lead works best (the pin1 (V ) and pin2 (GND)’s capaciDD
tor must short less than 1cm). For filtering lower-frequency
the leakage path from the input source through the input
network (R i+R f , Ci ) to the load. This leakage current
noise signals, a large aluminum electrolytic capacitor of
10µF or greater is placed near the audio power amplifier
creates a DC offset voltage at the input to the amplifier
that reduces useful headroom, especially in high gain
is recommended.
Shutdown Function
applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized
In order to reduce power consumption while not in use,
the APA2057A contains a shutdown pin to externally turn
capacitors are used, the positive side of the capacitor
should face the amplifier input. As the DC level is held
off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when a logic low is placed on the
at VDD/2, which is likely higher than the source DC level.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
23
www.anpec.com.tw
APA2057A
Application Information (Cont.)
power levels. Note that the efficiency of the amplifier is
quite low for lower power levels and rises sharply as
Shutdown Function (Cont.)
SET pin. The trigger point between a logic high and logic
low level is typically 2.0V. It is the best to switch be-
power to the load is increased resulting in nearly flat
internal power dissipation over the normal operating
tween ground and the supply VDD to provide maximum
device performance.
range. Note that the internal dissipation at full output
power is less than in the half power range. Calculating
By switching the SET pin to low, the amplifier enters a
the efficiency for a specific system is the key to proper
power supply design. For a stereo 1W audio system with
low-current consumption state, I DD<80µA. Even the
APA2057A is in shutdown mode, PC_BEEP will keep
8W loads and a 5V supply, the maximum draw on the
power supply is almost 3W.
detecting circuit. In normal operating, SET pin is pulled
to high level to keep the IC out of the shutdown mode.
The SET pin should be tied to a definite voltage to
avoid unwanted state changes.The wake-up time of shut-
Po (W)
Efficiency (%)
IDD(A)
VPP(V)
PD (W)
0.25
31.25
0.16
2.00
0.55
down is about 150ms, and the shutdown release’s
pop is caused by the operational amplifier’s offset.
0.50
47.62
0.21
2.83
0.55
1.00
66.67
0.30
4.00
0.5
PC-BEEP Detection
1.25
78.13
0.32
4.47
0.35
**High peak voltages cause the THD
D+N
to increase.
to increase
Table 2. Efficiency vs. Output Power in 5-V/8W Differential
Amplifier Systems.
The APA2057A integrates a PCBEEP circuit detection for notebook PC using. When PC-BEEP signal
drives to PCBEEP input pin, PCBEEP mode is active.
A final point to remember about linear amplifiers is how
The APA2057A will turn on speaker drivers and the internal gain is fixed as 0dB. The PCBEEP signal becomes
to manipulate the terms in the efficiency equation to
utmost advantage when possible. Note that in equation,
v
the amplifiers
input signal. If the amplifiers in the shutdown mode, it will be out of shutdown mode whenever
VDD is in the denominator. This indicates that as VDD goes
down, efficiency goes up. In other words, using the effi-
PCBEEP mode is enabled. The APA2057A will return to
previous setting when it is out of PC BEEP mode. The
ciency analysis to choose the correct supply voltage
and speaker impedance for the application.
input impedance is 100KΩ on PCBEEP input pin.
Power Dissipation
Speaker Driver Amplifier Efficiency
Whether the power amplifier is operated in BTL or SE
An easy-to-use equation to calculate efficiency starts out
modes, power dissipation is a major concern. Equation 8
states the maximum power dissipation point for a SE
as being equal to the ratio of power from the power
supply to the power delivered to the load. The following
mode operating at a given supply voltage and driving a
2
specified load.
V
PD,MAX = DD
(8)
2πRL
SE mode:
equations are the basis for calculating amplifier efficiency.
Efficiency =
PO
Psup
(3)
In BTL mode operation, the output voltage swing is
Where:
VOrms * VOrms
(V * VP )
= P
RL
2RL
VP
VOrms =
2
2VP
Psup = VDD * IDD (AVG) = VDD *
πRL
PO =
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the same
(4)
given conditions is 4 times as in SE mode.
2
4VDD
BTL mode: PD,MAX = 2
2p RL
(5)
(6)
Since the APA2057A is a dual channel power amplifier,
Efficiency of a Differential configuration:
the maximum internal power dissipation is 2 times that
both of equations depending on the mode of operation.
 (V * V )  
PO
2VP  πRL
(7)
=  P P  / VDD *
=
Psup  2RL  
πRL  4VDD
Table 1 calculates efficiencies for four different output
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
(9)
Even with this substantial increasing in power dissipation,
the APA2057A does not require extra heatsink. The
24
www.anpec.com.tw
APA2057A
Application Information (Cont.)
Power Dissipation (Cont.)
Via diameter
=15mil X10
70 mil
power dissipation from equation 9, assuming a 5Vpower supply and an 8Ω load, must not be greater than
the power dissipation that results from the equation 9:
T
-T
(10)
PD,MAX = J,MAX A
θJA
Via diameter
=25mil X4
120 mil
180 mil
70 mil
15 mil
For TSSOP-28 package with thermal pad, the thermal
resistance (θJA) is equal to 45oC/W.
240 mil
Since the maximum junction temperature (TJ,MAX) of
APA2057A is 150°C and the ambient temperature (TA) is
defined by the power system design, the maximum power
dissipation that the IC package is able to handle can be
obtained from equation10. Once the power dissipation is
greater than the maximum limit (PD,MAX), either the supply
voltage (V DD) must be decreased, the load impedance
(R L) must be increased or the ambient temperature
12mil
Exposed for thermal
PAD connected
Ground plane for
ThermalPAD
should be reduced.
Figure 5: TSSOP-28P layout recommendation
Thermal Pad Considerations
The thermal pad must be connected to ground. The
Thermal Considerations
package with thermal pad of the APA2057A requires
Linear power amplifiers dissipate a significant amount
special attention on thermal design. If the thermal design issues are not properly addressed, the APA2057A
of heat in the package under normal operating conditions.
In the Power Dissipation vs. Output Power graph, the
4Ω will go into thermal shutdown when driving a 4Ω load.
The thermal pad on the bottom of the APA2057A should
APA2057A is operating at a 5V supply and a 4Ω speaker
that 2W output power peaks are available. The vertical
be soldered down to a copper pad on the circuit board.
Heat can be conducted away from the thermal pad through
axis gives the information of power dissipation (PD) in
the IC with respect to each output driving power (PO) on
the copper plane to ambient. If the copper plane is not on
the top surface of the circuit board, 8 to 10 vias of 15 mil or
the horizontal axis.
This is valuable information when attempting to estimate
the heat dissipation of the IC requirements for the
smaller in diameter should be used to thermally couple
the thermal pad to the bottom plane. For good thermal
amplifier system.
conduction, the vias must be plated through and solder
filled. The copper plane used to conduct heat away from
Using the power dissipation curves for a 5V/4Ω system,
the internal dissipation in the APA2057A and maximum
ambient temperatures is shown in Table 3.
the thermal pad should be as large as practical.
If the ambient temperature is higher than 25°C, a larger
Peak output
power (W)
Average
output
power (W)
shutdown temperature (150°C).
2
1.95
1.25
37
In higher ambient temperature, higher airflow rate and/or
larger copper area will be required to keep the IC out of
2
1.17
1.25
37
2
0.74
1.19
43
thermal shutdown. See Demo Board Circuit Layout as
an example for PCB layout.
2
0.43
1.05
55
2
0.19
0.8
78
copper plane or forced-air cooling will be required to keep
the APA2057A junction temperature below the thermal
Power
Max. TA (°C)
dissipation
(W/channel) With thermal pad
Table 3: APA2057A Power information, 5V/4Ω, Stereo, Differential mode
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
25
www.anpec.com.tw
APA2057A
Application Information (Cont.)
Thermal Considerations (Cont.)
Package
θJA
TSSOP-28
45°C/W
TQFN -28
43°C/W
Table 4: Thermal resistance Table
This parameter is measured with the recommended
copper heat sink pattern on a 2-layer PCB, 23cm 2
i n 5 . 7 m m * 4 m m in PCB, 2oz. Copper, 100mm 2
coverage. Airflow 0 CFM the maximum ambient temperature depends on the heat sink ability of the PCB
system.
To calculate maximum ambient temperatures, first
consideration is that the numbers from the dissipation
graphs are per channel values, so the dissipation of the
IC heat needs to be doubled for two-channel operation.
Given θJA, the maximum allowable junction temperature
(TJ,Max), and the total intemal dissipation (PD), the maximum
ambient temperature can be calculated with the following
equation. The maximum recommended junction
temperature for the APA2057A is 150°C. The internal
dissipation figures are taken from the Power Dissipation
vs. Output Power graph.
TA,Max = TJ,Max - θJAPD
(11)
150 - 45(0.8*2) = 78°C (with thermal pad)
NOTE: Internal dissipation of 0.8W is estimated for a 2W system
with 15-dB headroom per channel.
Table 3 shows that for some applications, no airflow is
required to keep junction temperatures in the specified
range. The APA2057A is designed with a thermal shutdown protection that turns the device off when the junction
temperature surpasses 150°C to prevent IC from
damage. The information in table 3 was calculated for
maximum listen volume with limited distortion. When
the output level is reduced, the numbers in the table
change significantly. Also, using 8Ω speakers will dramatically increase the thermal performance by increasing
amplifier efficiency.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
26
www.anpec.com.tw
APA2057A
Package Information
TSSOP-28P
D
SEE VIEW A
E2
EXPOS
ED PAD
E1
E
D1
c
0.25
b
S
Y
M
B
O
L
VIEW A
L
GAUGE PLANE
SEATING PLANE
0
A1
A2
A
e
TSSOP-28P
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
9.60
9.80
0.378
0.386
D1
3.30
7.00
0.130
0.276
E
6.40 BSC
0.252 BSC
E1
4.30
4.50
0.169
0.177
E2
1.50
4.00
0.059
0.157
e
L
0
0.65 BSC
0.45
0°
0.026 BSC
0.75
0.018
0.030
8°
0°
8°
Note : 1. Followed from JEDEC MO-153 AET.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
27
www.anpec.com.tw
APA2057A
Package Information
TQFN5x5-28
D
b
E
A
A1
D2
A3
L
E2
Pin 1
Corner
e
TQFN5x5-28
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.30
0.007
3.80
0.138
3.80
0.138
0.45
0.014
MILLIMETERS
A3
b
0.20 REF
0.18
D
D2
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
0.150
0.197 BSC
0.50 BSC
0.35
0.012
0.197 BSC
5.00 BSC
3.50
e
L
0.008 REF
5.00 BSC
3.50
E
E2
INCHES
0.150
0.020 BSC
28
0.018
www.anpec.com.tw
APA2057A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
TSSOP-28P
Application
C
d
16.4+2.00 13.0+0.50
1.5 MIN.
-0.00
-0.20
D
P1
P2
D0
D1
T
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
A
H
T1
C
d
D
16.4+2.00 13.0+0.50
1.5 MIN.
-0.00
-0.20
W
E1
20.2 MIN. 16.0±0.30 1.75±0.10
P0
330.0±2.00 50 MIN.
TQFN5x5-28
T1
A0
B0
P1
P2
D0
D1
T
4.0±0.10
12.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
7.5±0.10
K0
6.90±0.20 10.2±0.20 1.50±0.20
W
E1
20.2 MIN. 12.0±0.30 1.75±0.10
P0
F
A0
B0
F
5.5±0.10
K0
5.30±0.20 5.30±0.20 1.30±0.20
(mm)
Devices Per Unit
Package Type
TSSOP- 28P
TQFN5x5-28
Unit
Tape & Reel
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
Quantity
2000
2500
29
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APA2057A
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
30
www.anpec.com.tw
APA2057A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
<2.5 mm
≥2.5 mm
Volume mm
≥350
225 +0/-5°C
225 +0/-5°C
Volume mm
<350
240 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2007
31
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