PD - 95773A
IRLR024ZPbF
IRLU024ZPbF
AUTOMOTIVE MOSFET
HEXFET® Power MOSFET
Features
n
n
n
n
n
n
n
Logic Level
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 55V
RDS(on) = 58mΩ
G
ID = 16A
S
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
D-Pak
IRLR024Z
I-Pak
IRLU024Z
Absolute Maximum Ratings
Parameter
Max.
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM
Pulsed Drain Current
11
c
Linear Derating Factor
Gate-to-Source Voltage
VGS
EAS (Thermally limited) Single Pulse Avalanche Energy
EAS (Tested )
Single Pulse Avalanche Energy Tested Value
d
c
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
A
64
PD @TC = 25°C Power Dissipation
IAR
Units
16
h
35
W
0.23
W/°C
± 16
V
25
mJ
25
See Fig.12a, 12b, 15, 16
g
A
mJ
-55 to + 175
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθJA
Junction-to-Ambient (PCB mount)
RθJA
Junction-to-Ambient
i
Typ.
Max.
–––
4.28
–––
40
–––
110
Units
°C/W
HEXFET® is a registered trademark of International Rectifier.
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1
12/8/04
IRLR/U024ZPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
Min. Typ. Max. Units
55
–––
–––
–––
0.053
–––
–––
46
58
–––
–––
80
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
e
e
= 3.0A e
VGS = 10V, ID = 9.6A
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
100
VGS(th)
Gate Threshold Voltage
1.0
–––
3.0
V
VDS = VGS, ID = 250µA
gfs
IDSS
Forward Transconductance
7.4
–––
–––
S
VDS = 25V, ID = 9.6A
µA
VDS = 55V, VGS = 0V
IGSS
Drain-to-Source Leakage Current
–––
–––
20
–––
–––
250
VGS = 5.0V, ID = 5.0A
VGS = 4.5V, ID
VDS = 55V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
nA
VGS = 16V
Qg
Total Gate Charge
–––
6.6
9.9
Qgs
Gate-to-Source Charge
–––
1.6
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
3.9
–––
VGS = 5.0V
td(on)
Turn-On Delay Time
–––
8.2
–––
VDD = 28V
tr
Rise Time
–––
43
–––
ID = 5.0A
td(off)
Turn-Off Delay Time
–––
19
–––
tf
Fall Time
–––
16
–––
VGS = 5.0V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
VGS = -16V
ID = 5.0A
nC
ns
nH
VDS = 44V
RG = 28 Ω
e
e
D
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Input Capacitance
–––
380
–––
and center of die contact
VGS = 0V
Coss
Output Capacitance
–––
62
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
39
–––
Coss
Output Capacitance
–––
180
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
50
–––
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
81
–––
VGS = 0V, VDS = 0V to 44V
pF
G
S
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
16
ISM
(Body Diode)
Pulsed Source Current
–––
–––
64
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 9.6A, VGS = 0V
trr
Reverse Recovery Time
–––
16
24
ns
Qrr
Reverse Recovery Charge
–––
11
17
nC
ton
Forward Turn-On Time
2
c
MOSFET symbol
A
D
G
S
e
TJ = 25°C, IF = 9.6A, VDD = 28V
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRLR/U024ZPbF
100
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
1
3.0V
10
BOTTOM
VGS
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
3.0V
1
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1
0.1
0.1
1
0.1
10
10
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
15
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
1
T J = 175°C
10
1
T J = 25°C
VDS = 10V
≤60µs PULSE WIDTH
0.1
T J = 25°C
10
TJ = 175°C
5
V DS = 8.0V
300µs PULSE WIDTH
0
0
2
4
6
8
10
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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12
0
2
4
6
8
10
12
14
16
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRLR/U024ZPbF
10000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS , Gate-to-Source Voltage (V)
ID= 5.0A
C, Capacitance(pF)
C oss = C ds + C gd
1000
Ciss
Coss
100
Crss
VDS= 44V
VDS= 28V
5.0
VDS= 11V
4.0
3.0
2.0
1.0
10
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
2
3
4
5
6
7
Q G Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
100
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 175°C
10
T J = 25°C
10
100µsec
1
VGS = 0V
1
10msec
0.1
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
3.0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U024ZPbF
16
ID, Drain Current (A)
14
12
10
8
6
4
2
ID = 5.0A
VGS = 5.0V
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
2.5
1.5
1.0
0
0.5
25
50
75
100
125
150
-60 -40 -20 0
175
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
T C , Case Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
10
Thermal Response ( Z thJC )
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
τJ
τJ
τ1
R2
R2
τC
τ2
τ1
τ2
τ
Ri (°C/W) τi (sec)
2.354
0.000354
1.926
0.001779
Ci= τi/Ri
Ci= i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.01
R1
R1
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U024ZPbF
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
100
15V
ID
1.2A
1.8A
BOTTOM 9.6A
TOP
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
2.5
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
VCC
VGS(th) Gate threshold Voltage (V)
QGS
2.0
ID = 250µA
1.5
1.0
-75 -50 -25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRLR/U024ZPbF
Avalanche Current (A)
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
Duty Cycle = Single Pulse
10
0.01
0.05
0.10
1
0.1
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
30
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 9.6A
25
20
15
10
5
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRLR/U024ZPbF
D.U.T
Driver Gate Drive
+
-
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRLR/U024ZPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRF R120
WITH AS SEMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 1999
IN T HE AS SEMBLY LINE "A"
PART NUMBER
INTERNAT IONAL
RECTIF IER
LOGO
Note: "P" in as sembly line position
indicates "Lead-Free"
IRFU120
12
916A
34
AS SEMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INTERNATIONAL
RECT IFIER
LOGO
IRFU120
12
ASSEMBLY
LOT CODE
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34
DAT E CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = ASSEMBLY SIT E CODE
9
IRLR/U024ZPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS SEMB LY
LOT CODE 5678
ASS EMBLED ON WW 19, 1999
IN T HE ASS EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF U120
919A
56
78
AS SEMB LY
LOT CODE
Note: "P" in assembly line
pos ition indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFU120
56
AS S EMBLY
LOT CODE
10
78
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 19
A = AS S EMBLY SIT E CODE
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IRLR/U024ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.54mH
RG = 25Ω, IAS = 9.6A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994.
Rθ is measured at TJ of approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/