– – E T E L OBSO AP0332 8 P-Channel Latchable Power MOSFET Array Ordering Information VDD RO(ON) IO(ON) IO(OFF) Order Number/Package (max) (max) (min) (max) SO-16 Die -320V 700Ω -15mA -1.0nA AP0332CG AP0332ND *Average current per channel, measured with all eight channels connected in parallel. Features General Description The Supertex AP0332 is an 8 P-Channel 320V common source power MOSFET array with a CMOS 8 bit addressable latch. The outputs are guaranteed to have very low leakage current. The outputs are addressed by logic inputs A0, A1, and A2. The addressed and unaddressed output can be turned on or off by the data, set, and write disable inputs. Low drain to source leakage Interfaces directly to TTL and CMOS logic 8 independent channels Low crosstalk between channels Low power dissipation The AP0332 is ideally suited for low leakage/high impedance measurements, providing excellent accuracy as well as resolution for automatic bare board test equipment and other applications. Freedom from secondary breakdown Serial data input On-chip decoder, latch with set and write disable circuitry Applications High impedance/low leakage measurements for bare board testers Pin Configuration High voltage piezoelectric transducer drivers High voltage electroluminescent panel drivers High voltage electrostatic array drivers General multi-channel driver arrays Absolute Maximum Ratings1 Off-state output voltage, VOO Logic supply voltage, VDD Logic input levels, all inputs Operating and storage temperature range Soldering temperature 2 Channel-to-channel crosstalk -320V Q7 1 16 VDD Set 2 15 Q6 Data 3 14 Q5 Write Dis 4 13 Q4 A0 5 12 Q3 A1 6 11 Q2 -0.5V to +15V A2 7 10 Q1 -0.5V to VDD VSS 8 9 Q0 -55°C to +150°C top view SO-16 300°C 10mV/V Notes: 1. All voltages are referenced to VSS. 2. Distance of 1.6mm from case for 10 seconds. Note: See Package Outline section for dimensions. 9-5 9 AP0332 Electrical Characteristics (@ 25°C and V DD = 12V unless otherwise specified) DC Characteristics Symbol Parameter IO(OFF) Off-State Output Current IO(ON) On-State Output Current RO(ON) On-State Output Resistance ∆RO(ON) Change in RO(ON) with High Temperature IDDQ Quiescent Logic Supply Current VIL Input Low Voltage VIH Input High Voltage IIN Input Current Note: 1. All voltages are referenced to VSS. AC Characteristics Symbol Min Typ Max Unit -8.0 nA VO = max. rating, 8 outputs connected in parallel mA VO = 25V -15 700 0.8 0.05 Ω IO = -10mA %/°C IO = -10mA 16.5 µA 3.5 V 12 Conditions V 1.0 µA – E T E L O S B O – Parameter Min Typ Max Unit Fig. 1* tD(ON) Turn-On Delay Time 800 ns 1a tD(OFF) Turn-Off Delay Time 800 ns 1b tr Rise Time 200 ns 10 tf Fall Time 200 ns 11 tPHL, tPLH Propagation Delay Time from Write Disable to Output 87 ns 2 tPHL, tPLH Propagation Delay Time from Set to Output 87 ns 3 tPHL, tPLH Propagation Delay Time from Address to Output 107 ns 9 tW Minimum Pulse Width – Data 50 100 ns 4 tW Minimum Pulse Width – Address 100 200 ns 8 tW Minimum Pulse Width – Set 40 75 ns 5 tS Setup Time – Data to Write Disable 50 ns 6 tH Hold Time – Data to Write Disable 75 ns 7 CIN Input capacitance – Any Input 5.0 *Refer to circled numbers on Timing Diagram (Figure 1). Note: 1. All voltages are referenced to VSS. 9-6 7.5 pF Conditions VO = 25V, IO = -10mA AP0332 Recommended Operating Conditions (For maximum reliability, nominal operating conditons should be selected so that operation is always within the following ranges.) Symbol Parameter VDD Min Max Unit 10.0 13.2 V 0 -320 V VDD Logic supply voltage VO Output Voltage referenced to VDD VIH Input High Voltage 12V VDD - 2 VDD V VIL Input Low Voltage 12V 0 2.0 V TA Operating Free-Air Temperature 0 70 °C Note: 1. All voltages are referenced to VSS. Mode Selection – E T E L O S B O – Data Write Disable Set Addressed Output Unaddressed Outputs H L L L Off On Holdspriv. H L H L Holdspriv. Holdspriv. H L L H Off On Off H L H H Off Off 9 Timing Diagram A0, A1, A2 tW 8 Write Disable Data Set 5 tW tW tS tH 4 6 7 Q0 ON Q0 OFF Q7 ON td(ON) 1a tP 3 tf 11 tP tP 2 9 Q7 OFF 1b td(OFF) tR 10 Figure 1 9-7 AP0332 – E T E L O S B O – Functional Block Diagram VDD (+) S Data Write Disable Latch Q7 Latch Q6 Latch Q5 A0 Latch 3:8 Decoder A1 Q4 Latch A2 Q3 Latch Q2 Latch Q1 Latch Q0 Set VSS (–) 9-8