Dallas DS1243Y-120 64k nv sram with phantom clock Datasheet

DS1243Y
64K NV SRAM with Phantom Clock
www.dalsemi.com
PIN ASSIGNMENT
FEATURES
§ Real time clock keeps track of hundredths of
seconds, seconds, minutes, hours, days, date
of the month, months, and years
§ 8K x 8 NV SRAM directly replaces volatile
static RAM or EEPROM
§ Embedded lithium energy cell maintains
calendar operation and retains RAM data
§ Watch function is transparent to RAM
operation
§ Month and year determine the number of days
in each month; valid up to 2100
§ Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
§ Standard 28–pin JEDEC pinout
§ Full ±10% operating range
§ Operating temperature range 0°C to 70°C
§ Accuracy is better than ±1 minute/month @
25°C
§ Over 10 years of data retention in the absence
of power
§ Available in 120, 150 and 200 ns access time
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
1
2
3
4
5
6
7
8
9
10
11
12
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ2
13
16
DQ4
GND
14
15
DQ3
28-Pin Encapsulated Package
720-Mil Extended
PIN DESCRIPTION
A0–A12
CE
GND
DQ0–DQ7
VCC
WE
ORDERING INFORMATION
OE
DS1243Y–XXX
NC
DS1243Y
–120 120 ns access
–150 150 ns access
200 ns access
RST
– Address Inputs
– Chip Enable
– Ground
– Data In/Data Out
– Power (+5V)
– Write Enable
– Output Enable
– No Connect
– Reset
DESCRIPTION
The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192
words by 8 bits) with a built–in real time clock. The DS1243Y has a self–contained lithium energy source
and control circuitry which constantly monitors VCC for an out–of–tolerance condition. When such a
condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent corrupted data in both the memory and real time clock.
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080299
DS1243Y
The Phantom Clock provides timekeeping information including hundredths of seconds, seconds,
minutes, hours, day, date, month, and year information. The date at the end of the month is automatically
adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock
operates in either 24–hour or 12–hour format with an AM/PM indicator.
RAM READ MODE
The DS1243Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers
within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output
Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either
tCO for CE or tOE for OE rather than address access.
RAM WRITE MODE
The DS1243Y is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active)
then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1243Y provides full functional capability for VCC greater than VTP and write protects by 4.25
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write
protects itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC
falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power–up, when VCC rises above approximately 3.0 volts, the power
switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 4.5 volts.
FRESHNESS SEAL
Each DS1243Y is shipped from Dallas Semiconductor with its lithium energy source disconnected,
insuring full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy
source is enabled for battery backup operation.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
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DS1243Y
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable ( CE ), Output Enable ( OE ), and Write Enable ( WE ). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable.
However, the write cycles generated to gain access to the Phantom Clock are also writing data to a
location in the mated RAM. The preferred way to manage this requirement is to set aside just one address
location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared
to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location
of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not
advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the
Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64
cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of
the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with
CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom
Clock.
PHANTOM CLOCK
REGISTER INFORMATION
The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
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DS1243Y
PHANTOM CLOCK REGISTER DEFINITION Figure 1
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This
pattern is sent to the Phantom Clock LSB to MSB.
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DS1243Y
PHANTOM CLOCK REGISTER DEFINITION Figure 2
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode,
bit 5 is the second 10–hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET
bit is set to logic 0, a low input on the RESET pin will cause the Phantom Clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
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DS1243Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
*
–0.3V to +7.0V
0°C to 70°C
–40°C to +70°C
260°C for 10 seconds (See Note 13)
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input Logic 1
Input Logic 0
SYMBOL
VCC
VIH
VIL
MIN
4.5
2.2
-0.3
MAX
5.5
VCC+0.3
0.8
UNITS
V
V
V
NOTES
(0°C to 70°C; VCC = 5V ± 10%)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE ≥ VIH ≤VCC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE = 2.2
Standby Current CE = VCC – 0.5V
Operating Current tCYC = 200ns
Write Protection Voltage
(0°C to 70°C)
TYP
5.0
SYMBOL
IIL
IIO
MIN
-1.0
-1.0
IOH
IOL
ICCS1
ICCS2
ICC01
VTP
-1.0
2.0
TYP
MAX
+1.0
+1.0
UNITS
µA
µA
5.0
3.0
10
5.0
85
4.5
mA
mA
mA
mA
mA
V
TYP
5
5
MAX
10
10
UNITS
pF
pF
4.25
NOTES
12
DC TEST CONDITIONS
Outputs are open; all voltages are referenced to ground.
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
(tA = 25°C)
SYMBOL
CIN
CI/O
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MIN
NOTES
DS1243Y
MEMORY AC ELECTRICAL
CHARACTERISTICS
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to
Output Active
Output High Z from
Deselection
Output Hold from
Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery
Time
Output High Z from
(0°C to 70°C; VCC = 5.0V ± 10%)
DS1243Y-120
SYMBOL MIN MAX
tRC
120
tACC
120
tOE
60
tCO
120
tCOE
5
tOD
DS1243Y-150
MIN MAX
150
150
70
150
5
40
DS1243Y
MIN MAX
200
200
100
200
5
70
100
UNITS
ns
ns
ns
ns
ns
NOTES
ns
5
toH
5
5
5
ns
tWC
tWP
tAW
tWR
120
90
0
20
150
100
0
20
200
150
0
20
ns
ns
ns
ns
tODW
40
70
80
5
3
ns
5
WE
Output Active from
tOEW
5
5
5
ns
5
tDS
tDH
50
20
60
20
80
20
ns
ns
4
4
WE
Data Setup Time
Data Hold Time
from WE
AC TEST CONDITIONS
Output Load:
Input Pulse Levels:
50 pF + 1TTL Gate
0–3V
Timing Measurement Reference Levels
Input:
1.5V
Output:
1.5V
Input Pulse Rise and Fall Times:
5 ns
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DS1243Y
PHANTOM CLOCK AC ELECTRICAL
CHARACTERISTICS
PARAMETER
Read Cycle Time
CE Access Time
OE Access Time
CE to Output Low Z
OE to Output Low Z
CE to Output High Z
OE to Output High Z
Read Recovery
Write Cycle Time
Write Pulse Width
Write Recovery
Data Setup Time
Data Hold Time
CE Pulse Width
RESET Pulse Width
CE High to Power-Fail
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tRST
tPF
(0°C to 70°C; VCC = 4.5 to 5.5V)
MIN
120
TYP
MAX
100
100
10
10
40
40
20
120
100
20
40
10
100
200
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
UNITS
µs
µs
µs
ms
NOTES
5
5
10
11
11
POWER-DOWN/POWER-UP TIMING
PARAMETER
CE at VIH before Power-Down
VCC Slew from 4.5V to 0V ( CE at VIH)
VCC Slew from 0V to 4.5V ( CE at VIH)
CE at VIH after Power-Up
SYMBOL
tPD
tF
tR
tREC
MIN
0
300
0
TYP
MAX
2
(tA = 25°C)
PARAMETER
Expected Data Retention Time
SYMBOL
tDR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
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DS1243Y
MEMORY READ CYCLE (NOTE 1)
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
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DS1243Y
MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
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DS1243Y
WRITE CYCLE TO PHANTOM CLOCK
POWER-DOWN/POWER-UP CONDITION
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DS1243Y
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10. tWR is a function of the latter occurring edge of WE or CE .
11. tDH and tDS are a function of the first occurring edge of WE or CE .
12. RST (Pin1) has an internal pull–up resistor.
13. Real–Time Clock Modules can be successfully processed through conventional wave–soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
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DS1243Y
DS1243Y 28–PIN EXTENDED BOTTOM
720-MIL BODY WIDTH (DIMENSION B)
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
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28-PIN
MIN
MAX
1.520
1.540
38.61
39.12
0.695
0.720
17.65
1.29
0.395
0.415
10.03
10.54
0.100
0.130
2.54
3.30
0.017
0.030
0.43
0.76
0.120
0.160
3.05
4.06
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.008
0.012
0.20
0.30
0.015
0.021
0.38
0.53