DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 DRV8313 TRIPLE HALF-H-BRIDGE DRIVER IC Check for Samples: DRV8313 FEATURES DESCRIPTION • The DRV8313 provides three individually controllable half-H-bridge drivers. It is intended to drive a threephase brushless dc motor, though it can also be used to drive solenoids or other loads. Each output driver channel consists of N-channel power MOSFETs configured in a half-H-bridge configuration. The design brings the ground terminals of each driver to pins, to allow one to perform current sensing on each output. 1 23 • • • • • Three Half-H-Bridge Driver IC – Drives 3-Phase Brushless DC Motors – Individual Half-Bridge Control – Pins for Low-Side Current Sensing – Low MOSFET On-Resistance 2.5-A Maximum Drive Current at 24 V, 25°C Uncommitted Comparator Can Be Used for Current Limit or Other Functions Built-In 3.3-V 10-mA LDO Regulator 8-V to 60-V Operating Supply Voltage Range Thermally Enhanced Surface-Mount Package APPLICATIONS • • • • • The DRV8313 comes PowerPAD™ package. (1) (2) in a 28-pin HTSSOP ORDERING INFORMATION (1) PACKAGE (2) ORDERABLE PART NUMBER DRV8313PWP The DRV8313 can supply up to 2.5-A peak or 1.75-A rms output current per channel (with proper PCB heatsinking at 24 V and 25°C) per half-H-bridge. The device provides internal shutdown functions for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature. HVAC Motors Consumer Products Office Automation Machines Factory Automation Robotics DRV8313PWPR Current-limit circuitry or other functions are possible uses of an uncommitted comparator. HTSSOP – PWP TOPSIDE MARKING DRV8313 SHIPPING Reel of 2000 Tube of 50 For the most-current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. See package drawings, thermal data, and symbolization at www.ti.com/packaging. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DRV8313 SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM VM 10 μF VM VM VM Internal Reference and Regs VM Int. VCC CP 1 LS Gate Drive 0.01 μF Charge Pump V3P3OUT CP 2 VM VCP Thermal Shutdown 0.1 μF HS Gate Drive VM IN1 EN1 Predriver OCP OUT1 IN2 PGND1 EN2 VM IN3 Optional EN3 Control Logic Predriver OCP OUT2 PGND2 RESET SLEEP VM Optional FAULT Predriver OCP OUT3 PGND3 COMPO COMPP Optional + COMPN GND1 GND2 GND3 B0480-01 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 PWP Package (Top View) CP1 CP2 1 28 2 27 VCP VM OUT1 PGND1 3 26 4 25 PGND2 OUT2 OUT3 PGND3 VM COMPP COMPN GND 7 5 24 6 23 8 Thermal Pad (GND) GND IN1 EN1 IN2 EN2 IN3 EN3 NC GND COMPO FAULT SLEEP RESET V3P3OUT 22 21 9 20 10 19 11 18 12 17 13 16 14 15 P0146-01 PIN DESCRIPTIONS PIN NAME NO. TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS Power and Ground CP1 1 IO Charge-pump flying capacitor CP2 2 IO Charge-pump flying capacitor GND 12, 20, 28, PPAD – Device ground Connect to system ground V3P3OUT 15 O 3.3-V regulator output Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Use for suppling external loads is permissible. VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM. VM 4, 11 – Main power supply Connect to power supply (8.2 V–60 V). Connect both pins to the same supply. Bypass to GND with a 10-µF (minimum) capacitor. EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the outputs. Internal pulldown nSLEEP 17 I Sleep-mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent, UVLO) COMPN 13 I Comparator negative input Negative input of comparator COMPP 12 I Comparator positive input Positive input of comparator nCOMPO 19 OD Comparator out Output of comparator. Open-drain output Connect a 0.01-μF 100-V capacitor between CP1 and CP2. Control Status nFAULT Comparator Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 3 DRV8313 SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com PIN DESCRIPTIONS (continued) PIN NAME NO. TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS Output OUT1 5 O Output 1 OUT2 8 O Output 2 OUT3 9 O Output 3 PGND1 6 – Ground for OUT1 PGND2 7 – Ground for OUT2 PGND3 10 – Ground for OUT3 Connect to loads. Connect to ground, or to low-side current-sense resistors. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT –0.3 V to 65 V Digital-pin voltage range –0.5 to 7 V Comparator input-voltage range –0.5 to 7 V Peak motor-drive output current Internally limited A ±600 mV Power-supply voltage range (VM) Pin voltage (GND1, GND2, GND3) Continuous motor-drive output current (3) 2.5 A TJ Operating virtual junction temperature range –40 to 150 ºC Tstg Storage temperature range –60 to 150 ºC (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. Observe power dissipation and thermal limits. THERMAL INFORMATION DRV8313 THERMAL METRIC (1) PWP UNIT 28 PINS θJA Junction-to-ambient thermal resistance (2) 31.6 °C/W θJCtop Junction-to-case (top) thermal resistance (3) 15.9 °C/W θJB Junction-to-board thermal resistance (4) 5.6 °C/W (5) ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter (6) 5.5 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) 1.4 °C/W (1) (2) (3) (4) (5) (6) (7) 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VM Motor power-supply voltage range VGNDX GND1, GND2, GND3 pin voltage IV3P3 V3P3OUT load current (1) (1) NOM MAX 60 V 0 500 mV 10 mA MAX UNIT 8 –500 0 UNIT All VM pins must be connected to the same supply voltage. ELECTRICAL CHARACTERISTICS TA = 25°C, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Power Supplies IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 1 5 mA IVMQ VM sleep-mode supply current VM = 24 V 500 800 µA VUVLO VM undervoltage lockout voltage VM rising 6.3 8 V 3.3 3.52 V 0.6 0.7 V V3P3OUT Regulator V3P3 V3P3OUT voltage IOUT = 0 to 10 mA 3.1 Logic-Level Inputs VIL Input low voltage VIH Input high voltage 2.2 5.25 V VHYS Input hysteresis 50 600 mV IIL Input low current VIN = 0 –5 5 µA IIH Input high current VIN = 3.3 V 100 µA RPD Pulldown resistance 100 kΩ nFAULT and COMPO OutputS (Open-Drain Outputs) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 µA 5 V –7 7 mV –300 300 nA 2 µs Comparator VCM Common-mode input-voltage range VIO Input offset voltage IIB Input bias current tR Response time 0 100-mV step with 10-mV overdrive H-Bridge FETs rds(on) High-side FET on-resistance rds(on) Low-side FET on-resistance IOFF Off-state leakage current tDEAD Output dead time VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C 0.29 VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C 0.29 –2 0.39 0.39 2 Ω Ω µA 90 ns 5 µs Protection Circuits IOCP Overcurrent protection trip level tOCP Overcurrent protection deglitch time TTSD Thermal shutdown temperature 3 Die temperature 150 A 160 180 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 °C 5 DRV8313 SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com SWITCHING CHARACTERISTICS (1) TA = 25°, VM = 24 V, RL = 20 Ω (1) NO. PARAMETER 1 t1 2 t2 3 DESCRIPTION MIN MAX UNIT Delay time, ENx high to OUTx high, INx = 1 130 330 ns Delay time, ENx low to OUTx low, INx = 1 275 475 ns t3 Delay time, ENx high to OUTx low, INx = 0 100 300 ns 4 t4 Delay time, ENx low to OUTx high, INx = 0 200 400 ns 5 t5 Delay time, INx high to OUTx high 300 500 ns 6 t6 Delay time, INx low to OUTx low 275 475 ns 7 tr Output rise time, resistive load to GND 30 150 ns 8 tf Output fall time, resistive load to GND 30 150 ns Not production tested ENx 50% 50% ENx t1 OUTx 50% t2 50% 50% t3 OUTx 50% 50% t4 50% INx = 0, Resistive Load to VM INx = 1, Resistive Load to GND INx 50% 50% t5 t6 80% 80% OUTx OUTx 50% 50% 20% 20% tr tf ENx = 1, Resistive Load to GND T0543-01 Figure 1. DRV8313 Switching Characteristics 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 FUNCTIONAL DESCRIPTION Output Stage The DRV8313 contains three half-H-bridge drivers. The source terminals of the low-side FETs of all three half-Hbridges terminate at separate pins (GND1, GND2, and GND3) to allow the use of a low-side current-sense resistor on each output, if desired. The user may also connect all three together to a single low-side sense resistor, or may connect them directly to ground if there is no need for current sensing. If using a low-side sense resistor, take care to ensure that the voltage on the GND1, GND2, or GND3 pin does not exceed ±500 mV. Note that there are multiple VM motor power-supply pins. Connect all VM pins together to the motor-supply voltage. Bridge Control The INx input pins directly control the state (high or low) of the OUTx outputs; the ENx input pins enable or disable the OUTx driver. The following table shows the logic: INx ENx OUTx X 0 Z 0 1 L 1 1 H Charge Pump Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power supply to enhance the high-side FETs fully. The DRV8313 integrates a charge-pump circuit that generates a voltage above the VM supply for this purpose. The charge pump requires two external capacitors for operation. See the block diagram and pin descriptions for details on these capacitors (value, connection, and so forth). The charge pump shuts down when nSLEEP is active-low. VM VM CP1 0.01 F 100 V CP2 Charge Pump VCP 0.1 F 16 V To Predrivers B0481-01 Figure 2. DRV8313 Charge Pump Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 7 DRV8313 SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com Comparator The DRV8313 includes an uncommitted comparator, which can find use as a current-limit comparator or for other purposes. The following diagram shows connections to use the comparator to sense current for implementing a current limit. Current from all three low-side FETs is sensed using a single low-side sense resistor. The voltage across the sense resistor is compared with a reference, and when the sensed voltage exceeds the reference, a currentlimit condition is signaled to the controller. The V3P3OUT internal voltage regulator can be used to set the reference voltage of the comparator. V3P3OUT Current Limit COMPO COMPN – + COMPP VREF PGND1 PGND2 PGND3 RSENSE B0482-01 Figure 3. DRV8313 Comparator nRESET and nSLEEP Operation The nRESET pin, when driven active-low, resets any faults. It also disables the output drivers while it is active. The device ignores all inputs while nRESET is active. Note that there is an internal power-up-reset circuit, so that driving nRESET at power up is not required. Driving nSLEEP low puts the device into a low-power sleep state. Entering this state disables the output drivers, stops the gate-drive charge pump, resets all internal logic (including faults), and stops all internal clocks. In this state, the device ignores all inputs until nSLEEP returns inactive-high. When returning from sleep mode, some time (approximately 1 ms) must pass before the motor driver becomes fully operational. Note that the V3P3 regulator remains operational in sleep mode. Protection Circuits The DRV8313 has full protection against undervoltage, overcurrent, and overtemperature events. OVERCURRENT PROTECTION (OCP) An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP deglitch time, the device disables the channel experiencing the overcurrent and drives the nFAULT pin low. The driver remains off until either assertion of nRESET or the cycling of VM power. Overcurrent conditions on both high- and low-side devices, that is, a short to ground, supply, or across the motor winding, all result in an overcurrent shutdown. THERMAL SHUTDOWN (TSD) If the die temperature exceeds safe limits, the device disables all outputs and drives the nFAULT pin low. Once the die temperature has fallen to a safe level, operation automatically resumes. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 UNDERVOLTAGE LOCKOUT (UVLO) If at any time the voltage on the VM pins falls below the undervoltage-lockout threshold voltage, the device disables all outputs, resets internal logic, and drives the nFAULT pin low. Operation resumes when VM rises above the UVLO threshold. THERMAL INFORMATION Thermal Protection The DRV8313 has thermal shutdown (TSD) as previously described. A die temperature in excess of approximately 150°C disables the device until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation The power dissipated in the output FET resistance, or rDS(on) dominates power dissipation in the DRV8313. A rough estimate of average power dissipation of each half-H-bridge when running a static load is: P = r DS(on) ´ (IOUT )2 (1) where P is the power dissipation of one H-bridge, rDS(on) is the resistance of each FET, and IOUT is equal to the average current drawn by the load. Note that at start-up and fault conditions, this current is much higher than normal running current; remember to take these peak currents and their duration into consideration. The total device dissipation is the power dissipated in each of the three half-H-bridges added together. The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking. Note that rDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when sizing the heatsink. Heatsinking The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, add a number of vias to connect the thermal pad to the ground plane to accomplish this. On PCBs without internal planes, add copper area on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, use thermal vias to transfer the heat between the top and bottom layers. For details about how to design the PCB, see TI Application Report SLMA002, PowerPAD Thermally Enhanced Package and TI Application Brief SLMA004, PowerPAD Made Easy, available at www.ti.com. In general, providing more copper area allows the dissipation of more power. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 9 DRV8313 SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 www.ti.com APPLICATION INFORMATION Output Configurations and Connections The typical application for the DRV8313 is to drive a 3-phase brushless motor. In this application, the three outputs connect to the three motor leads, as shown in Figure 4. OUT1 Phase U OUT2 Phase V Phase W OUT3 Figure 4. Three-Phase Motor Connection The device achieves standard 120° (also called trapezoidal or block) commutation, using synchronous rectification, by following the states shown in Table 1 Table 1. Three-Phase Motor Signals State OUT1 (Phase U) OUT2 (Phase V) OUT3 (Phase W) IN1 EN1 OUT1 IN2 EN2 OUT2 IN3 EN3 OUT3 1 X 0 Z 1 / PWM 1 H / PWM 0 1 L 2 1 / PWM 1 H / PWM X 0 Z 0 1 L 3 1 / PWM 1 H / PWM 0 1 L X 0 Z 4 X 0 Z 0 1 L 1 / PWM 1 H / PWM 5 0 1 L X 0 Z 1 / PWM 1 H / PWM 6 0 1 L 1 / PWM 1 H / PWM X 0 Z On can implement asynchronous rectification by also applying the PWM signal to the enable inputs. The DRV8313 can drive other loads, including dc brush motors and solenoids. For example, one could drive a dc brush motor in both directions, plus a single solenoid or unidirectional dc brush motor: OUT1 DCM Motor 1 OUT2 OUT3 Motor 2 or Solenoid Figure 5. Bidirectional Motor Plus Motor or Solenoid Connection 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 DRV8313 www.ti.com SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012 The functions would be as shown in Table 2. Table 2. Bidirectional Motor Plus Motor or Solenoid Signals Motor 1 Function Motor 2 or Solenoid IN1 EN1 OUT1 IN2 EN2 OUT2 Function Off or coast IN3 EN3 OUT3 X 0 Z X X X On 1 / PWM 1 1 Off or coast X X X X 0 X Off or slow decay 0 1 0 Forward 1 / PWM 1 1 0 1 0 Off or coast X 0 X Reverse 0 1 0 1 / PWM 1 1 Brake or slow decay 0 1 0 0 1 0 Brake or slow decay 1 1 1 1 1 1 Applying a PWM signal to the appropriate INx pin(s) as shown in Table 2 could implement PWM speed control. Another possibility is controlling three different loads. Note that it is possible to return one side of the load either to the power supply (VM) or to ground. OUT1 VM Motor or Solenoid 1 Motor or Solenoid 2 OUT2 OUT3 Motor or Solenoid 2 Figure 6. Three Independent Load Connections Table 3. Three Independent Load Signals Motor or Solenoid 1 Function Motor or Solenoid 2 IN1 EN1 OUT1 1 / PWM 1 1 On Off or slow decay 0 1 0 Off or coast X 0 X On Function Motor or Solenoid 3 IN2 EN2 OUT2 Function 1 / PWM 1 1 On IN3 EN3 OUT3 1 / PWM 1 1 Off or slow decay 0 1 0 Off or slow decay 0 1 0 Off or coast X 0 X Off or coast X 0 X Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: DRV8313 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DRV8313PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8313 DRV8313PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8313 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8313PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8313PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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