Cypress CY14B101PA 1-mbit (128 k ã 8) serial (spi) nvsram with real time clock Datasheet

CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
1-Mbit (128 K × 8) Serial (SPI) nvSRAM
with Real Time Clock
Features
■
Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■
Low power consumption
❐ Average active current of 3 mA at 40 MHz operation
❐ Average standby mode current of 250 uA
❐ Sleep mode current of 8 uA
■
Industry standard configurations
❐ Operating voltages:
• CY14C101PA : VCC = 2.4 V to 2.6 V
• CY14B101PA : VCC = 2.7 V to 3.6 V
• CY14E101PA : VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
■
1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
❐ RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ Real time clock (RTC)
❐ Full-featured RTC
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 uA (typical)
■ 40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
❐ 40 MHz clock rate SPI write and read with zero cycle delay
❐ 104 MHz clock rate SPI write and read (with special fast read
instructions)
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ SPI access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
Logic Block Diagram
VCC
VCAP VRTCcap VRTCbat
Overview
The Cypress CY14X101PA combines a 1 Mbit nvSRAM[1] with a
full-featured RTC in a monolithic integrated circuit with serial SPI
interface. The memory is organized as 128 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Serial Number
8x8
Power Control
Block
Manufacture ID/
Product ID
Quantrum Trap
128 K x 8
SLEEP
SI
RDSN/WRSN/RDID
CS
READ/WRITE
SCK
WP
SO
SPI Control Logic
Write Protection
Instruction decoder
WRSR/RDSR/WREN
RDRTC/WRTC
Xin
INT/SQW
Xout
STORE/RECALL/ASENB/ASDISB
Memory Data
&
Address Control
SRAM
128 K x 8
STORE
RECALL
Status Register
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document #: 001-54392 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 21, 2011
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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Contents
Pinouts .............................................................................. 3
Device Operation .............................................................. 4
SRAM Write................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation.................................................... 4
Software STORE Operation ........................................ 5
Hardware STORE and HSB pin Operation ................. 5
RECALL Operation...................................................... 5
Hardware RECALL (Power Up)................................... 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore............................... 5
Serial Peripheral Interface ............................................... 6
SPI Overview............................................................... 6
SPI Modes ......................................................................... 7
SPI Operating Features.................................................... 8
Power-Up .................................................................... 8
Power-On Reset.......................................................... 8
Power Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description.............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Fast Read Status Register (FAST_RDSR) Instruction 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection......................... 11
Write Enable (WREN) Instruction.............................. 11
Write Disable (WRDI) Instruction .............................. 12
Block Protection ........................................................ 12
Hardware Write Protection (WP Pin)......................... 12
Memory Access .............................................................. 12
Read Sequence (READ) Instruction.......................... 12
Fast Read Sequence (FAST_READ) Instruction ...... 12
Write Sequence (WRITE) Instruction ........................ 13
RTC Access..................................................................... 15
READ RTC (RDRTC) Instruction .............................. 15
Fast Read Sequence (FAST_RDRTC) Instruction.... 15
WRITE RTC (WRTC) Instruction............................... 16
nvSRAM Special Instructions........................................ 17
Software STORE (STORE) Instruction ..................... 17
Software RECALL (RECALL) Instruction .................. 17
AutoStore Enable (ASENB) Instruction ..................... 17
AutoStore Disable (ASDISB) Instruction ................... 17
Special Instructions ....................................................... 17
SLEEP Instruction ..................................................... 17
Serial Number ........................................................... 18
Document #: 001-54392 Rev. *C
Device ID...................................................................
HOLD Pin Operation .................................................
Real Time Clock Operation............................................
nvTIME Operation .....................................................
Clock Operations.......................................................
Reading the Clock .....................................................
Setting the Clock .......................................................
Backup Power ...........................................................
Stopping and Starting the Oscillator..........................
Calibrating the Clock .................................................
Alarm .........................................................................
Watchdog Timer ........................................................
Programmable Square Wave Generator...................
Power Monitor ...........................................................
Backup Power Monitor ..............................................
Interrupts ...................................................................
Interrupt Register.......................................................
Flags Register ...........................................................
Best Practices.................................................................
Maximum Ratings...........................................................
DC Electrical Characteristics ........................................
Data Retention and Endurance ....................................
Capacitance ....................................................................
Thermal Resistance........................................................
AC Test Conditions ........................................................
RTC Characteristics .......................................................
AC Switching Characteristics .......................................
AutoStore or Power Up RECALL ..................................
Switching Waveforms ....................................................
Software Controlled STORE/RECALL Cycles..............
Hardware STORE Cycle .................................................
Ordering Information......................................................
Ordering Code Definition...........................................
Package Diagram............................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page ................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Pinouts
Figure 1. Pin Diagram - 16-Pin SOIC
NC
1
16
VCC
VRTCbat
2
15
INT/SQW
Xout
3
14
VCAP
Xin
4
13
SO
Top View
not to scale
WP
5
12
SI
HOLD
6
11
SCK
VRTCcap
7
10
CS
VSS
8
9
HSB
Table 1. Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip Select: Activates the device when pulled LOW. Driving this pin HIGH puts the device in low
power standby mode.
SCK
Input
Serial clock: Runs at speeds up to a maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
SI
Input
Serial input: Pin for input of all SPI instructions and data
SO
Output
WP
Input
Write Protect: Implements hardware write protection in SPI
HOLD
Input
HOLD pin: Suspends Serial Operation
HSB
Input/Output
Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then
a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power Supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
VRTCcap
Power Supply
Capacitor backup for RTC: Left unconnected if VRTCbat is used
VRTCbat
Power Supply
Battery backup for RTC: Left unconnected if VRTCcap is used
Xout
Output
Crystal output connection
Xin
Input
Crystal input connection
INT/SQW
Output
NC
No Connect
VSS
Power Supply
Ground
VCC
Power Supply
Power supply
Document #: 001-54392 Rev. *C
Serial output: Pin for output of data through SPI
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the
watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or
LOW (open drain). In calibration mode, a 512 Hz square wave is driven out. In the square wave
mode, you may select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a
continuous output.
No connect. This pin is not connected to the die.
Page 3 of 44
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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Device Operation
SRAM Read
CY14X101PA is a 1-Mbit serial (SPI) nvSRAM memory with
integrated RTC and SPI interface. All the reads and writes to
nvSRAM happen to the SRAM, which gives nvSRAM the unique
capability to handle infinite writes to the memory. The data in
SRAM is secured by a STORE sequence that transfers the data
in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (VCAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
In CY14X101PA, the 1-Mbit memory array is organized as 128 K
words × 8 bits. The memory can be accessed through a standard
SPI interface that enables very high clock speeds up to 40 MHz
with zero cycle delay read and write cycles. This nvSRAM chip
also supports 104 MHz SPI access speed with a special
instruction for read operation. CY14X101PA supports SPI
modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as
SPI slave. The device is enabled using the Chip Select (CS) pin
and accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
CY14X101PA provides the feature for hardware and software
write protection through the WP pin and WRDI instruction.
CY14X101PA also provides mechanisms for block write
protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the
Status Register. Further, the HOLD pin is used to suspend any
serial communication without resetting the serial sequence.
CY14X101PA uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, CY14X101PA provides four special instructions that allow
access to four nvSRAM specific functions: STORE, RECALL,
AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and three bytes of address. The
data is read out on the SO pin.
Speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, three bytes of address, and one dummy
byte. The data is read out on the SO pin.
CY14X101PA enables burst mode reads to be performed
through SPI. This enables reads on consecutive addresses
without issuing a new READ instruction. When the last address
in memory is reached in burst mode read, the address rolls over
to 0x00000 and the device continues to read.
The SPI read cycle sequence is defined in the Memory Access
section of SPI Protocol Description
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14X101PA allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x00000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
Document #: 001-54392 Rev. *C
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The CY14X101PA STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X101PA is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore Enable (ASENB) Instruction on page 17). If
AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
Page 4 of 44
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PRELIMINARY
to complete the Store. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1, and WPEN in the Status Register.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 32 for the size of the VCAP.
Figure 2. AutoStore Mode
0.1uF
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
VCC
10kOhm
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. In CY14X101PA, a
RECALL may be initiated in two ways: Hardware RECALL,
initiated on power-up and Software RECALL, initiated by a SPI
RECALL instruction.
VCC
CS
CY14C101PA
CY14B101PA
CY14E101PA
VCAP
VSS
Hardware RECALL (Power Up)
VCAP
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM.
A Power Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software STORE Operation
Software RECALL
Software STORE allows the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction regardless of whether or not a
write has been performed since the last NV operation.
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. In
CY14X101PA, this can be done by issuing a RECALL instruction
in SPI.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready/Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Hardware STORE and HSB pin Operation
If the application does not require the AutoStore feature, it can
be disabled in CY14X101PA by using the ASDISB instruction. If
this is done, the nvSRAM does not perform a STORE operation
at power-down.
The HSB pin in CY14X101PA is used to control and
acknowledge STORE operations. If no STORE/RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the CY14X101PA
conditionally initiates a STORE operation after tDELAY duration.
A STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW. The HSB pin also acts as an open drain
driver (internal 100 kΩ weak pull up resistor) that is internally
driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 kΩ pull-up
resistor.
Document #: 001-54392 Rev. *C
Disabling and Enabling AutoStore
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X101PA comes from the factory with AutoStore
Enabled.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power Up RECALL operation cannot
be disabled in any case.
Page 5 of 44
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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Serial Peripheral Interface
Serial Clock (SCK)
SPI Overview
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X101PA provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X101PA can run at speeds up to
104 MHz except RDRTC and READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. CY14X101PA supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X101PA operates as a slave device and may share the SPI
bus with multiple CY14X101PA devices or other SPI devices.
Chip Select (CS)
CY14X101PA allows SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X101PA has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
CY14X101PA requires a 3-byte address for any read or write
operation. However, because the address is only 17 bits, it
implies that the first seven bits that are fed in are ignored by the
device. Although these seven bits are ‘don’t care’, Cypress
recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X101PA uses the standard opcodes for memory accesses.
In addition to the memory accesses, CY14X101PA provides
additional opcodes for the nvSRAM specific functions: STORE,
RECALL, AutoStore Enable, and AutoStore Disable. Refer to
Table 2 on page 9 for details on opcodes.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS and the SO pin remains tri-stated.
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW.
Status Register
The CY14X101PA is selected when the CS pin is LOW. When
the device is not selected, data through the SI pin is ignored and
the serial output pin (SO) remains in a high-impedance state.
CY14X101PA has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Document #: 001-54392 Rev. *C
Page 6 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 3. System Configuration Using SPI nvSRAM
SCK
M OSI
M IS O
SCK
SI
SO
SCK
SI
SO
u C o n tro lle r
C Y 1 4 X 1 0 1 PA
CS
C Y14X 101P A
HO LD
CS
HO LD
CS1
HO LD 1
CS2
HO LD 2
SPI Modes
CY14X101PA device may be driven by a microcontroller with its
SPI peripheral running in either of these two modes:
■
SPI Mode 0 (CPOL=0, CPHA=0)
■
SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a high state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
Figure 4. SPI Mode 0
■
SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. CY14X101PA detects the SPI mode
from the status of SCK pin when device is selected by bringing
the CS pin LOW. If SCK pin is LOW when the device is selected,
SPI Mode 0 is assumed and if SCK pin is HIGH, CY14X101PA
works in SPI Mode 3.
Figure 5. SPI Mode 3
CS
CS
0
1
2
3
4
5
6
7
SCK
SI
The two SPI modes are shown in Figure 4 and Figure 5. The
status of clock when the bus master is in standby mode and not
transferring data is:
0
1
2
3
4
5
6
7
SCK
7
6
5
4
MSB
Document #: 001-54392 Rev. *C
3
2
1
0
LSB
SI
7
MSB
6
5
4
3
2
1
0
LSB
Page 7 of 44
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PRELIMINARY
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
CS must be enabled to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull-up resistor. As
a built in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS must have been
HIGH before going LOW to start the first operation.
As described earlier, nvSRAM performs a Power Up RECALL
operation after power-up and, therefore, all memory accesses
are disabled for tFA duration after power-up. The HSB pin can be
probed to check the Ready/Busy status of nvSRAM after
power-up.
Power-On Reset
A power-on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs a Power Up RECALL operation.
During Power Up RECALL all device accesses are inhibited. The
device is in the following state after POR:
■
Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
■
Standby power mode
■
Not in the Hold condition
■
Status Register state:
❐ Write Enable (WEN) bit is reset to ‘0’.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation
❐ Don’t care bits 4-5 are reset to ‘0’.
Document #: 001-54392 Rev. *C
CY14C101PA
CY14B101PA
CY14E101PA
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
Prior to selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
Power Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down. However, to avoid the possibility
of inadvertent writes during power-down, ensure that the device
is deselected and is in standby power mode and the CS follows
the voltage applied on VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 32. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode after tSB time if a STORE or RECALL cycle is not in
progress. If a STORE/RECALL cycle is in progress, the device
goes into the standby power mode after the STORE/RECALL
cycle is completed. In the standby power mode the current drawn
by the device drops to ISB.
Page 8 of 44
[+] Feedback
CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
SPI Functional Description
The CY14X101PA uses an 8-bit instruction register. Instructions and their operation codes are listed in Table 2. All instructions,
addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS transition. There are, in all, 21 SPI instructions
that provide access to most of the functions in nvSRAM. Further, the WP, HOLD, and HSB pins provide additional functionality driven
through hardware.
Table 2. Instruction Set
Instruction
Category
Instruction
Name
Status Register Control Instructions
RDSR
FAST_RDSR
Status Register access
WRSR
Write protection and block WREN
protection
WRDI
SRAM Read/Write Instructions
READ
Memory access
FAST_READ
WRITE
RTC Read/Write Instructions
RDRTC
FAST_RDRTC
RTC access
WRTC
Opcode
0000 0101
0000 1001
Operation
0000 0001
0000 0110
0000 0100
Read Status Register
Fast Status Register read - SPI clock >40
MHz
Write Status Register
Set Write Enable latch
Reset Write Enable latch
0000 0011
0000 1011
0000 0010
Read data from memory array
Fast read - SPI clock >40 MHz
Write data to memory array
0001 0011
0001 1101
0001 0010
Read RTC registers
Fast RTC register read - SPI clock > 25
MHz
Write RTC registers
0011 1100
0110 0000
0101 1001
0001 1001
Software STORE
Software RECALL
AutoStore enable
AutoStore disable
1011 1001
1100 0010
1100 0011
1100 1001
Sleep mode enable
Write serial number
Read serial number
Fast serial number read - SPI clock > 40
MHz
Read manufacturer JEDEC ID and
product ID
Fast manufacturer JEDEC ID and
product ID Read - SPI clock > 40 MHz
Special NV Instructions
STORE
RECALL
nvSRAM special functions
ASENB
ASDISB
Special Instructions
Sleep
SLEEP
WRSN
RDSN
Serial number
FAST_RDSN
Device ID read
Reserved
RDID
1001 1111
FAST_RDID
1001 1001
- Reserved -
0001 1110
The SPI instructions in CY14X101PA are divided based on their
functionality in these types:
❐ Status Register control instructions:
• Status Register access: RDSR, FAST_RDSR and WRSR
instructions
• Write protection and block protection: WREN and WRDI
instructions along with WP pin and WEN, BP0, and BP1
bits
❐ SRAM Read/Write instructions
Document #: 001-54392 Rev. *C
• Memory access: READ, FAST_READ, and WRITE instructions
❐ RTC Read/Write instructions
• RTC access: RDRTC, FAST_RDRTC and WRTC
instructions
❐ Special NV instructions
• nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
❐ Special instructions: SLEEP, WRSN, RDSN, FAST_RDSN,
RDID, FAST_RDID
Page 9 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Status Register
The Status Register bits are listed in Table 3. The Status Register
consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the
Ready/Busy status while a nvSRAM STORE or Software
RECALL cycle is in progress. The Status Register can be
modified by WRSR instruction and read by RDSR or
FAST_RDSR instruction. However, only the WPEN, BP1, and
BP0 bits of the Status Register can be modified by using the
WRSR instruction. The WRSR instruction has no effect on WEN
and RDY bits. The default value shipped from the factory for
WEN, BP0, BP1, bits 4 -5, SNL and WPEN is ‘0’.
SNL (bit 6) of the Status Register is used to lock the serial
number written using the WRSN instruction. The serial number
can be written using the WRSN instruction multiple times while
this bit is still '0'. When set to '1', this bit prevents any modification
to the serial number. This bit is factory programmed to '0' and can
only be written to once. After this bit is set to '1', it can never be
cleared to '0'.
Table 3. Status Register Format
Bit 7
WPEN (0)
Bit 6
SNL (0)
Bit 5
X (0)
Bit 4
X (0)
Bit 3
BP1 (0)
Bit 2
BP0 (0)
Bit 1
WEN (0)
Bit 0
RDY
Table 4. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is write enabled. This bit defaults to 0 (disabled) on power-up.
WEN = '1' --> Write enabled
WEN = '0' --> Write disabled
Bit 2 (BP0)
Block Protect bit ‘0’
Used for block protection. For details see Table 5 on page 12.
Bit 3 (BP1)
Block Protect bit ‘1’
Used for block protection. For details see Table 5 on page 12.
Bit 4-5
Don’t care
Bits are writeable and volatile. On power-up, bits are written with ‘0’.
Bit 6 (SNL)
Serial Number Lock
Bit 7(WPEN) Write Protect Enable bit
Set to '1' for locking serial number
Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12.
Read Status Register (RDSR) Instruction
The Read Status Register instruction provides access to the
Status Register at SPI frequency up to 40 MHz. This instruction
is used to probe the Write Enable status of the device or the
Ready status of the device. RDY bit is set by the device to ‘1’
whenever a STORE or Software RECALL cycle is in progress.
The block protection and WPEN bits indicate the extent of
protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Fast Read Status Register (FAST_RDSR) Instruction
The FAST_RDSR instruction allows you to read the Status
Register at SPI frequency above 40 MHz and up to 104 MHz
(max).This instruction is used to probe the Write Enable status
of the device or the Ready status of the device. RDY bit is set by
the device to ‘1’ whenever a STORE or Software RECALL cycle
is in progress. The block protection and WPEN bits indicate the
extent of protection employed.
Document #: 001-54392 Rev. *C
This instruction is issued after the falling edge of CS using the
opcode for RDSR followed by a dummy byte.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used
to select one of four levels of block protection. Further, WPEN bit
must be set to ‘1’ to enable the use of Write Protect (WP) pin.
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by eight bits of data to be
stored in the Status Register. Since only bits 2, 3, and 7 can be
modified by WRSR instruction, it is recommended to leave the
bits 4-5 as ‘0’ while writing to the Status Register.
Note In CY14X101PA, the values written to Status Register are
saved to nonvolatile memory only after a STORE operation. If
AutoStore is disabled, any modifications to the Status Register
must be secured by performing a Software STORE operation.
Page 10 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 6. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
0
0
0
0
0
1
0
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Figure 7. Fast Read Status Register (FAST_RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1
X
X
0
1
2
3
4
5
6
7
SCK
Dummy Byte
Op-Code
SI
0
0
0
0
1
0
0
X
X
X
X
X
0
X
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
SI
SO
0
0
0
0
0
0
0
X
X D3 D2 X
X
LSB
HI-Z
Write Protection and Block Protection
CY14X101PA provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE, and WRTC) and nvSRAM special instruction (STORE,
RECALL, ASENB, ASDISB) need the write to be enabled (WEN
bit = ‘1’) before they can be issued.
Document #: 001-54392 Rev. *C
1 D7 X
MSB
Write Enable (WREN) Instruction
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRTC, or nvSRAM special instruction
must therefore be preceded by a Write Enable instruction. If the
device is not write enabled (WEN = ‘0’), it ignores the write
instructions and returns to the standby state when CS is brought
HIGH. A new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR, WRITE, or
WRTC) or nvSRAM special instruction (STORE, RECALL,
ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is
done to provide protection from any inadvertent writes.
Therefore, WREN instruction needs to be used before a new
write instruction can be issued
Page 11 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
.
Figure 9. WREN Instruction
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Table 6 summarizes all the protection features provided in the
CY14X101PA.
HI-Z
SO
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Table 6. Write Protection Operation
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ to protect the device against inadvertent writes. This
instruction is issued following the falling edge of CS followed by
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
WP
Unprotected Status
WEN Protected
Blocks
Blocks
Register
X
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
1
Protected
Writable
Protected
1
HIGH
1
Protected
Writable
Writable
Memory Access
CS
0
1
2
3
4
5
6
7
SCK
SI
WPEN
0
SO
0
0
0
0
1
0
0
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) Instruction
HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
Block Protect bits.
Table 5. Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
0
0
0
None
1 (1/4)
0
1
0x18000-0x1FFFF
2 (1/2)
1
0
0x10000-0x1FFFF
3 (All)
1
1
0x00000-0x1FFFF
Hardware Write Protection (WP Pin)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
Document #: 001-54392 Rev. *C
The read operations on CY14X101PA are performed by giving
the instruction on the SI pin and reading the output on SO pin.
The following sequence needs to be followed for a read
operation: After the CS line is pulled LOW to select a device, the
read opcode is transmitted through the SI line followed by three
bytes of address. The most significant address byte contains
A16 in bit 0 and other bits as don’t cares. Address bits A15 to A0
are sent in the following two address bytes. After the last address
bit is transmitted on the SI pin, the data (D7-D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
CY14X101PA allows reads to be performed in bursts through
SPI which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x1FFFF) is reached, the address rolls over to
0x00000 and the device continues to read.
Note READ instruction operates up to Max of 40 MHz SPI
frequency.
Fast Read Sequence (FAST_READ) Instruction
The FAST_READ instruction allows you to read memory at SPI
frequency above 40 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS LOW, the
FAST_READ instruction is then written to SI, followed by 3
address byte containing the17 bit address (A16 -A0) and then a
dummy byte.
Page 12 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
A16 in bit 0 with other bits being don’t cares. Address bits A15 to
A0 are sent in the following two address bytes.
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_READ instruction. When the highest
address in the memory array is reached, address counter rolls
over to start address 0x00000 and thus allowing the read
sequence to continue indefinitely. The FAST_READ instruction
is terminated by driving CS HIGH at any time during data output.
CY14X101PA allows writes to be performed in bursts through
SPI which can be used to write consecutive addresses without
issuing a new WRITE instruction. If only one byte is to be written,
the CS line must be driven HIGH after the D0 (LSB of data) is
transmitted. However, if more bytes are to be written, CS line
must be held LOW and address incremented automatically. The
following bytes on the SI line are treated as data bytes and
written in the successive addresses. When the last data memory
address (0x1FFFF) is reached, the address rolls over to 0x00000
and the device continues to write.
Note FAST_READ instruction operates up to maximum of
104 MHz SPI frequency.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Write Sequence (WRITE) Instruction
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
The write operations on CY14X101PA are performed through the
SI pin. To perform a write operation, if the device is write
disabled, then the device must first be write enabled through the
WREN instruction. When the writes are enabled (WEN = ‘1’),
WRITE instruction is issued after the falling edge of CS. A
WRITE instruction constitutes transmitting the WRITE opcode
on SI line followed by 3-bytes of address and the data (D7-D0)
which is to be written. The most significant address byte contains
Figure 11. Read Instruction Timing
CS
1
2
3
4
5
6
1
0
7
2
3
4
5
6
7
~
~ ~
~
0
SCK
Op-Code
SI
0
0
0
0
0
20 21 22 23 0
1
2
3
4
5
6
7
17-bit Address
0
1
1
0 0
MSB
0
0
0
0
0 A16
A3 A2 A1 A0
LSB
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Data
MSB
Figure 12. Burst Mode Read Instruction Timing
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Op-Code
0
0
0
0
0
1
2
3
4
5
6
7
0
7
0
1
2
3
4
5
6
7
17-bit Address
0
1
1
0
0
MSB
0
0
0
0
0
~
~
SI
20 21 22 23 0
~
~
0
SCK
~
~
CS
A16
A3 A2 A1 A0
LSB
Data Byte N
SO
~
~
Data Byte 1
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-54392 Rev. *C
LSB
MSB
LSB
Page 13 of 44
[+] Feedback
CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 13. Fast Read Instruction Timing
CS
1
2
3
4
5
6
1
0
7
2
3
4
5
6
Op-Code
SI
0
0
0
0
1
20 21 22 23 24 25 26 27 28 29 30 31 0
7
~
~ ~
~
0
SCK
1 1
0 0
MSB
0
0
0
0
0 A16
A3 A2 A1 A0 X X
LSB
X
X X
X X
3
4
5
6
7
X
HI-Z
SO
2
Dummy Byte
17-bit Address
0
1
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Data
MSB
Figure 14. Write Instruction Timing
CS
1
2
3
4
5
0
7
6
1
2
3
4
5
6
Op-Code
SI
0
0
0
0
0
7
~
~ ~
~
0
SCK
20 21
22 23
0
1
2
3
4
5
6
7
17-bit Address
0
1
0
0
0
0
0
0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A16
0
MSB
LSB MSB
LSB
Data
HI-Z
SO
Figure 15. Burst Mode Write Instruction Timing
CS
2
3
4
5
6
7
0
1
2
3
4
5
6
7
20 21 22 23 0
1
2
3
4
5
6
7
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
A16
Document #: 001-54392 Rev. *C
2
3
4
5
6
7
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
MSB
SO
1
~
~
0
~
~
SI
17-bit Address
0
Data Byte N
Data Byte 1
Op-Code
7
~
~
1
~
~
0
SCK
LSB
HI-Z
Page 14 of 44
[+] Feedback
CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
RTC Access
The R bit in RTC flags register must be set to ‘1’ before reading
RTC time keeping registers to avoid reading transitional data.
Modifying the RTC flag registers requires a Write RTC cycle. The
R bit must be cleared to '0' after completion of the read operation.
CY14X101PA uses 16 registers for RTC. These registers can be
read out or written to by accessing all 16 registers in burst mode
or accessing each register, one at a time. The RDRTC,
FAST_RDRTC, and WRTFC instructions are used to access the
RTC.
The easiest way to read RTC registers is to perform RDRTC in
burst mode. The read may start from the first RTC register (0x00)
and the CS must be held LOW to allow the data from all 16 RTC
registers to be transmitted through the SO pin.
Note RDRTC instruction operates at a maximum clock
frequency of 25 MHz. The opcode cycles, address cycles and
data out cycles need to run at 25 MHz for the instruction to work
properly.
All the RTC registers can be read in burst mode by issuing the
RDRTC and FAST_RDRTC instruction and reading all 16 bytes
without bringing the CS pin HIGH. The ‘R’ bit must be set while
reading the RTC timekeeping registers to ensure that transitional
values of time are not read.
Writes to the RTC register are performed using the WRTC
instruction. Writing RTC timekeeping registers and control
registers, except for the flags register needs the ‘W’ bit of the
flags register to be set to ‘1’. The internal counters are updated
with the new date and time setting when the ‘W’ bit is cleared to
‘0’. All the RTC registers can also be written in burst mode using
the WRTC instruction.
Fast Read Sequence (FAST_RDRTC) Instruction
The FAST_RDRTC instruction allows you to read memory at a
SPI frequency above 25 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS LOW, the
FAST_READ instruction is then written to SI, followed by 8 bit
address and a dummy byte.
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
automatically increments to the next higher address after each
byte of data is output. The entire memory array can therefore be
read with a single FAST_RDRTC instruction. When the highest
address (0x0F) in the memory array is reached, the address
counter rolls over to start address 0x00 and thus allowing the
read sequence to continue indefinitely. The FAST_RDRTC
instruction is terminated by driving CS HIGH at any time during
data output.
Note FAST_READ instruction operates up to Max of 104 MHz
SPI frequency.
READ RTC (RDRTC) Instruction
Read RTC (RDRTC) instruction allows you to read the contents
of RTC registers at SPI frequency upto 25 MHz. Reading the
RTC registers through the SO pin requires the following
sequence: After the CS line is pulled LOW to select a device, the
RDRTC opcode is transmitted through the SI line followed by
eight address bits for selecting the register. Any data on the SI
line after the address bits is ignored. The data (D7-D0) at the
specified address is then shifted out onto the SO line. RDRTC
also allows burst mode read operation. When reading multiple
bytes from RTC registers, the address rolls over to 0x00 after the
last RTC register address (0x0F) is reached.
Figure 16. Read RTC (RDRTC) Instruction Timing
CS
0
1
2
3
4
5
6
1
7
0
1
0 0
MSB
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
0
0
SO
0
1
0
0
1
HI-Z
0
0 A3 A2 A1 A0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-54392 Rev. *C
Data
LSB
Page 15 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 17. Fast RTC Read (FAST_RDRTC) Instruction Timing
CS
0
1
2
3
4
5
6
1
0
7
2
4
3
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Op-Code
SI
0
0
0
1
1
Dummy Byte
1
0
1
0 0
MSB
0
0 A3 A2 A1 A0 X X
LSB
X X
X
X
X
X
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
bytes of data. WRTC allows burst mode write operation. When
writing more than one registers in burst mode, the address rolls
over to 0x00 after the last RTC address (0x0F) is reached.
WRITE RTC (WRTC) Instruction
WRITE RTC (WRTC) instruction allows you to modify the
contents of RTC registers. The WRTC instruction requires the
WEN bit to be set to '1' before it can be issued. If WEN bit is '0',
a WREN instruction needs to be issued before using WRTC.
Writing RTC registers requires the following sequence: After the
CS line is pulled LOW to select a device, WRTC opcode is
transmitted through the SI line followed by eight address bits
identifying the register which is to be written to and one or more
Note that writing to RTC timekeeping and control registers
require the W bit to be set to '1'. The values in these RTC
registers take effect only after the ‘W’ bit is cleared to '0'. Write
Enable bit (WEN) is automatically cleared to ‘0’ after completion
of the WRTC instruction.
Figure 18. Write RTC (WRTC) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
0
0
0
1
0
0
4-bit Address
1
0
0
0
0
0
A3 A2 A1 A0
MSB
SO
Document #: 001-54392 Rev. *C
D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
Data
LSB
HI-Z
Page 16 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
nvSRAM Special Instructions
.
Figure 20. Software RECALL Operation
CY14X101PA provides four special instructions that allow
access to the nvSRAM specific functions: STORE, RECALL,
ASDISB, and ASENB. Table 7 lists these instructions.
Function Name
Opcode
STORE
0011 1100
Software STORE
RECALL
0110 0000
Software RECALL
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable
Operation
Software STORE (STORE) Instruction
When a STORE instruction is executed, CY14X101PA performs
a Software STORE operation. The STORE operation is
performed regardless of whether or not a write has taken place
since the last STORE or RECALL operation.
Figure 19. Software STORE Operation
CS
1
2
3
4
5
6
0
1
1
3
4
5
6
7
SI
0
1
1
0
0
0
0
0
HI-Z
SO
AutoStore Enable (ASENB) Instruction
The AutoStore Enable instruction enables the AutoStore on
CY14X101PA. This setting is not nonvolatile and needs to be
followed by a STORE sequence if this is desired to survive the
power cycle.
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASENB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASENB
instruction.
1
1
0
0
0
1
2
3
4
5
6
7
SCK
HI-Z
SO
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’).The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Software RECALL (RECALL) Instruction
When a RECALL instruction is executed, CY14X101PA
performs a Software RECALL operation. To issue this
instruction, the device must be write enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Figure 22. AutoStore Disable Operation
.
SI
0
1
0
SO
1
1
0
0
1
HI-Z
AutoStore Disable (ASDISB) Instruction
AutoStore is enabled by default in CY14X101PA. The AutoStore
Disable instruction disables the AutoStore on CY14X101PA.
This setting is not nonvolatile and needs to be followed by a
STORE sequence if this is desired to survive the power cycle.
To issue this instruction, the device must be write enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASDISB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASDISB
instruction.
Special Instructions
SLEEP Instruction
CS
0
1
2
3
4
5
6
7
SCK
SO
2
CS
0
SI
1
Figure 21. AutoStore Enable Operation
7
SCK
SI
0
SCK
Table 7. nvSRAM Special Instructions
0
CS
0
0
0
1
1
HI-Z
Document #: 001-54392 Rev. *C
0
0
1
SLEEP instruction puts the nvSRAM in sleep mode. When the
SLEEP instruction is issued and CS is brought HIGH, the
nvSRAM performs a STORE operation to secure the data to
nonvolatile memory and then enters into sleep mode. The device
starts consuming IZZ current after tSLEEP time from the instance
when SLEEP instruction is registered. The device is not accessible for normal operations after SLEEP instruction is issued.
Once in sleep mode, the SCK and SI pins are ignored and SO
will be Hi-Z but device continues to monitor the CS pin.
Page 17 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
consists of a two byte Customer ID, followed by five bytes of
unique serial number and one byte of CRC check. However,
nvSRAM does not calculate the CRC and it is up to the system
designer to utilize the eight byte memory space in whatever
manner desired. The default value for eight byte locations are set
to ‘0x00’.
To wake the nvSRAM from the sleep mode, the device must be
selected by toggling the CS pin from HIGH to LOW. The device
wakes up and is accessible for normal operations after tWAKE
duration after a falling edge of CS pin is detected.
Note Whenever nvSRAM enters into sleep mode, it initiates
nonvolatile STORE cycle which results in an endurance cycle per
sleep command execution. A STORE cycle starts only if a write
to the SRAM has been performed since the last STORE or
RECALL cycle.
Figure 23. Sleep Mode Entry
WRSN (Serial Number Write) Instruction
The serial number can be written using the WRSN instruction. To
write serial number the write must be enabled using the WREN
instruction. The WRSN instruction can be used in burst mode to
write all the 8 bytes of serial number.
t
SLEEP
The serial number is locked using the SNL bit of the Status
Register. Once this bit is set to '1', no modification to the serial
number is possible. After the SNL bit is set to '1', using the WRSN
instruction has no effect on the serial number.
CS
0
1
2
3
4
5
6
7
SCK
SI
1
0
1
1
1
0
0
A STORE operation (AutoStore or Software STORE) is required
to store the serial number in nonvolatile memory. If AutoStore is
disabled, you must perform a Software STORE operation to
secure and lock the serial number. If SNL bit is set to ‘1’ and is
not stored (AutoStore disabled), the SNL bit and serial number
defaults to ‘0’ at the next power cycle. If SNL bit is set to ‘1’ and
is stored, the SNL bit can never be cleared to ‘0’. This instruction
requires the WEN bit to be set before it can be executed. The
WEN bit is reset to '0' after completion of this instruction.
1
HI-Z
SO
Serial Number
The serial number is an 8-byte programmable memory space
provided to you to uniquely identify this device. It typically
Figure 24. WRSN Instruction
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI
1
1
0
0
0
0
1
0
Document #: 001-54392 Rev. *C
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0
MSB
SO
56 57 58 59 60 61 62 63
Byte - 8
Op-Code
~
~
0
SCK
~
~
CS
D7 D6 D5 D4 D3 D2 D1 D0
8-Byte Serial Number
LSB
HI-Z
Page 18 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
RDSN (Serial Number Read) Instruction
The serial number is read using RDSN instruction at SPI frequency upto 40 MHz. A serial number read may be performed in burst
mode to read all the eight bytes at once. After the last byte of serial number is read, the device does not loop back. RDSN instruction
can be issued by shifting the op-code for RDSN in through the SI pin of nvSRAM after CS goes LOW. This is followed by nvSRAM
shifting out the eight bytes of serial number through the SO pin.
Figure 25. RDSN Instruction
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
~
~
CS
56 57 58 59 60 61 62 63
Op-Code
SI
1
1
0
0
0
0
1
0
Byte - 1
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
~
~
Byte - 8
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
LSB
8-Byte Serial Number
FAST_RDSN (Fast Serial Number Read) Instruction
The FAST_RDSN instruction is used to read serial number at SPI frequency above 40 MHz and up to 104 MHz (max). A serial number
read may be performed in burst mode to read all the eight bytes at once. After the last byte of serial number is read, the device does
not loop back. FAST_RDSN instruction can be issued by shifting the op-code for FAST_RDSN in through the SI pin of nvSRAM
followed by dummy byte after CS goes LOW. This is followed by nvSRAM shifting out the eight bytes of serial number through the SO
pin
Figure 26. FAST_RDSN Instruction
0
1
2
3
4
5
7
6
8
9
10 11 12 13
14 15
0
1
2
3
4
5
6
7
SCK
Op-Code
SI
1
1
0
0
1
0
~
~
CS
56 57 58 59 60 61 62 63
Dummy Byte
0
1
X
X
X
X
X
X X
X
Byte - 1
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-54392 Rev. *C
~
~
Byte - 8
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
8-Byte Serial Number
LSB
Page 19 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Device ID
Device ID is a 4-byte read only code identifying a type of product uniquely. This includes the product family code, configuration, and
density of the product.
Table 8. Device ID
Bits
#of Bits
31 - 21
(11 bits)
20 - 7
(14 bits)
6-3
(4 bits)
2-0
(3 bits)
Device
Manufacturer ID
Product
ID
Density
ID
Die Rev
CY14C101PA
00000110100
00001110000001
0100
000
CY14B101PA
00000110100
00001110010001
0100
000
CY14E101PA
00000110100
00001110100001
0100
000
The device ID is divided into four parts as shown in Table 8:
1. Manufacturer ID (11 bits)
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Cypress’s manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is:
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID for device is shown in the Table 8.
3. Density ID (4 bits)
4. Die Rev (3 bits)
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
RDID (Device ID Read) Instruction
This instruction is used to read the JEDEC assigned manufacturer ID and product ID of the device at SPI frequency upto
40 MHz. This instruction can be used to identify a device on the
bus. RDID instruction can be issued by shifting the op-code for
RDID in through the SI pin of nvSRAM after CS goes LOW. This
is followed by nvSRAM shifting out the four bytes of device ID
through the SO pin.
The 4 bit density ID is used as shown in Table 8 for indicating the
1Mb density of the product.
Figure 27. RDID Instruction
CS
0 1
2
3 4
5
6
7 0 1
2
3 4
5
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Op-Code
SI
1 0 0 1 1 1 1
1
Byte - 4
SO
HI-Z
Byte - 3
Byte - 2
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
4-Byte Device ID
Document #: 001-54392 Rev. *C
Page 20 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
FAST_RDID (Fast Device ID Read) Instruction
The FAST_RDID instruction allows you to read the JEDEC assigned manufacturer ID and product ID at SPI frequency above 40 MHz
and up to 104 MHz (Max). FAST_RDID instruction can be issued by shifting the op-code for FAST_RDID in through the SI pin of
nvSRAM followed by dummy byte after CS goes LOW. This is followed by nvSRAM shifting out the four bytes of device ID through
the SO pin.
Figure 28. FAST_RDID Instruction
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Op-Code
SI
1 0 0 1 1
Dummy Byte
0 0
1 X X X X X X X X
Byte - 4
SO
HI-Z
Byte - 3
Byte - 2
Byte - 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
4-Byte Device ID
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. To
resume serial communication, the HOLD pin must be brought
HIGH when the SCK pin is LOW (SCK may toggle during HOLD).
While the device serial communication is paused, inputs to the
SI pin are ignored and the SO pin is in the high-impedance state.
This pin can be used by the master with the CS pin to pause the
serial communication by bringing the pin HOLD LOW and
deselecting an SPI slave to establish communication with
another slave device, without the serial communication being
Document #: 001-54392 Rev. *C
reset. The communication may be resumed at a later point by
selecting the device and setting the HOLD pin HIGH.
Figure 29. HOLD Operation
CS
SCK
~
~
~ ~
HOLD Pin Operation
HOLD
SO
Page 21 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Real Time Clock Operation
nvTIME Operation
The CY14X101PA offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. The RTC
registers occupy a separate address space from nvSRAM and
are accessible through RDRTC and WRTC instructions on
register addresses 0x00 to 0x0F. Internal double buffering of the
clock and the timer information registers prevents accessing
transitional internal clock data during a read or write operation.
Double buffering also circumvents disrupting normal timing
counts or the clock accuracy of the internal clock when accessing
clock data. Clock and alarm registers store data in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14X101PA time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x00), and does not restart until a ‘0’
is written to the read bit. The RTC registers are read while the
internal clock continues to run. After a ‘0’ is written to the read bit
(‘R’), all RTC registers are simultaneously updated within 20 ms.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ stops
updates to the time keeping registers and enables the time to be
set. The correct day, date, and time is then written into the
registers and must be in 24-hour BCD format. The time written
is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping
registers to the actual clock counters, after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,
alarm, calibration, and interrupt registers are transferred to the
RTC time keeping counters in tRTCp time. These counter values
must be saved to nonvolatile memory either by initiating a
Software/Hardware STORE or AutoStore operation. While
working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Document #: 001-54392 Rev. *C
Backup Power
The RTC in the CY14X101PA is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14X101PA consumes a 0.35 µA
(Typ) at room temperature. The user must choose capacitor or
battery values according to the application.
Backup time values based on maximum current specifications
are shown in Table 9. Nominal backup times are approximately
two times longer.
Table 9. RTC Backup Time
Capacitor Value
Backup Time
(CY14B101PA)
0.1F
60 hours
0.47F
12 days
1.0F
25 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3-V lithium is recommended and the CY14X101PA
sources current only from the battery when the primary power is
removed. However, the battery is not recharged at any time by
the CY14X101PA. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x08 controls the
enable and disable of the oscillator. This bit is nonvolatile and is
shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14X101PA has the ability to detect
oscillator failure when system power is restored. This is recorded
in the Oscillator Fail Flag (OSCF) of the flags register at the
address 0x00. When the device is powered on (VCC goes above
VSWITCH) the OSCEN bit is checked for ‘enabled’ status. If the
OSCEN bit is enabled and the oscillator is not active within the
first 5 ms, the OSCF bit is set to ‘1’. The system must check for
this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see Setting the Clock on page 22), which is
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Page 22 of 44
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PRELIMINARY
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit ‘W’ (in the flags register at 0x00)
to a ‘1’ to enable writes to the flags register. Write a ‘0’ to the
OSCF bit and then reset the write bit to ‘0’ to disable writes.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +20 ppm to +35 ppm. However,
CY14X101PA employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5
seconds to -5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in calibration register at 0x08. The
calibration bits occupy the five lower order bits in the calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the calibration register.
To determine the required calibration, the CAL bit in the flags
register (0x00) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the calibration register to offset
this error.
Note Setting or changing the calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x00) to ‘1’ to enable writes to the flags register. Write a value to
CAL, and then reset the write bit to ‘0’ to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x01-5) with the corresponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
Document #: 001-54392 Rev. *C
CY14C101PA
CY14B101PA
CY14E101PA
There are four alarm match fields: date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x00 indicates that a date or time match has occurred. The AF
bit is set to ‘1’ when a match occurs. Reading the flags register
clears the alarm flag bit (and all others). A hardware interrupt pin
may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in the flags
register - 0x00) to ‘1’ to enable writes to alarm registers. After
writing the alarm value, clear the ‘W’ bit back to ‘0’ for the
changes to take effect.
Note CY14X101PA requires the alarm match bit for seconds
(0x02 - D7) to be set to ‘0’ for proper operation of Alarm Flag and
Interrupt.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The timer consists of a loadable register and a free running
counter. On power-up, the watchdog time out value in register
0x07 is loaded into the counter load register. Counting begins on
power-up and restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to ‘1’. The counter is compared
to the terminal value of ‘0’. If the counter reaches this value, it
causes an internal flag and an optional interrupt output. You can
prevent the time out interrupt by setting WDS bit to ‘1’ prior to the
counter reaching ‘0’. This causes the counter to reload with the
watchdog time out value and to be restarted. As long as the user
sets the WDS bit prior to the counter reaching the terminal value,
the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables you to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 30 on page 24. Note that
setting the watchdog time out value to ‘0’ disables the watchdog
function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the flag registers.
Page 23 of 44
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PRELIMINARY
.
Backup Power Monitor
Figure 30. Watchdog Timer Block Diagram
Clock
Divider
Oscillator
32.768 KHz
1 Hz
32 Hz
Counter
Zero
Compare
WDF
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
CY14C101PA
CY14B101PA
CY14E101PA
Watchdog
Register
Programmable Square Wave Generator
The square wave generator block uses the crystal output to
generate a desired frequency on the INT pin of the device. The
output frequency can be programmed to be one of these:
1. 1Hz
2. 512 Hz
3. 4096 Hz
4. 32768 Hz
The square wave output is not generated while the device is
running on backup power.
Power Monitor
The CY14X101PA provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the section “AutoStore Operation” on page 4,
when VSWITCH is reached as VCC decays from power loss, a data
STORE operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write operations to nvSRAM are inhibited and the RTC functions are not
available to the user. The RTC clock continues to operate in the
background. The updated RTC time keeping registers are
available to the user after VCC is restored to the device (see
“AutoStore or Power Up RECALL” on page 37).
The CY14X101PA provides a backup power monitoring system
which detects the backup power (either battery or capacitor
backup) failure. The backup power fail flag (BPF) is issued on
the next power-up in case of backup power failure. The BPF flag
is set in the event of backup voltage falling lower than VBAKFAIL.
The backup power is monitored even while the RTC is running
in backup mode. Low voltage detected during backup mode is
flagged through the BPF flag. BPF can hold the data only until a
defined low level of the back-up voltage (VDR).
Interrupts
The CY14X101PA has a flags register, interrupt register, and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the interrupt
register (0x06). In addition, each has an associated flag bit in the
flags register (0x00) that the host processor uses to determine
the cause of the interrupt. The INT pin driver has two bits that
specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the section Interrupt Register.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
Note CY14X101PA generates valid interrupts only after the
Power Up RECALL sequence is completed. All events on INT pin
must be ignored for tFA duration after powerup.
Interrupt Register
Watchdog Interrupt Enable (WIE): When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in flags register.
Alarm Interrupt Enable (AIE): When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flag in flags register.
Power Fail Interrupt Enable (PFE): When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in flags
register.
Square Wave Enable (SQWE): When set to ‘1’, a square wave
of programmable frequency is generated on the INT pin. The
frequency is decided by the SQ1 and SQ0 bits of the interrupts
register. This bit is nonvolatile and survives power cycle. The
SQWE bit over rides all other interrupts. However, CAL bit will
take precedence over the square wave generator. This bit
defaults to ‘0’ from factory.
Document #: 001-54392 Rev. *C
Page 24 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
High/Low (H/L): When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives HIGH only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L): When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags register is read.
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags register is read. If the INT pin is used as a
host reset, the flags register is not read during a reset.
This summary table shows the state of the INT pin.
Table 11. State of the INT pin
CAL
SQWE
WIE/AIE/
PFE
INT Pin Output
1
X
X
512 Hz
SQ1 and SQ0. These bits are used together to fix the frequency
of square wave on INT pin output when SQWE bit is set to ‘1’.
These bits are nonvolatile and survive power cycle. The output
frequency is decided as per the following table.
0
1
X
Square Wave
Output
0
0
1
Alarm
Table 10. SQW Output Selection
0
0
0
HI-Z
SQ1
SQ0
Frequency
Comment
0
0
1 Hz
1 Hz signal
0
1
512 Hz
Useful for calibration
1
0
4096 Hz
4 KHz clock output
1
1
32768 Hz
Oscillator output
frequency
When an enabled interrupt source activates the INT pin, an
external host reads the flag registers to determine the cause.
Remember that all flag are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
Document #: 001-54392 Rev. *C
Flags Register
The flags register has three flag bits: WDF, AF, and PF, which
can be used to generate an interrupt. These flag are set by the
watchdog timeout, alarm match, or power fail monitor
respectively. The processor can either poll this register or enable
interrupts to be informed when a flag is set. These flags are
automatically reset after the register is read. The flags register is
automatically loaded with the value 0x00 on power-up (except
for the OSCF bit. See “Stopping and Starting the Oscillator” on
page 22.)
Page 25 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 31. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768 KHz (12.5 pF)
C1 = 10 pF
C2 = 67 pF
Xout
C1
Y1
Xin
C2
Note: The recommended values for C1 and C2 include
board trace capacitance.
Figure 32. Interrupt Block Diagram
WIE
Watchdog
Timer
WDF
Power
Monitor
PFE
PF
AIE
P/L
512 Hz
Clock
AF
Pin
Driver
Mux
Clock
Alarm
Square
Wave
HI-Z
Control
SEL Line
VCC
INT
H/L
VSS
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
SQWE - Square wave enable
SQWE
Priority
CAL
Encoder
WIE/PIE/
AIE
Document #: 001-54392 Rev. *C
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Table 12. RTC Register Map[2, 3]
Register
BCD Format Data
D7
0x0F
0x0E
D6
D5
D4
D3
D2
D1
10s years
0
0
0x0D
0
0
0x0C
0
0
0x0B
0
0
0x0A
0
0
10s
months
10s day of month
0
0
D0
Years
Years: 00–99
Months
Months: 01–12
Day of month
Day of month: 01–31
0
Day of week
10s hours
10s minutes
Day of week: 01–07
Hours
Hours: 00–23
Minutes
Minutes: 00–59
0x09
0
0x08
OSCEN
(0)
0x07
WDS (0) WDW (0)
0x06
WIE (0)
AIE (0)
0x05
M (1)
0
10s alarm date
Alarm day
Alarm, day of month: 01–31
0x04
M (1)
0
10s alarm hours
Alarm hours
Alarm, hours: 00–23
0x03
M (1)
10 alarm minutes
Alarm minutes
Alarm, minutes: 00–59
0x02
M (1)
10 alarm seconds
Alarm seconds
Alarm, seconds: 00–59
0x01
0x00
10s seconds
Function/Range
0
Seconds
Cal sign
(0)
AF
Watchdog [4]
WDT (000000)
PFE (0)
SQWE
(0)
H/L (1)
10s centuries
WDF
Seconds: 00–59
Calibration values [4]
Calibration (00000)
PF
P/L (0)
SQ1
(0)
SQ0
(0)
Centuries
OSCF[5]
BPF[5]
CAL (0)
W (0)
Interrupts [4]
Centuries: 00–99
R (0)
Flags [4]
Notes
2. ( ) designates values shipped from the factory.
3. The unused bits of RTC registers are reserved for future use and should be set to ‘0’
4. This is a binary value, not a BCD value.
5. When user resets OSCF and BPF flag bits, the flags register will be updated after tRTCp time.
Document #: 001-54392 Rev. *C
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Table 13. Register Map Detail
Time Keeping - Years
D7
D6
0x0F
D5
D4
D3
D2
10s years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four
bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
0x0E
D7
D6
D5
D4
0
0
0
10s month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
Time Keeping - Date
0x0D
D7
D6
0
0
D5
D4
D3
10s day of month
D2
D1
D0
Day of month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0
to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap
years are automatically adjusted for.
Time Keeping - Day
0x0C
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated
with the date.
Time Keeping - Hours
0x0B
D7
D6
0
0
D5
D4
D3
D2
10s hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from
0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
0x0A
D6
0
D5
D4
D3
D2
10s minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
Time Keeping - Seconds
D7
0x09
D6
0
D5
D4
D3
D2
10s seconds
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper
nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Calibration/Control
0X08
OSCEN
D7
D6
D5
OSCEN
0
Calibration
sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage.
Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
Sign
Calibration These five bits control the calibration of the clock.
Document #: 001-54392 Rev. *C
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CY14B101PA
CY14E101PA
PRELIMINARY
Table 13. Register Map Detail (continued)
Watchdog Timer
0x07
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The
bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a ‘0’.
WDW
Watchdog Write Enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This enables
the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows bits D5–D0 to
be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in
Watchdog Timer on page 23.
WDT
Watchdog Timeout Selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting
of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was
set to ‘0’ on a previous cycle.
Interrupt Status/Control
0x06
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
SQWE
H/L
P/L
SQ1
SQ0
WIE
Watchdog Interrupt Enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.
AIE
Alarm Interrupt Enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm
match only affects the AF flag.
PFE
Power Fail Enable. When set to ‘1’, the alarm match drives the INT pin and the PF flag. When set to ‘0’, the power fail
monitor affects only the PF flag.
SQWE
Square Wave Enable. When set to ‘1’, a square wave is driven on the INT pin with frequency programmed using SQ1
and SQ0 bits. The square wave output takes precedence over interrupt logic. If the SQWE bit is set to ‘1’. when an
enabled interrupt source becomes active, only the corresponding flag is raised and the INT pin continues to drive the
square wave.
H/L
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
SQ1, SQ0 SQ1, SQ0. These bits are used to decide the frequency of the Square wave on the INT pin output when SQWE bit is
set to ‘1’. The following is the frequency output for each combination of (SQ1, SQ0):
(0, 0) - 1 Hz
(0, 1) - 512 Hz
(1, 0) - 4096 Hz
(1, 1) - 32768 Hz
Alarm - Day
0x05
D7
D6
M
0
D5
D4
D3
D2
10s alarm date
D1
D0
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit
to ignore the date value.
Alarm - Hours
0x04
D7
D6
M
0
D5
D4
10s alarm hours
D3
D2
D1
D0
Alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the hours value.
Document #: 001-54392 Rev. *C
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CY14E101PA
PRELIMINARY
Table 13. Register Map Detail (continued)
Alarm - Minutes
0x03
D7
D6
M
D5
D4
D3
10s alarm minutes
D2
D1
D0
Alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the minutes value.
Alarm - Seconds
0x02
D7
D6
M
D5
D4
D3
10s alarm seconds
D2
D1
D0
Alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the seconds value.
Time Keeping - Centuries
0x01
D7
D6
D5
D4
D3
D2
10s centuries
D1
D0
Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
Flags
0x00
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
BPF
CAL
W
R
WDF
Watchdog Timer Flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being reset
by the user. It is cleared to ‘0’ when the flags register is read or on power-up
AF
Alarm Flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with
the match bits = ‘0’. It is cleared when the flags register is read or on power-up.
PF
Power Fail Flag. This read only bit is set to ‘1’ when power falls below the power fail threshold VSWITCH. It is cleared
when the flags register is read.
OSCF
Oscillator Fail Flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This
indicates that RTC backup power failed and clock value is no longer valid. This bit survives power cycle and is never
cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets
OSCF flag bit, the bit will be updated after tRTCp time.
BPF
Backup Power Fail Flag. Set to ‘1’ on power-up if the backup power (battery or capacitor) failed. The backup power fail
condition is determined by the voltage falling below their respective minimum specified voltage. BPF can hold the data
only until a defined low level of the back-up voltage (VDR). User must reset this bit to clear this flag. When user resets
BPF flag bit, the bit will be updated after tRTCp time.
CAL
Calibration Mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes
normal operation. This bit takes priority than SQ0/SQ1 and other functions. This bit defaults to ‘0’ (disabled) on power-up.
W
Write Enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers,
alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of
the RTC registers to be transferred to the time keeping counters if the time has changed. This transfer process takes
tRTCp time to complete. This bit defaults to 0 on power-up.
R
Read Enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen during
the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require
‘W’ bit to be set to ‘1’. This bit defaults to ‘0’ on power-up.
Document #: 001-54392 Rev. *C
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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Best Practices
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in these suggestions as best practices:
■
■
The nonvolatile cells in this nvSRAM product are delivered by
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■
The VCAP value specified in this datasheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection
with Cypress to understand any impact on the VCAP voltage level
at the end of a tRECALL period.
■
When base time is updated, these updates are transferred to
the time keeping registers when ‘W’ bit is set to ‘0’. This transfer
takes tRTCp time to complete. It is recommended to initiate
software STORE or Hardware STORE after tRTCp time to save
the base time into nonvolatile memory.
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
Document #: 001-54392 Rev. *C
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Maximum Ratings
Transient voltage (<20 ns) on
Any pin to ground potential.................. –2.0 V to VCC + 2.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
Capability (TA = 25°C) .................................................. 1.0 W
Storage temperature ................................ –65 °C to +150 °C
Maximum accumulated storage time
Surface mount lead soldering
Temperature (3 Seconds) ......................................... +260 °C
At 150 °C ambient temperature........ ............... 1000 h
DC output current (1 output at a time, 1s duration). .... 15 mA
At 85 °C ambient temperature..................... 20 Years
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Ambient temperature with
power applied ........................................... –55 °C to +150 °C
Latch up current..................................................... > 140 mA
Supply voltage on VCC relative to VSS
CY14C101PA: VCC = 2.4 V to 2.6 V ..–0.5 V to +3.1 V
CY14B101PA: VCC = 2.7 V to 3.6 V ..–0.5 V to +4.1 V
CY14E101PA: VCC = 4.5 V to 5.5 V ..–0.5 V to +7.0 V
DC voltage applied to outputs
in High-Z State..................................... –0.5 V to VCC + 0.5 V
Table 14. Operating Range
CY14B101PA
2.7 V to 3.6 V
Input voltage ........................................ –0.5 V to VCC + 0.5 V
CY14E101PA
4.5 V to 5.5 V
Device
Range
CY14C101PA
Industrial
Ambient
Temperature
VCC
–40 °C to +85 °C 2.4 V to 2.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VCC
ICC1
Power supply
Average VCC current
Min
Typ[6]
Max
Unit
CY14C101PA
2.4
2.5
2.6
V
CY14B101PA
2.7
3.0
3.6
V
CY14E101PA
4.5
5.0
5.5
V
CY14C101PA
–
–
3
mA
–
–
4
mA
–
–
2
mA
Test Conditions
fSCK = 40 MHz;
Values obtained without output loads
(IOUT = 0 mA)
CY14B101PA
CY14E101PA
ICC2
Average VCC current
during STORE
ICC3
All inputs cycling at CMOS levels.
Average VCC current
Values obtained without output loads (IOUT = 0 mA)
fSCK = 1 MHz;
VCC = VCC (Typ), 25 °C
–
–
1
mA
ICC4
Average VCAP current All inputs don't care. Average current for duration tSTORE
during AutoStore cycle
–
–
3
mA
ISB
VCC standby current
CS > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). ‘W’
bit set to ‘0’. Standby current level after nonvolatile cycle
is complete. Inputs are static. fSCK = 0 MHz.
–
–
250
μA
IZZ
Sleep mode current
tSLEEP time after SLEEP instruction is registered. All
Inputs are static and configured at CMOS logic level.
–
–
8
μA
IIX[7]
Input leakage current
(except HSB)
–1
–
+1
μA
Input leakage current
(for HSB)
–100
–
+1
μA
All inputs don’t care, VCC = max
Average current for duration tSTORE
Notes
6. Typical values are at 25 °C, VCC = VCC (Typ). Not 100% tested.
7. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-54392 Rev. *C
Page 32 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Min
Typ[6]
Max
Unit
–1
–
+1
μA
CY14C101PA
1.7
–
VCC + 0.5
V
CY14B101PA
2.0
–
VCC + 0.5
V
–
0.7
V
–
0.8
V
Test Conditions
IOZ
Off state output
Leakage Current
VIH
Input HIGH voltage
CY14E101PA
VIL
Input LOW voltage
CY14C101PA Vss – 0.5
CY14B101PA Vss – 0.5
CY14E101PA
VOH
Output HIGH voltage
IOUT = –1 mA
CY14C101PA
2.0
–
–
V
IOUT = –2 mA
CY14B101PA
2.4
–
–
V
CY14C101PA
–
–
0.4
V
CY14B101PA
–
–
0.4
V
CY14C101PA
170
220
270
μF
CY14B101PA
42
47
180
μF
CY14E101PA
VOL
Output LOW voltage
IOUT = 2 mA
IOUT = 4 mA
CY14E101PA
VCAP
Storage capacitor
Between VCAP pin and VSS
CY14E101PA
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
7
pF
16-SOIC
Unit
56.68
°C/W
32.11
°C/W
Capacitance
Parameter[8]
Description
CIN
Input capacitance
COUT
Output pin capacitance
Test Conditions
TA = 25 °C, f = 1MHz,
VCC = VCC (Typ)
Thermal Resistance
Parameter[8]
ΘJA
ΘJC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
Note
8. These parameters are guaranteed by design and are not tested.
Document #: 001-54392 Rev. *C
Page 33 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 33. AC Test Loads and Waveforms
For 2.5 V (CY14C101PA):
909Ω
909Ω
2.5 V
2.5 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
R2
1290Ω
30 pF
R2
1290Ω
5 pF
For 3 V (CY14B101PA):
577Ω
577Ω
3.0 V
3.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
R2
789Ω
30 pF
R2
789Ω
5 pF
For 5 V (CY14E101PA):
963Ω
963Ω
5.0 V
5.0 V
R1
For Tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
512Ω
R2
512Ω
5 pF
AC Test Conditions
Description
CY14C101PA
CY14B101PA
CY14E101PA
0 V to 2.5 V
0 V to 3 V
0 V to 3 V
Input rise and fall times (10% - 90%)
<3 ns
<3 ns
<3 ns
Input and output timing reference levels
1.25 V
1.5 V
1.5 V
Input pulse levels
Document #: 001-54392 Rev. *C
Page 34 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
RTC Characteristics
Parameters
Description
Min
Typ[9]
Max
Units
VRTCbat
RTC battery pin voltage
IBAK[10]
RTC backup current
1.8
3.0
3.6
V
–
0.45
0.6
µA
VRTCcap[11]
RTC capacitor pin voltage
tOCS
RTC oscillator time to start
1.6
–
3.6
V
–
1
2
sec
VBAKFAIL
Backup failure threshold
1.8
–
2
V
VDR
BPF flag retention voltage
1.6
–
–
V
tRTCp
RTC processing time from end of ‘W’ bit set to ‘0’
RBKCHG
RTC backup capacitor charge current limiting resistor
–
–
1
ms
350
–
850
Ω
AC Switching Characteristics
Cypress
Alt.
Parameter Parameter
Description
25 MHz
(RDRTC Instruction)[12]
40 MHz
104 MHz
Unit
Min
Max
Min
Max
Min
Max
fSCK
fSCK
Clock frequency, SCK
–
25
–
40
––
104
MHz
tCL[13]
tCH[13]
tWL
Clock pulse width LOW
18
–
11
–
4.5
–
ns
tWH
Clock pulse width HIGH
18
–
11
–
4.5
–
ns
tCS
tCE
CS HIGH time
20
–
20
–
20
–
ns
tCSS
tCES
CS setup time
10
–
10
–
5
–
ns
tCSH
tCEH
CS hold time
10
–
10
–
5
–
ns
tSD
tSU
Data in setup time
5
–
5
–
4
–
ns
tHD
tH
Data in hold time
5
–
5
–
3
–
ns
tHH
tHD
HOLD hold time
5
–
5
–
3
–
ns
tSH
tCD
HOLD setup time
5
–
5
–
3
–
ns
tCO
tV
Output valid
–
15
–
9
–
8
ns
tHHZ[13]
tHZ
HOLD to output high-Z
–
15
–
15
–
8
ns
tHLZ[13]
tLZ
HOLD to output low-Z
–
15
–
15
–
8
ns
tOH
tHO
Output hold time
0
–
0
–
0
–
ns
tHZCS[13]
tDIS
Output disable time
–
25
–
20
–
8
ns
Notes
9. Typical values are at 25 °C, VCC= VCC (Typ). Not 100% tested.
10. Current drawn from either VRTCcap or VRTCbat when VCC < VSWITCH.
11. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator will start in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the
capacitor must be allowed to charge to 0.5 V for oscillator to start.
12. Applicable for RTC opcode cycles, address cycles and data out cycles.
13. These parameters are guaranteed by design and are not tested.
Document #: 001-54392 Rev. *C
Page 35 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Figure 34. Synchronous Data Timing (Mode 0)
tCS
CS
tCH
tCL
tCSH
~
~
tCSS
SCK
tSD
tHD
VALID IN
SI
tCO
SO
tOH
HI-Z
tHZCS
HI-Z
~
~
~ ~
Figure 35. HOLD Timing
CS
SCK
tHH
tHH
tSH
tSH
HOLD
tHHZ
tHLZ
SO
Document #: 001-54392 Rev. *C
Page 36 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
AutoStore or Power Up RECALL
Parameters
tFA
[14]
Power up RECALL duration
CY14C101PA
CY14B101PA
CY14E101PA
tSTORE [15]
tDELAY [16]
VSWITCH
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level
tVCCRISE[17]
VHDIS[17]
tLZHSB[17]
tHHHD[17]
tWAKE
VCC rise time
HSB output disable voltage
HSB high to nvSRAM active time
HSB HIGH active time
Time for nvSRAM to wake up from SLEEP mode
tSLEEP
tSB
CY14X101PA
Min
Max
–
40
–
20
–
20
–
8
–
25
–
2.35
–
2.65
–
4.40
150
–
–
1.9
–
5
–
500
–
40
–
20
–
20
–
8
–
100
Description
CY14C101PA
CY14B101PA
CY14E101PA
CY14C101PA
CY14B101PA
CY14E101PA
Time to enter into SLEEP mode after Issuing SLEEP instruction
Time to enter into standby mode after CS going HIGH
Unit
ms
ms
ms
ms
ns
V
V
V
µs
V
µs
ns
ms
ms
ms
ms
µs
Switching Waveforms
Figure 36. AutoStore or Power Up RECALL[18]
VCC
VSWITCH
VHDIS
t VCCRISE
15
tHHHD
Note
tSTORE
Note
tHHHD
19
Note
15
tSTORE
19
Note
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
14. tFA starts from the time VCC rises above VSWITCH.
15. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
16. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
17. These parameters are guaranteed by design and are not tested.
18. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
19. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-54392 Rev. *C
Page 37 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Software Controlled STORE/RECALL Cycles
CY14X101PA
Parameter
Description
tRECALL
tSS
[20, 21]
Max
RECALL duration
–
600
µs
Soft sequence processing time
–
500
µs
Figure 37. Software STORE Cycle[21]
Figure 38. Software RECALL Cycle[21]
CS
CS
0
1
2
3
4
5
6
7
0
SCK
SI
Unit
Min
1
2
3
4
5
6
7
SCK
0
0
1
1
1
1
0
0
SI
0
1
1
0
0
0
0
0
tRECALL
tSTORE
HI-Z
RWI
RDY
RDY
Figure 39. AutoStore Enable Cycle
Figure 40. AutoStore Disable Cycle
CS
CS
0
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
SCK
SCK
SI
HI-Z
RWI
0
1
0
1
1
0
0
SI
1
0
0
0
1
1
0
0
1
tSS
tSS
RWI
HI-Z
RDY
RWI
HI-Z
RDY
Notes
20. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
21. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-54392 Rev. *C
Page 38 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Hardware STORE Cycle
CY14X101PA
Parameter
tPHSB
Description
Unit
Min
Max
15
–
Hardware STORE pulse width
ns
Figure 41. Hardware STORE Cycle[15]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
tDELAY
HSB (OUT)
tLZHSB
RWI
tPHSB
HSB (IN)
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDELAY
RWI
~
~
HSB (OUT)
~
~
Write Latch not set
Note
22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document #: 001-54392 Rev. *C
Page 39 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Ordering Information
Ordering Code
Package Diagram
CY14C101PA-SFXIT
51-85022
Package Type
Operating Range
16-pin SOIC, 40 MHz
CY14C101PA-SFXI
16-pin SOIC, 40 MHz
CY14C101PA-SF104XIT
16-pin SOIC, 104 MHz
CY14C101PA-SF104XI
16-pin SOIC, 104 MHz
CY14B101PA-SFXIT
16-pin SOIC, 40 MHz
CY14B101PA-SFXI
16-pin SOIC, 40 MHz
CY14B101PA-SF104XIT
16-pin SOIC, 104 MHz
CY14B101PA-SF104XI
16-pin SOIC, 104 MHz
CY14E101PA-SFXIT
16-pin SOIC, 40 MHz
CY14E101PA-SFXI
16-pin SOIC, 40 MHz
CY14E101PA-SF104XIT
16-pin SOIC, 104 MHz
CY14E101PA-SF104XI
16-pin SOIC, 104 MHz
Industrial
All the above parts are Pb-free.
Ordering Code Definition
CY 14 C 101 P A - 104 SF X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (-40 to 85 °C)
Pb-free
Frequency:
Blank - 40 MHz
104 - 104 MHz
Package:
SF - 16 SOIC
Die revision:
Blank - No Rev
A - 1st Rev
P - Serial (SPI) nvSRAM with RTC
Density:
Voltage:
C - 2.5 V
B - 3.0 V
E - 5.0 V
101 - 1 Mb
14 - nvSRAM
Cypress
Document #: 001-54392 Rev. *C
Page 40 of 44
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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Package Diagram
Figure 42. 16-Pin (300 mil) SOIC (51-85022)
51-85022 *C
Document #: 001-54392 Rev. *C
Page 41 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Acronyms
Document Conventions
Table 15. Acronyms Used in this Document
Acronym
Description
Units of Measure
Symbol
Unit of Measure
BCD
Binary coded decimal
°C
degree Celsius
CMOS
Complementary metal oxide semiconductor
Hz
Hertz
CRC
Cyclic redundancy check
kbit
1024 bits
CPHA
Clock phase
kHz
kilo Hertz
CPOL
Clock polarity
KΩ
kilo ohms
EEPROM
Electrically erasable programmable
read-only memory
μA
micro Amperes
EIA
Electronic Industries Alliance
mA
milli Ampere
I/O
Input/output
μf
micro Farad
JEDEC
Joint Electron Devices Engineering Council
MHz
mega Hertz
nvSRAM
nonvolatile static random access memory
RoHS
Restriction of hazardous substances
RWI
Read and write inhibited
SOIC
Small outline integrated circuit
SONOS
Silicon-oxide-nitride-oxide semiconductor
SPI
Serial peripheral interface
Document #: 001-54392 Rev. *C
μs
micro seconds
ms
milli second
ns
nano seconds
pF
pico Farad
ps
pico seconds
V
Volts
Ω
ohms
W
Watts
Page 42 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Document History Page
Document Title: CY14C101PA, CY14B101PA, CY14E101PA 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock
Document Number: 001-54392
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
2754627
08/21/09
GVCH
New Data Sheet
*A
2860397
01/20/2010
GVCH
Changed Vcc range for CY14C101PA from 2.3 - 2.7 V to 2.4-2.6 V
Removed 16-SOIC 150 mil package
Added VOH, VOL, VIH, VIL and VCAP specs for Vcc (Typ) = 2.5 V
Updated VIH min value from 1.4 V to 2.0 V for Vcc (Typ) = 3 V & 5 V
*B
2902491
03/31/2010
GVCH
Changes datasheet status from “Advance” to “Preliminary”
Updated Logic Block Diagram, Pinouts, and Pin Definitions
Complete content write
Changed ICC4 value from 2 mA to 3 mA
Added FAST_RDSN, FAST_RDSR, and FAST_RDID opcodes in Table 2
Added Ci parameter in DC Electrical Characteristics
Changed VCAP value from for VCC=2.4 V-2.6 V in DC Electrical Characteristics
Changed min value from 100 uF to 170 uF
Changed typ value from 150 uF to 220 uF
Changed max value from 330 uF to 270 uF
Changed VCAP value from for VCC=2.7 V-3.6 V and VCC=4.5-5.5 V in DC
Electrical Characteristics
Changed min value from 40 uF to 42 uF
Added Data Retention and Endurance Table
Added Capacitance Table
Added Thermal Resistance Table
Added AC Test Conditions Table
Added VDR and RBKCHG in RTC Characteristics Table
Changed tCSS parameter min value from 3 ns to 5 ns for 104 MHz
Changed tCSH parameter min value from 3 ns to 5 ns for 104 MHz
Changed tSD parameter min value from 3 ns to 4 ns for 104 MHz
Changed tHD parameter min value from 2 ns to 3 ns for 104 MHz
Added Figures
Added tFA for VCC=2.4 V-2.6 V
Added tWAKE for VCC=2.4 V-2.6 V
Added tSB parameter
Changed VSWITCH from 4.45 V to 4.40 V for VCC = 4.5 V to 5.5 V
Added Software Controlled STORE/RECALL Cycles Table
Updated tRECALL value from 200 us to 300 us
Changed tSS value from 100 to 200 µs
Added Hardware STORE Cycle Table
Updated Ordering Information
Updated package diagram
*C
3150044
01/21/2011
GVCH
Hardware STORE and HSB pin Operation: Added more clarity on HSB pin
operation
Updated Setting the Clock description
Updated ‘W’ bit desription in Register Map Detail table
Updated best practices
Added tRTCp parameter to RTC Characteristics table
Updated tLZHSB parameter description
Fixed typo in Figure 36
Updated tSS value from 200 us to 500 us
Updated tRECALL value from 300 us to 600 us
Added Acronyms and Document Conventions table
Document #: 001-54392 Rev. *C
Page 43 of 44
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CY14C101PA
CY14B101PA
CY14E101PA
PRELIMINARY
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-54392 Rev. *C
Revised January 21, 2011
Page 44 of 44
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