LINER LTM4650-1 25a dc/dc step-down î¼module regulator Datasheet

LTM4645
25A DC/DC Step-Down
µModule Regulator
Description
Features
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4.7V to 15V Input Voltage Range
0.6V to 1.8V Output Voltage Range
25A DC Output Current
±1.2% Total DC Output Voltage Error (–40°C to 125°C)
High Reliability N + 1 Phase Redundancy Supported
Internal or External Control Loop Compensation
Differential Remote Sense Amplifier for Precision
Regulation
Current Mode Control/Fast Transient Response
Multiphase Current Sharing Up to 150A
Built-In Temperature Monitoring
Selectable Pulse-Skipping, Burst Mode® Operation
Soft-Start/Voltage Tracking
Frequency Synchronization
Output Overvoltage Protection
Output Overcurrent Foldback Protection
9mm × 15mm × 3.51mm BGA Package
The LTM®4645 is a 25A output switching mode step-down
DC/DC µModule® (power module) regulator. Included in
the package are the switching controller, power FETs, inductor and all supporting components. Operating over an
input voltage range of 4.7V to 15V, the LTM4645 supports
an output voltage range of 0.6V to 1.8V, set by a single
external resistor. Only a few input and output capacitors
are needed.
Its high efficiency design delivers about 86% efficiency
from 12V input to 1.0V output with 25A continuous load
current. High switching frequency and a current-mode
architecture enable a very fast transient response to line
and load changes without sacrificing stability. The device
supports frequency synchronization, programmable
multiphase operation, N+1 phase redundancy, and output
voltage tracking for supply rail sequencing.
Fault protection features include overvoltage and overcurrent protection. The power module is offered in a space
saving 9mm × 15mm × 3.51mm BGA package. The
LTM4645 is available with SnPb (BGA) or RoHS compliant terminal finish.
Applications
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Telecom, Networking and Industrial Equipment
Point of Load Regulation
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule, LTpowerCAD
and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners.
Typical Application
Efficiency vs Output Current
at 1V Output
12VIN, 1VOUT, 25A DC/DC µModule Regulator
2.2Ω
VIN
22µF
25V
×2
SVIN
95
DRVCC INTVCC
90
HIZB
FREQ
43.2k
LTM4645
VOUT
COMPa
VOSNS+
COMPb
VFB
TRACK/SS
0.1µF
VOSNS–
SGND GND
47pF
90.9k
VOUT
1V
25A
100µF
6.3V
×4
4645 TA01a
PINS NOT USED IN THIS CIRCUIT:
CLKOUT, MODE/PLLIN, PGOOD,
PHASMD, PWM, RUN, SW, TEMP+, TEMP–
EFFICIENCY (%)
VIN
6V TO 15V
100
4.7µF
6.3V
1µF
85
80
75
70
5V INPUT
12V INPUT
65
60
0
5
10
15
20
25
LOAD CURRENT (A)
4645 TA01b
4645f
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1
LTM4645
Absolute Maximum Ratings
Pin Configuration
(Note 1)
VIN, SVIN, HIZB........................................... –0.3V to 16V
VOUT,.......................................................... –0.3V to 3.5V
INTVCC, DRVCC, PGOOD, RUN...................... –0.3V to 6V
MODE/PLLIN, TRACK/SS, VOSNS+, VOSNS –,
CLKOUT, COMPa, COMPb, VFB, PHASMD,
FREQ ..................................................... –0.3V to INTVCC
Operating Junction Temperature (Note 2)... –40 to 125°C
Storage Temperature Range....................... –55 to 125°C
Peak Solder Reflow Body Temperature.................. 250°C
TEMP+, TEMP–........................................... –0.3V to 0.8V
A
DRVCC
TEST2
B
TOP VIEW
3
4
5
6
7
GND GND RUN GND
2
1
VIN
PWM
C
D
TEMP–
E
TRACK/SS
SW
TEMP+ F
VOSNS–
G
H
J
K
GND
HIZB
GND
GND
VOUT
CLKOUT
TEST1
MODE/PLLIN
INTVCC
PHASMD
SVIN
FREQ
VFB
SGND
TEST3
VOSNS+
PGOOD
COMPa
COMPb
GND
L
BGA PACKAGE
77-LEAD (9mm × 15mm × 3.51mm)
TJ(MAX) = 125°C, θJA = 9.5°C/W, θJCbottom = 4°C/W, θJCtop = 6.7°C/W, θJB = 4.5°C/W
θJA DERIVED FROM 95mm × 76mm PCB WITH SIX LAYERS; WEIGHT = 1.3g
θ VALUES DETERMINED PER JESD51-12
Order Information
http://www.linear.com/product/LTM4645#orderinfo
PART MARKING*
PART NUMBER
PAD OR BALL FINISH
LTM4645EY#PBF
SAC305 (RoHS)
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
LTM4645Y
e1
BGA
3
TEMPERATURE RANGE
(Note 2)
–40°C to 125°C
LTM4645IY#PBF
SAC305 (RoHS)
LTM4645Y
e1
BGA
3
–40°C to 125°C
LTM4645IY
SnPb (63/37)
LTM4645Y
e0
BGA
3
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
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LTM4645
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
VIN
Input DC Voltage
VOUT(RANGE)
Output Voltage Range
VIN = 4.7V to 15V
VOUT(DC)
Output Voltage, Total Variation
with Line and Load
CIN = 22µF × 4, COUT = 100µF Ceramic, 470µF POSCAP,
RFB = 60.4k, MODE = GND,VIN = 4.7V to 15V, IOUT = 0A to 25A
MIN
TYP
MAX
UNITS
l
4.7
15
V
l
0.6
1.8
V
l
1.186
1.214
V
1.200
Input Specifications
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.2V, Burst Mode Operation, IOUT = 0A
VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode, IOUT = 0A
VIN = 12V, VOUT = 1.2V, Switching Continuous, IOUT = 0A
Shutdown, RUN = 0, VIN = 12V
11
25
170
90
mA
mA
mA
µA
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 1.2V, IOUT = 25A
3.0
A
Output Specifications
IOUT(DC)
Output Continuous Current
Range
VIN = 12V, VOUT = 1.2V (Note 4)
∆VOUT(LINE)/VOUT
Line Regulation Accuracy
VOUT = 1.2V, VIN from 4.7V to 15V, IOUT = 0A
l
0.005
0.05
VOUT = 1.2V, IOUT = 0A to 25A, VIN = 12V (Note 4)
l
0.1
0.3
∆VOUT(LOAD)/ VOUT Load Regulation Accuracy
VOUT(AC)
Output Ripple Voltage
∆VOUT(START)
0
25
A
%/V
%
COUT = 100µF Ceramic × 6,
VIN = 12V, VOUT = 1.2V, IOUT = 0A
15
mV
Turn-On Overshoot
COUT = 100µF Ceramic × 6,
VIN = 12V, VOUT = 1.2V, IOUT = 0A
20
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic × 6
VIN = 12V, VOUT = 1.2V, No Load, TRACK/SS = 0.01µF
5
ms
∆VOUTLS
Peak Deviation for Dynamic
Load
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V
36
mV
tSETTLE
Settling Time for Dynamic
Load Step
Load: 0% to 50% to 0% of Full Load,
COUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V
15
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 1.2V
35
A
Control Specifications
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.2V
600
606
IFB
Current at VFB Pin
(Note 7)
–30
–100
ITRACK/SS
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
1.25
(Note 3)
tON(MIN)
Minimum On-Time
RFBHI
Resistor Between VOUT_LCL
and VFB Pins
VRUN
RUN Pin On Threshold
VRUNHYS
RUN Pin On Hysteresis
UVLO
Undervoltage Lockout
UVLOHYS
UVLO Hysteresis
VHIZB
HIZB Pin On Threshold
VHIZBHYS
HIZB Pin On Hysteresis
VRUN Rising
l
594
VINTVCC Falling
VHIZB Rising
µA
90
ns
60.05
60.40
60.75
1.2
1.35
1.45
180
4
nA
kΩ
V
mV
V
400
mV
2.3
V
800
mV
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LTM4645
Electrical Characteristics
The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
90
200
Ω
PGOOD
RPGOOD
PGOOD Pull-Down Resistance
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–7.5
7.5
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
5.5
5.7
%
%
V
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
VIN ≥ 12V
VINTVCC Load Reg
INTVCC Load Regulation
ICC = 0mA to 10mA
5.3
0.5
V
%
Oscillator and Phase-Locked Loop
fSYNC
SYNC Capture Range
fSW
Switching Frequency
RFREQ = 47.5kΩ
300
IFREQ
FREQ Pin Current
VFREQ = 0.8V
RMODE_PLLIN
Mode_PLLIN Input Resistance
VIH_MODE_PLLIN
Clock Input Level High
VIL_MODE_PLLIN
Clock Input Level Low
θCLKOUT
CLKOUT to SW Phase Delay
540
600
1000
kHz
660
kHz
20
µA
250
kΩ
2.0
V
1.2
VPHSMD = 0V
VPHSMD = 1/4 INTVCC
VPHSMD = Float
VPHSMD = 3/4 INTVCC
VPHSMD = INTVCC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4645 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4645E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4645I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
90
90
120
60
180
V
Deg
Deg
Deg
Deg
Deg
Note 3: The minimum on-time condition is specified for a peak-to-peak
inductor ripple current of ~40% of IMAX Load. (See the Applications
Information section)
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Limit current into the RUN pin to less than 2mA.
Note 6: Guaranteed by design.
Note 7: 100% tested at wafer level.
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LTM4645
Typical Performance Characteristics
Efficiency vs Output Current,
VIN = 12V
100
95
95
90
90
85
80
0.9VOUT 500kHz
1VOUT 600kHz
1.2VOUT 700kHz
1.5VOUT 800kHz
1.8VOUT 900kHz
75
70
65
0
10
5
15
20
80
85
80
0.9VOUT 500kHz
1VOUT 600kHz
1.2VOUT 700kHz
1.5VOUT 800kHz
1.8VOUT 900kHz
70
65
0
5
10
15
20
70
60
50
40
30
20
CCM
Burst Mode OPERATION
PULSE-SKIPPING MODE
10
25
0
0.01
0.1
LOAD CURRENT (A)
LOAD CURRENT (A)
1
10
LOAD CURRENT (A)
100
4645 G03
4645 G02
4645 G01
0.9V Output Load Step Transient
Response
1.2V Output Load Step Transient
Response
1V Output Load Step Transient
Response
VOUT
50mV/DIV
ACCOUPLED
VOUT
50mV/DIV
ACCOUPLED
VOUT
50mV/DIV
ACCOUPLED
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
50µs/DIV
CCM, Burst Mode and PulseSkipping Mode Efficiency
VIN = 12V, VOUT = 1.2V, 750kHz
90
75
25
100
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current,
VIN = 5V
50µs/DIV
4645 G04
VIN = 12V, VOUT = 0.9V, FS = 500kHz
COUT = 6 × 100µF CERAMIC
CFF = 33pF
0A TO 6.25A LOAD STEP, 10A/µs
VOUT
50mV/DIV
ACCOUPLED
VOUT
50mV/DIV
ACCOUPLED
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
50µs/DIV
4645 G06
VIN = 12V, VOUT = 1.2V, FS = 700kHz
COUT = 6 × 100µF CERAMIC
CFF = 33pF
0A TO 6.25A LOAD STEP, 10A/µs
1.8V Output Load Step Transient
Response
1.5V Output Load Step Transient
Response
VIN = 12V, VOUT = 1.5V, FS = 800kHz
COUT = 6 × 100µF CERAMIC
CFF = 33pF
0A TO 6.25A LOAD STEP, 10A/µs
50µs/DIV
4645 G05
VIN = 12V, VOUT = 1V, FS = 600kHz
COUT = 6 × 100µF CERAMIC
CFF = 33pF
0A TO 6.25A LOAD STEP, 10A/µs
50µs/DIV
4645 G07
4645 G08
VIN = 12V, VOUT = 1.8V, FS = 900kHz
COUT = 6 × 100µF CERAMIC
CFF = 33pF
0A TO 6.25A LOAD STEP, 10A/µs
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LTM4645
Typical Performance Characteristics
Start-Up with No Load Applied
Start-Up with 25A Load Applied
SW
10V/DIV
SW
10V/DIV
VOUT
500m/DIV
IIN
200mA/DIV
VOUT
500m/DIV
IIN
200mA/DIV
20ms/DIV
4645 G09
VIN = 12V, VOUT = 1.2V, FS = 700kHz, NO LOAD
COUT = 1 × 47µF CERAMIC + 1 × 470µF SPCAP
CSS = 0.1µF
20ms/DIV
4645 G10
VIN = 12V, VOUT = 1.2V, FS = 700kHz, NO LOAD
COUT = 1 × 47µF CERAMIC + 1 × 470µF SPCAP
CSS = 0.1µF
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LTM4645
Pin Functions
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VIN (A1-A3, B1-B2, C1-C2): Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between VIN
pins and GND pins.
GND (A4, A7, B3, C3, C4, D1-D4, E2-E4, F2, F4, F6, G1G4, H1-H5, J5-J7, K5-K7): Ground Pins for Both Input
and Output Returns. All ground pins need to connect with
large copper areas underneath the unit.
RUN (A6): Run Control Pin. A voltage above 1.35V will
turn on the module. This is a 1µA pull-up current on this
pin. Once the RUN pin rises above the 1.35V threshold
the pull-up current increases to 5µA.
PWM (B4): Control PWM Three-State Output Signal. For
monitor and test purpose only. Do not drive this pin.
CLKOUT (B5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
TEST1, TEST2, TEST3 (B6, D5, F7): These pins are for
µModule initial test purposes. Please connect these pins
to GND with a large GND copper area.
MODE/PLLIN (B7): Mode Selection Pin and External
Synchronization Pin. Connect this pin to SGND to force
the module into force continuous current mode (CCM) of
operation. Connect to INTVCC to enable pulse-skipping
mode of operation. Leaving the pin floating will enable
Burst Mode operation. A clock on the pin will force the
module into continuous current mode of operation and
synchronized to the external clock applied to this pin. See
the Applications Information section.
SVIN (D6): Signal VIN. Input voltage to the internal 5.5V
regulator for the control circuitry of the regulator. Tie this
pin to VIN pin through a 2.2Ω plus 1µF R-C filter in most
application. See the Application Information section.
DRVCC (C5): Power Input Pin for the MOSFET driver circuitry. Connect to INTVCC output for the application with
the input voltage 6V and above or connect this pin to an
external supply 4.5V or above through a 2.2Ω plus 1µF
R-C filter. See the Application Information section.
INTVCC (C6): Internal 5.5V LDO for driving the control
circuitry decouple with pin to GND with a minimum of
2.2µF low ESR ceramic capacitor. The 5.5V LDO has a
50mA current limit.
PHASMD (C7): This pin determines the relative phases
between the internal controller and the CLKOUT signal.
See Table 2 in the Application Information section.
FREQ (D7): Frequency Set Pin. A 20µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
HIZB (E5): Phase Shedding Input Pin. When this pin is low,
TRACK/SS, COMP and PWM pin go to high impedance.
Tie to INTVCC or VIN to disable this function.
VFB (E6): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOSNS+ with a 60.4k 0.5%
precision resistor. Different output voltages can be programmed with an additional resistor between VFB and
VSNS– pins. In PolyPhase® operation, tying the VFB pins
together allows for parallel operation. See the Applications
Information section for details.
SGND (E7): Signal Ground Pin. Return ground path for all
analog and low power circuitry. Tie a single connection
to the output capacitor GND in the application. See layout
guidelines in Figure 22.
SW (F3): Switching node of the circuit is used for testing
purposes. Also an R-C snubber network can be applied
to reduce or eliminate switch node ringing, or otherwise
leave floating. See the Applications Information section.
TRACK/SS (F5): Output Voltage Tracking Pin and Soft-Start
Inputs. The pin has a 1.25µA pull-up current. A capacitor
from this pin to ground will set a soft-start ramp rate. In
tracking, the regulator output can be tracked to a different
voltage. The voltage ramp rate at his pin sets the voltage
ramp rate of the output. See the Applications Information
section.
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LTM4645
Pin Functions
VOSNS– (G5): Input to the Remote Sense Amplifier. This
pin connects to the ground remote sense point at the
output load.
connect an R-C compensation network from COMPa to
SGND. Tie COMPa pins together in parallel operation. See
the Applications Information section.
VOSNS+ (G6): Input to the Remote Sense Amplifier. Internally, this pin is connected to VFB with a 60.4k 0.5%
precision resistor.
COMPb (H7): Internal Loop Compensation Networks. Tie to
COMPa to provide internal loop compensation for majority
of applications. Float this pin if internal loop compensation
not used. See COMPa description.
PGOOD (G7): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±7.5% of the regulation point.
COMPa (H6): Current Control Threshold and Error Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. Small filter
capacitor (10pF) internal to LTM4645 on this pin provides
good noise rejection in the control loop. Tie to COMPb
pin to use internal compensation in the vast majority of
applications. Whereas, when more specialized applications require an optimization of control loop response,
VOUT (J1-J4, K1-K4, L1-L7): Power Output Pins. Apply
output load between these pins and GND pins. Recommend
placing output decoupling capacitance directly between
these pins and GND pins. See Table 1.
TEMP+ (F1): Temperature Monitor. An internal diode connected PNP transistor. See the Applications Information
section.
TEMP– (E1): Low Side of the Internal Temperature Monitor.
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LTM4645
Block Diagram
2.2Ω
1µF
RUN
CLKOUT
HIZB
INTVCC
COMPa
PGOOD
10pF
COMPb
3300pF
47pF
2k
VIN
2.2µF
SVIN
M1
PHASMD
FREQ
INTVCC
POWER
CONTROL
1µF
M2
GND
SGND
VOUT
1V
25A
COUT
+
INTVCC
INTVCC
4.7µF
0.1µF
DVRVCC
DIFF
AMP
+
TRACK/SS
0.1µF
CIN
VOUT
–
RFREQ
48.7k
90nH
VIN
6V TO 15V
+
VSNS–
VFB
90.9k
60.4k
VSNS+
MODE/PLLIN
4645 F01
Figure 1. Simplified LTM4645 Block Diagram
Decoupling Requirements
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CIN
External Input Capacitor Requirement
(VIN = 4.7V to 15V, VOUT = 1V)
IOUT = 25A
44
µF
COUT
External Output Capacitor Requirement
(VIN = 4.7V to 15V, VOUT = 1V)
IOUT = 25A
300
µF
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LTM4645
Operation
Power Module Description
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
The LTM4645 is a high performance single output standalone nonisolated switching mode DC/DC power supply.
It can provide a 25A output with few external input and
output capacitors. This module provides precisely regulated output voltages programmable via external resistors
from 0.6V DC to 1.8V DC over a 4.7V to 15V input range.
The typical application schematic is shown in Figure 23
and Figure 24.
Pulling the RUN pin below 1.35V forces the regulator into
a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking
during start-up. See the Application Information section.
The LTM4645 has an integrated constant-frequency current mode regulator, power MOSFETs, inductor, and other
supporting discrete components. The switching frequency
range is optimized from 400kHz to 900kHz, depending on
output voltage. For switching noise-sensitive applications,
it can externally program to or be synchronized to a clock
from 300kHz to 1MHz subject to minimum on-time and
inductor ripple current limitations. See the Applications
Information section.
For high reliability environment, N+1 phase redundancy
can be easily implemented in LTM4645 together with a hot
swap controller, such as the LTC®4226, for extra system
protection. By connecting the HIZB pin to the gate of the
hot swap switch, any fault channel can be disconnected
while the rest of the system is not affected. See Applications Information section and Figure 27 for example.
The LTM4645 is designed to use either external or internal
control loop compensation by shorting COMPb and COMPa
pins together. With current mode control, the internal
loop compensation has sufficient stability margins and
good transient performance with a wide range of output
capacitors, even with all ceramic output capacitors. Table
5 provides a guideline for input and output capacitances
for several different output conditions using the internal
loop compensation. The LTpowerCAD® design tool is
available to download for optimizing the loop stability and
transient response.
Multiphase operation can be easily employed by cascading the MODE/PLLIN input to the CLKOUT output. See the
Applications Information section and Figure 25 for example.
High efficiency at light loads can be accomplished with
phase shedding in multiphase operation or with selectable
pulse-skipping mode or Burst Mode operation in single
phase operation. Efficiency graphs are provided for light
load operation in the Typical Performance Characteristics
section.
A remote sense amplifier is provided for accurately sensing
output voltages at the load point.
A TEMP+ and TEMP– pins are provided to allow the internal
device temperature to be monitored using an onboard
diode connected PNP transistor.
Current mode control provides cycle-by-cycle fast current
limit in an overcurrent condition. An internal overvoltage
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LTM4645
Applications Information
The typical LTM4645 application circuit is shown in
Figure 23 and Figure 24. External component selection
is primarily determined by the maximum load current
and output voltage. Refer to Table 5 for specific external
capacitor requirements for particular applications.
In multiphase single output application. Only one set of
differential sensing amplifier and one set of feedback resistor are required while connecting VOUT, VFB and COMP of
different channels together. See Figure 25 for paralleling
application.
VIN to VOUT Step-Down Ratios and Minimum On-Time
Input Capacitors
There are restrictions in the VIN to VOUT step-down ratio
that can be achieved for a given input, output voltage
and frequency. The minimum on-time, tON(MIN), limits
the smallest time duration that the module is capable of
turning on the top MOSFET. It is determined by internal
timing delays, and the gate charge required turning on
the top MOSFET. At very low duty cycles, the minimum
90ns on-time must be maintained and satisfy the equation:
The LTM4645 module should be connected to a low
AC-impedance DC source. Additional input capacitors
are needed for the RMS input ripple current rating. The
ICIN(RMS) equation which follows can be used to calculate
the input capacitor requirement. Typically 22µF ceramics
are a good choice with RMS ripple current ratings of ~2A
each. A 47µF to 100µF surface mount aluminum electrolytic
bulk capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
tON =
VOUT
> 90ns
VIN •FREQ
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple voltage of inductor ripple and current
will increase. The minimum on-time can be increased by
lowering the switching frequency.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4k, 0.5% accuracy
internal feedback resistor connects from the VOSNS+ pin
to the VFB pin.
The output voltage will default to 0.6V with no feedback
resistor. Adding a resistor RFB from VFB to VOSNS– programs the output voltage:
VOUT = 0.6V •
60.4k +RFB
RFB
For a buck converter, the switching duty cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
IOUT(MAX)
η%
• D• (1–D)
In the previous equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor or a Polymer
capacitor.
Output Capacitors
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT (V)
0.6
0.9
1.0
1.2
1.5
1.8
RFB (kΩ)
OPEN
121
90.9
60.4
40.2
30.1
Frequency (kHz)
400
500
600
700
800
900
RFREQ (kΩ)
37.4
43.2
48.7
53.6
59
64.9
The LTM4645 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low ESR
Polymer capacitor or ceramic capacitors. Please note small
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LTM4645
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22pF to 47pF feedforward capacitor (CFF) is necessary for
all ceramic output application to achieve enough phase
margin. The typical output capacitance range is from 400µF
to 800µF. Additional output filtering may be required by
the system designer if further reduction of output ripple
or dynamic transient spikes is required. Table 5 shows a
matrix of different output voltages and output capacitors
to minimize the voltage droop and overshoot during a 6A/
µs transient (at 10A/µs slew rate). The table optimizes total
equivalent ESR and total output capacitance to optimize
the transient performance. Multiphase operation will reduce effective output ripple as a function of the number
of phases. Application Note 77 discusses this reduction
versus output ripple current cancellation. But the output
capacitance should be considered carefully as a function
of stability and transient response. The Linear Technology
LTpowerCAD Design Tool can calculate the output ripple
reduction as the number of implemented phase’s increases
by N times and provide stability analysis.
Burst Mode Operation
The LTM4645 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply float the MODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductor is set to approximately one-third of the maximum
peak current value in normal operation even though the
voltage at the COMPa pin indicates a lower value. The
voltage at the COMPa pin drops when the inductor’s average current is greater than the load requirement. As the
COMPa voltage drops below 0.5V, the burst comparator
trips, causing the internal sleep line to go high and turn
off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMPa to rise, the internal
sleep line goes low, and the LTM4645 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4645 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. With pulse-skipping mode at light load, the
internal current comparator may remain tripped for several
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMPa voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4645’s output
voltage is in regulation.
Frequency Selection
The LTM4645 device is operated over a range of frequencies
to improve power conversion efficiency. It is recommended
to operate the lower output voltages or lower duty cycle
conversions at lower frequencies to improve efficiency by
lowering power MOSFET switching losses. Higher output
voltages or higher duty cycle conversions can be operated
at higher frequencies to limit inductor ripple current. The
efficiency graphs will show an operating frequency chosen
for that condition. See Table 1 for optimized frequency for
various output voltages.
The LTM4645 switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
20µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 2 shows a graph of frequency setting verses
programming voltage.
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Applications Information
Multiphase Operation
1300
For outputs that demand more than 25A of load current,
multiple LTM4645 devices can be paralleled to provide
more output current without increasing input and output
voltage ripple.
FREQUENCY (kHz)
1100
900
700
500
The MODE_PLLIN pin allows the LTM4645 to synchronize
to an external clock (between 300kHz and 1MHz) and the
internal phase-locked loop allows the LTM4645 to lock
onto an incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
entire system. Tying the PHASMD pin to INTVCC, threefourths of INTVCC, floating or, SGND generates a phase
difference (between VOUT and CLKOUT) of 180 degrees,
60 degrees, 120 degrees, 90 degrees respectively. A total
of 12 phases can be cascaded to run simultaneously with
respect to each other by programming the PHASMD pin
of each LTM4645 channel to different levels. Figure 3
shows a 2-phase, 3-phase, 4-phase, and 6-phase design
example for clock phasing.
300
100
0.4
0.6
0.8
1.0 1.2
VFREQ (V)
1.4
1.6
1.8
4645 F02
Figure 2. Relationship Between Switching Frequency
and FREQ Pin Voltage
PLL and Frequency Synchronization
For some switching noise sensitive applications, LTM4645
can be synchronized from 300kHz to 1MHz subject to
minimum on-time and inductor current ripple limitation
with an input clock that has a high level above 2V and a
low level below 0.8V at the MODE_PLLIN pin. Once the
LTM4645 is synchronizing to an external clock frequency,
it will always be running in forced continuous current
operation. The 300kHz low end operation frequency limit
is suggested to limit inductor ripple current.
PHASE SELECTION
VOUT CLKOUT PHASMD
PHASE PHASE
(V)
0
90
0
0
90
1/4 INTVCC
FLOAT
0
120
0
60
3/4 INTVCC
0
180
INTVCC
TWO PHASE
0 PHASE
180 PHASE
MODE_PLLIN CLKOUT
INTVCC
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
LTM4645
PHASMD
VOUT
INTVCC
THREE PHASE
0 PHASE
120 PHASE
240 PHASE
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
FOUR PHASE
0 PHASE
90 PHASE
180 PHASE
270 PHASE
MODE_PLLIN CLKOUT
MODE_PLLIN CLKOUT
MODE_PLLIN CLKOUT
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
LTM4645
PHASMD
VOUT
LTM4645
PHASMD
VOUT
LTM4645
PHASMD
VOUT
INTVCC
R2
10k 3/4 INTV
CC
R1
30.1k
3/4 INTVCC
0 PHASE
SIX PHASE
60 PHASE
120 PHASE
MODE_PLLIN CLKOUT
MODE_PLLIN CLKOUT
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
3/4 INTVCC
LTM4645
PHASMD
VOUT
3/4 INTVCC
LTM4645
PHASMD
VOUT
180 PHASE
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
240 PHASE
300 PHASE
MODE_PLLIN CLKOUT
LTM4645
PHASMD
VOUT
3/4 INTVCC
MODE_PLLIN CLKOUT
LTM4645
VOUT
PHASMD
3/4 INTVCC
Figure 3. Phase Selection Examples
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4645 F03
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LTM4645
Applications Information
The LTM4645 device is an inherently current mode controlled device, so parallel modules will have good current
sharing. This will balance the thermals in the design. Tie the
COMPa, VFB, TRACK/SS and RUN pins of each LTM4645
together to share the current evenly. Figures 25 and 28
show a schematic of the parallel design.
Table 2. PHASMD and CLKOUT Signal Relationship
PHASMD
GND
1/4 INTVCC
FLOAT
3/4 INTVCC
INTVCC
CLKOUT
90°
90°
120°
60°
180°
A multiphase power supply could significantly reduce
the amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by
the number of phases used.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 4).
Soft-Start And Output Voltage Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A capacitor on the TRACK/SS pin will program the ramp rate
of the output voltage. An internal 1.25µA current source
will charge up the external soft-start capacitor towards
INTVCC voltage. When the TRACK/SS voltage is below
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
be calculated as:
tSS = 0.6 •
0.60
0.55
0.50
CSS
1.25µA
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4645 F04
Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)
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Applications Information
where CSS is the capacitance on the TRACK/SS pin. Current foldback and forced continuous mode are disabled
during the soft-start process.
Output voltage tracking can also be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. Figure 5 and Figure 6
show an example waveform and schematic of ratiometric
tracking where the slave regulator’s output slew rate is
proportional to the master’s.
OUTPUT VOLTAGE
MASTER OUTPUT
output voltage and the master output voltage should satisfy
the following equation during start-up:
VOUT(SL) •
RFB(SL)
RFB(SL) + 60.4k
VOUT(MA) •
=
R TR(BOT)
R TR(TOP) +R TR(BOT)
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 6.
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR)
is determined by:
SLAVE OUTPUT
RFB(SL)
RFB(SL) + 60.4k
R TR(BOT)
MR
=
SR
TIME
R TR(TOP) +R TR(BOT)
4645 F05
Figure 5. Output Ratiometric Tracking Waveform
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
For example, VOUT(MA) = 1.5V, MR = 1.5V/1ms and
VOUT(SL) = 1.2V, SR = 1.2V/1ms, from the equation, we
could solve that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k
are a good combination for the ratiometric tracking. The
TRACK/SS pin will have the 2.5μA current source on when
a resistive divider is used to implement tracking on the
VIN
6V TO 15V
2.2Ω
SVIN
22µF
25V
×2
DRVCC INTVCC
HIZB
MODE/PLLIN
VOUT
LTM4645
VOSNS+
VFB
VOSNS–
COMPa
COMPb
FREQ
47.5k
SVIN
VIN
TRACK/SS
0.1µF
4.7µF
6.3V
4.7µF
6.3V
1µF
100µF
6.3V
×2
RFB(MA)
40.2k
VOUT
1.5V
25A
+
330µF
6.3V
×2
22µF
25V
×2
DRVCC INTVCC
VIN
HIZB
MODE/PLLIN
VOUT
LTM4645
RTR(TOP)
60.4k
VOSNS+
VFB
VOSNS–
TRACK/SS
RTR(BOT)
40.2k
COMPa
COMPb
FREQ
SGND GND
47.5k
100µF
6.3V
×2
RFB(SL)
60.4k
VOUT
1.2V
25A
+
330µF
6.3V
×2
4645 F06
SGND GND
PINS NOT USED IN THESE CIRCUITS:
CLKOUT, PGOOD, PHASMD, RUN, SW
Figure 6. Example Schematic of Ratiometric Output Voltage Tracking
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LTM4645
Applications Information
slave regulator. This will impose an offset on the TRACK/
SS pin input. Smaller value resistors with the same ratios
as the resistor values calculated from the above equation
can be used. For example, where the 60.4k is used then
a 6.04k can be used to reduce the TRACK/SS pin offset
to a negligible value.
The coincident output tracking can be recognized as a
special ratiometric output tracking in which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), waveform as shown in Figure 7.
OUTPUT VOLTAGE
MASTER OUTPUT
SLAVE OUTPUT
TIME
4645 F07
From the equation, we could easily find that, in coincident
tracking, the slave regulator’s TRACK/SS pin resistor divider
is always the same as its feedback divider:
RFB(SL) + 60.4k
=
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is build into
the LTM4645 to sense output voltages accurately at the
remote load points. This is especially true for high current
loads. It is very important that the VOSNS+ and VOSNS– are
connected properly at the remote output sense point, and
the feedback resistor RFB is connected to between VFB
pin to VOSNS– pin. Review the schematics in Figure 23
for reference.
In multiphase single output application. Only one set of
differential sensing amplifier and one set of feedback
resistor are required while connecting RUN, TRACK/SS,
VOUT, VFB and COMPa of different channels together. See
Figure 25 for paralleling application.
Figure 7. Output Coincident Tracking Waveform
RFB(SL)
In parallel operation the RUN pins can be tie together and
controlled from a single control. The RUN pin can also be
left floating. The RUN pin has a 1µA pull-up current source
that increases to 5µA during ramp-up. Please note that
the RUN pin has an ABSMAX voltage of 6V.
R TR(BOT)
Power Good
The PGOOD pins are open-drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±7.5% window around the regulation point. A resistor
can be pulled up to a particular supply voltage no greater
than 6V maximum for monitoring.
Overvoltage and Overcurrent Protection
R TR(TOP) +R TR(BOT)
For example, RTR(TOP) = 60.4k and RTR(BOT) = 60.4k is a
good combination for coincident tracking for a VOUT(MA)
=1 .5V and VOUT(SL) = 1.2V application.
Run Enable
The RUN pin has an enable threshold of 1.45V maximum,
typically 1.35V with 180mV of hysteresis. It controls the
turn-on of the µModule. The RUN pin can be pulled up to
VIN for 5V operation, or a 5V Zener diode can be placed
on the pin and a 10k to 100k resistor can be placed up to
higher than 5V input for enabling the µModule. The RUN
pin can also be used for output voltage sequencing.
The LTM4645 has over current protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current. An
overvoltage condition (OVP) above 10% of the regulated
output voltage will force the top MOSFET off and the bottom
MOSFET on until the condition is cleared. Foldback current limit is disabled during soft-start or tracking start-up.
Pre-Biased Output Start-Up
In the application that require the power supply to start
up with a pre-bias on the output capacitors, the LTM4645
module can safely power up into a pre-biased output
without discharging it.
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The LTM4645 accomplishes this by disabling both the top
and bottom MOSFETs until the TRACK/SS pin voltage and
the internal soft-start voltage are above the VFB pin voltage.
N+1 Phase Redundancy and Hot Swap
The HIZB pin can be used to force both top and bottom
MOSFET to turn off while not pulling down the COMPa and
TRACK/SS pins. In a multiphase system N+1 redundancy
can be achieved via the HIZB pin. When combined with a
hot swap controller, such as the LTC4211, the HIZB pin
could be connected to the gate of the hot swap switch.
When a damaged MOSFET triggers the hot swap controller, it also disables the corresponding channel’s power,
disconnecting it. Since COMPa and TRACK/SS pins are
unaffected, it does not affect the rest of the system. The
propagation delay from HIZB falling to both top and bottom
MOSFET turned off is <200ns. See Figure 27 for example.
SW Pins and Snubbering Circuit
The SW pin is generally for testing purposes by monitoring the pin. The SW pin can also be used to dampen out
switch node ringing caused by LC parasitic in the switched
current path. Usually a series R-C combination is used
called a snubber circuit. The resistor will dampen the
resonance and the capacitor is chosen to only affect the
high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z
can be calculated:
ZL = 2π • f • L
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
ZC =
1
2π • f •C
These values are a good place to start. Modification to
these components should be made to attenuate the ringing with the least amount the power loss.
Stability Compensation
The LTM4645 has already been internally optimized and
compensated for all output voltages and capacitor combinations including all ceramic capacitor applications when
COMPb is tied to COMPa. Please note that a 22pF to
47pF feedforward capacitor (CFF) is required connecting
from VOUT to VFB pin for all ceramic capacitor application
to achieve high bandwidth control loop compensation
with enough phase margin. Table 5 is provided for most
application requirements using the optimized internal
compensation. For specific optimized requirement, disconnect COMPb from COMPa and apply a Type II C-R-C
compensation network from COMPa to SGND to achieve
external compensation. The LTpowerCAD design tool is
available to download online to perform specific control
loop optimization and analyze the control stability and load
transient performance.
SVIN, PVIN, INTVCC AND DRVCC
SVIN is the filtered input voltage to the internal 5.5V LDO
regulator to power the control circuitry of the regulator.
Connect SVIN to VIN through a 2.2Ω and 1µF R-C filter.
INTVCC is the output of the 5.5V LDO. Decouple it with
a minimum 2.2µF ceramic capacitor. Connect INTVCC to
SVIN directly if SVIN is less than 6V.
PVIN is the power input connected to power MOSFETs and
the DRVCC is the supply voltage for the driver circuity to
drive both power MOSFETs. DRVCC could connect to an
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LTM4645
Applications Information
external supply higher than 4.5V or VIN(VIN < 6V) directly
through a 2.2Ω plus 1µF R-C filter. In the application with
the input voltage 6V or above, DRVCC could also connect
to INTVCC 5.5V output directly.
See Figure 23 for a typical application circuit for input 6V
or above. See Figure 24 for a typical application circuit for
input from 4.7V to 5.5V.
Please note that INTVCC and DRVCC has 6V ABSMAX
voltage rating.
Temperature Monitoring
Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage
and temperature described by the classic diode equation:
 V 
ID =IS • e  D 
 η• VT 
or
I
VD = η• VT •In D
IS
where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can
be broken out to:
KD =
η•k
q
where KD = 8.62 • 10−5, and knowing ln(ID/IS) is always
positive because ID is always greater than IS, leaves us
with the equation that:
I
VD = T (KELVIN) •KD •In D
IS
where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current
source has an approximate –2mV/°C temperature relationship (Figure 8), which is at odds with the equation. In
fact, the IS term increases with temperature, reducing the
ln(ID/IS) absolute value yielding an approximate –2mV/°C
composite diode voltage slope.
To obtain a linear voltage proportional to temperature
we cancel the IS variable in the natural logarithm term to
remove the IS dependency from the equation 1. This is
accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2) and subtracting we get:
I
I
∆VD = T(KELVIN)•KD •IN 1 – T(KELVIN)•KD •IN 2
IS
IS
k•T
q
0.8
0.7
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable temperature sensors. The IS term in the previous equation is
the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The IS term
varies from process to process, varies with temperature,
DIODE VOLTAGE (V)
VT =
and by definition must always be less than ID. Combining
all of the constants into one term:
0.6
0.5
0.4
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4645 F08
Figure 8. Diode Voltage VD vs Temperature T(°C)
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Combining like terms, then simplifying the natural log
terms yields:
∆VD = T(KELVIN) • KD • lN(10)
and redefining constant
K'D = KD •IN(10) =
198µV
K
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
yields
∆VD = K'D • T(KELVIN)
Solving for temperature:
T(KELVIN) =
section are, in and of themselves, not relevant to providing
guidance of thermal performance; instead, the derating
curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s
application usage, and can be adapted to correlate thermal
performance to one’s own application.
∆VD
(°CELSIUS) = T(KELVIN)– 273.15
K'D
where
300°K = 27°C
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
The diode connected PNP transistor between the TEMP+
and TEMP– pin can be used to monitor the internal temperature of the LTM4645. See Figure 23 for an example.
Thermal Considerations
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on
an µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients in
found in JESD 51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with six layers.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θJCbottom and the thermal resistance of
the bottom of the part through the solder joints and a
portion of the board. The board temperature is measured
a specified distance from the package.
4645f
For more information www.linear.com/LTM4645
19
LTM4645
Applications Information
A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package. As a
practical matter, it should be clear to the reader that no
individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4645, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4645 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4645 with heat sink and airflow;
(4) having solved for and analyzed these thermal resistance values and simulated various operating conditions
in the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operating the device at the same power loss as that which was
simulated. The outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
At
BOARD-TO-AMBIENT
RESISTANCE
4645 F09
µMODULE DEVICE
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
4645f
20
For more information www.linear.com/LTM4645
LTM4645
Applications Information
The LTM4645 has been designed to effectively remove
heat from both the top and bottom of the package. The
bottom substrate material has very low thermal resistance
to the printed circuit board. An external heat sink can be
applied to the top of the device for excellent heat sinking
with airflow. Basically all power dissipating devices are
mounted directly to the substrate and the top exposed
metal. This provides two low thermal resistance paths to
remove heat.
Figures 10 and 11 show the thermal images of the LTM4645
with no heat sink and no airflow running at 1V/25A and
1.8V/25A.
Safety Considerations
The LTM4645 modules do not provide isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET fails,
then turning it off will not resolve the overvoltage, thus
the internal bottom MOSFET will turn on indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
device does support over current protection. The TEMP+
and TEMP– pins are provided for monitoring internal temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the HIZB pin.
Output Current Derating
Figure 10. LTM4645 12VIN to 1VOUT at 25A with No Air Flow
and No Heat Sink
Figure 11. LTM4645 12VIN to 1.8VOUT at 25A with No Air
Flow and No Heat Sink
The 1V, 1.5V power loss curves in Figures 12 to 13 can
be used in coordination with the load current derating
curves in Figures 14 to 21 for calculating an approximate
θJA thermal resistance for the LTM4645 with various heat
sinking and airflow conditions. The power loss curves
are taken at room temperature and are increased with a
multiplicative factor according to the junction temperature,
which is 1.3 for 120°C. The derating curves are plotted
with the output current starting at 25A and the ambient
temperature at ~30°C. The output voltages are 1V and
1.5V. These are chosen to include the lower and higher
output voltage ranges for correlating the thermal resistance.
Thermal models are derived from several temperature
measurements in a controlled temperature chamber along
with thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased
with and without airflow. The power loss increase with
4645f
For more information www.linear.com/LTM4645
21
LTM4645
6
30
5
5
25
4
4
3
2
1
0
5
15
10
LOAD CURRENT (A)
20
3
2
1
VIN = 5V
VIN = 12V
0
LOAD CURRENT (A)
6
POWER LOSS (W)
POWER LOSS (W)
Applications Information
0
25
15
10
0
5
15
10
LOAD CURRENT (A)
20
0
25
Figure 13. 1.5V Power Loss Curve
25
25
0LMF
200LMF
400LMF
0
30
40
LOAD CURRENT (A)
25
LOAD CURRENT (A)
30
5
20
15
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
LOAD CURRENT (A)
LOAD CURRENT (A)
25
20
15
10
0LMF
200LMF
400LMF
40
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4645 F17
Figure 16. 12V to 1V Derating Curve,
BGA Heat Sink
25
30
0LMF
200LMF
400LMF
4645 F16
30
0
10
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
5
15
5
4645 F15
Figure 15. 5V to 1V Derating Curve,
No Heat Sink
20
0LMF
200LMF
400LMF
5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 14. 12V to 1V Derating Curve,
No Heat Sink
30
10
40
4645 F14
30
15
30
4645 F13
Figure 12. 1V Power Loss Curve
20
0LMF
200LMF
400LMF
5
VIN = 5V
VIN = 12V
4645 F12
LOAD CURRENT (A)
20
20
15
10
0LMF
200LMF
400LMF
5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4645 F19
4645 F18
Figure 18. 12V to 1.5V Derating Curve,
No Heat Sink
Figure 17. 5V to 1V Derating Curve,
BGA Heat Sink
Figure 19. 5V to 1.5V Derating Curve,
No Heat Sink
4645f
22
For more information www.linear.com/LTM4645
LTM4645
30
30
25
25
LOAD CURRENT (A)
LOAD CURRENT (A)
Applications Information
20
15
10
15
10
0LMF
200LMF
400LMF
5
0
20
30
40
0LMF
200LMF
400LMF
5
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4645 F21
4645 F20
Figure 20. 12V to 1.5V Derating Curve, BGA Heat Sink
Figure 21. 5V to 1.5V Derating Curve, BGA Heat Sink
Table 3. 1.0V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
Figures 14, 15
Figures 14, 15
Figures 14, 15
Figures 16, 17
Figures 16, 17
Figures 16, 17
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
Figure 12
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
Figures 18, 19
Figures 18, 19
Figures 18, 19
Figures 20, 21
Figures 20, 21
Figures 20, 21
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
0
200
400
0
200
400
None
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
θJA (°C/W)
9
6.5
6
8.5
5.5
5
Table 4. 1.5V Output
Heat Sink Manufacturer
Part Number
Website
Aavid Thermalloy
375424B00034G
www.aavid.com
Cool Innovations
4-050503P to 4-050508P
www.coolinnovations.com
θJA (°C/W)
9
6.5
6
8.5
5.5
5
4645f
For more information www.linear.com/LTM4645
23
LTM4645
Applications Information
Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values
CIN VENDORS VALUE
PART NUMBER
COUT VENDORS
Panasonic SP-CAP
Panasonic POSCAP
Panasonic POSCAP
Murata
Taiyo Yuden
22µF, 25V, 1206, X7S
C3216X7S0J226M
Murata
22µF, 25V,1206, X5R
GRM31CR61E226KE15L TDK
Bulk
Ceramic
VALUE
470µF 2.5V
470µF 2.5V
470µF 6.3V
100µF, 6.3V, 1206, X5R
PART NUMBER
EEFSX0E471E4
2R5TPD470M5
6TPD470M5
GRM31CR60J107M
100µF, 6.3V, 1206, X5R
C3216X5R0G107M
Murata
220µF, 4V, 1206, X5R
GRM31CR60G227M
Taiyo Yuden
220µF, 2.5V, 1206, X5R
PMK316DBJ227MLHT
Ceramic Cap Only
VIN
(V)
5, 12
VOUT
(V)
0.9
CIN
(CERAMIC)
COUT
(CERAMIC)
22µF × 3
100µF × 6
COUT
(BULK)
N/A
CFF
(pF)
47pF
DROOP
(mV)
0
P-P
DEVIATION
(mV)
109
RECOVERY
TIME
(µs)
130
LOAD
STEP
(A)
6
SLEW
RATE
(A/µs)
10
RFB
(kΩ)
121
FREQ
(kHz)
500
5, 12
1
22µF × 3
100µF × 6
N/A
47µF
0
102
130
6
10
90.9
600
5, 12
1.2
22µF × 3
100µF × 6
N/A
47µF
0
97
140
6
10
60.4
700
5, 12
1.5
22µF × 3
100µF × 6
N/A
47µF
0
100
140
6
10
40.2
800
5, 12
1.8
22µF × 3
100µF × 6
N/A
47µF
0
107
150
6
10
30.1
900
CFF
(pF)
N/A
DROOP
(mV)
0
P-P
DEVIATION
(mV)
109
RECOVERY
TIME
(µs)
30
LOAD
STEP
(A)
6
SLEW
RATE
(A/µs)
10
RFB
(kΩ)
121
FREQ
(kHz)
500
N/A
0
107
40
6
10
90.9
600
Bulk and Ceramic Cap
VIN
(V)
5, 12
VOUT
(V)
0.9
CIN
(CERAMIC)
COUT
(CERAMIC)
22µF × 3
47µF × 2
COUT
(BULK)
470µF
5, 12
1
22µF × 3
47µF × 2
470µF
5, 12
1.2
22µF × 3
47µF × 2
470µF
N/A
0
122
40
6
10
60.4
700
5, 12
1.5
22µF × 3
47µF × 2
470µF
N/A
0
131
50
6
10
40.2
800
5, 12
1.8
22µF × 3
47µF × 2
470µF
N/A
0
142
50
6
10
30.1
900
4645f
24
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LTM4645
Applications Information
ambient temperature change is factored into the derating
curves. The junctions are maintained at ~120°C maximum
while lowering output current or power with increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient temperature
is increased. The monitored junction temperature of 120°C
minus the ambient operating temperature specifies how
much module temperature rise can be allowed, as an example, in Figure 20 the load current is derated to 15A at
100°C with no air or heat sink and the power loss for the
12V to 1.5V at 15A output is about 3.5W. The 3.5W loss
is calculated with the 2.7W room temperature loss from
the 12V to 1.5V power loss curve at 15A, from Figure 13,
and the 1.3 multiplying factor at 120°C junction. If the
100°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 20°C divided
by 3.5W equals a 5.7°C/W θJA thermal resistance. Table
4 specifies a 5.5°C/W value which is very close. Tables 3
and 4 provide equivalent thermal resistances for 1.0V and
1.5V outputs with and without airflow and heat sinking. The
derived thermal resistances in Tables 3 and 4 for the various
conditions can be multiplied by the calculated power loss
as a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics
section and adjusted with the above ambient temperature
multiplicative factors. The printed circuit board is a 1.6mm
thick six layer board with two ounce copper for all layers.
The PCB dimensions are 95mm × 76mm. The BGA heat
sinks are listed in Table 4.
Layout Checklist/Example
The high integration of LTM4645 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure 22 gives a good example of the recommended layout.
4645f
For more information www.linear.com/LTM4645
25
LTM4645
Applications Information
COUT
VOUT
GND
GND
VIN
CIN
4645 F22
Figure 22. Recommended PCB Layout
4645f
26
For more information www.linear.com/LTM4645
LTM4645
Typical Applications
1µF
HIZB
DRVCC
4.7µF
INTVCC
RUN
VIN
22µF
25V
×2
MODE/PLLIN
VIN
6V TO 15V
SVIN
2.2Ω
100k
PGOOD
PGOOD
VOUT
TRACK/SS
0.1µF
VOSNS+
LTM4645
COMPa
VFB
COMPb
VOSNS–
47pF
90.9k
TEMP–
SGND
GND
TEMP+
FREQ
48.7k
100µF
6.3V
×4
VOUT
1V
25A
4645 F23
DIGITAL TELEMETRY FOR
TEMPERATURE MONITORING
PINS NOT USED IN THIS
CIRCUIT: CLKOUT, PHASMD,
PWM, SW
Figure 23. Typical 6V to 15V Input 1.0V at 25A Output Design
VIN
22µF
16V
×2
HIZB
MODE/PLLIN
RUN
SVIN
PGOOD
47µF
6.3V
VOSNS+
LTM4645
COMPa
VFB
COMPb
VOSNS–
60.4k
PINS NOT USED IN THIS
CIRCUIT: CLKOUT, PHASMD,
PWM, SW
+
330µF
6.3V
TEMP–
TEMP+
SGND
FREQ
48.7k
VOUT
1.2V
25A
VOUT
TRACK/SS
0.1µF
100k
PGOOD
DRVCC
GND
VIN
4.7V TO 5.5V
4.7µF
INTVCC
1µF
2.2Ω
DIGITAL TELEMETRY FOR
TEMPERATURE MONITORING
4645 F24
Figure 24. Typical 4.7V to 5.5V Input 1.2V at 25A Output Design
4645f
For more information www.linear.com/LTM4645
27
LTM4645
VIN
6V TO 15V
VIN
22µF
25V
×2
DRVCC
1µF
4.7µF
INTVCC
SVIN
PHMODE
CLKOUT
2.2Ω
MODE/PLLIN
Typical Applications
100k
HIZB
PGOOD
LTM4645
U1
RUN
TRACK/SS
PGOOD
VOUT
VOSNS+
COMPa
VFB
COMPb
VOSNS–
FB
90.9k
47µF
6.3V
×2
+
330µF
4V
TEMP–
SGND
GND
TEMP+
FREQ
48.7k
VOUT
1V
50A
VIN
22µF
25V
×2
HIZB
PGOOD
RUN
PGOOD
VOUT
TRACK/SS
LTM4645
U2
COMPa
0.1µF
4.7µF
INTVCC
SVIN
DRVCC
MODE/PLLIN
TEMPERATURE
MONITORING
VFB
COMPb
FB
VOSNS–
47µF
6.3V
×2
+
330µF
4V
PINS NOT USED IN CIRCUIT
LTM4647 U1: PWM, SW
TEMP–
TEMP+
SGND
48.7k
GND
FREQ
TEMPERATURE
MONITORING
PINS NOT USED IN CIRCUIT LTM4647 U2:
CLKOUT, PHASMD, PWM, SW, VOSNS+
4645 F25
Figure 25. 6V to 15V Input, 1.0V Output at 50A
4645f
28
For more information www.linear.com/LTM4645
LTM4645
22µF
25V
×2
VIN
HIZB
100k
PGOOD
LTM4645
VOSNS+
TRACK/SS
COMPb
VOSNS–
SVIN
HIZB
LTM4645
TRACK/SS
53.6k
90.9k
47µF
6.3V
×2
+
330µF
4V
4.7µF
PGOOD
PGOOD2
VOUT2
1.2V
25A
VOUT
VOSNS+
VFB
COMPb
VOSNS–
FREQ
VOUT1
1V
25A
100k
COMPa
GND
90.9k
SGND
60.4k
VIN
22µF
25V
×2
DRVCC
48.7k
MODE/PLLIN
FREQ
SGND
VFB
GND
COMPa
RUN
0.1µF
PGOOD1
VOUT
INTVCC
VIN
6V TO 15V
DRVCC
1µF
4.7µF
INTVCC
SVIN
MODE/PLLIN
2.2Ω
RUN
Typical Applications
60.4k
47µF
6.3V
×2
+
330µF
4V
4645 F25
PINS NOT USED IN LTM4647 U1 AND U2
CIRCUITS: CLKOUT, PHASMD, PWM, SW, TEMP+, TEMP–
Figure 26. 6V to 15V Input, 1.0V and 1.2V Output with Tracking
4645f
For more information www.linear.com/LTM4645
29
VIN
6V TO
15V BUS
100pF
GATE2
OUT2
100pF
100pF
22µF
25V
×2
INTVCC4
10k
0.1µF
48.7k
HIZB4
48.7k
HIZB3
48.7k
HIZB2
48.7k
HIZB1
LTM4645
U1
LTM4645
U2
LTM4645
U3
FREQ
COMPb
LTM4645
TRACK/SS
U4
COMPa
RUN
HIZB
VIN
SVIN
FREQ
COMPb
COMPa
TRACK/SS
RUN
HIZB
VIN
SVIN
CLK34
FREQ
COMPb
COMPa
TRACK/SS
RUN
HIZB
VIN
SVIN
CLK23
FREQ
COMPb
COMPa
TRACK/SS
RUN
HIZB
VIN
SVIN
VOSNS–
VFB
VOUT
FB
CLK34
INTVCC4
VOSNS–
VFB
VOUT
FB
CLK23
INTVCC3
VOSNS–
VFB
VOUT
FB
CLK12
INTVCC2
VOSNS–
VFB
VOSNS+
VOUT
INTVCC1
4.7µF
6.3V
4.7µF
6.3V
4.7µF
6.3V
FB
RFB6
60.4k
INTVCC1
100µF
6.3V
×2
100µF
6.3V
×2
INTVCC4
INTVCC3
INTVCC2
100µF
6.3V
×2
100µF
6.3V
×2
4.7µF
6.3V
Figure 27. 3-Phase 1V at 75A Design with Extra 1 Phase 25A Redundancy
PINS NOT USED IN CIRCUIT
LTM4647 U4: CLKOUT, PGOOD, PWM, SW
TEMP+, TEMP–, VOSNS+
PINS NOT USED IN CIRCUIT
LTM4647 U3: PGOOD, PWM, SW
TEMP+, TEMP–, VOSNS+
FDMS86500DC
SENSE2
0.007Ω
VCC2
FTMR2
HIZB4
LTC4226CUD-1
FAULT2
GND
CLS
HIZB3
R46
10k
FTMR1
OUT1
FAULT1
GATE1
INTVCC3
ON2
SENSE1
1N448HWT
22µF
25V
×2
22µF
25V
×2
INTVCC2
10k
ON1
VCC1
1N448HWT
PINS NOT USED IN CIRCUIT
LTM4647 U2: PGOOD, PWM, SW
TEMP+, TEMP–, VOSNS+
10k
38.3k
OUT2
FDMS86500DC
CMHZ4683
0.007Ω
2
GATE2
FDMS86500DC
SENSE2
0.007Ω
VCC2
GND
FTMR2
HIZB1
CLS
LTC4226CUD-1
HIZB2
100pF
INTVCC1
R58
10k
FAULT2
OUT1
FTMR1
GATE1
1N448HWT
FAULT1
SENSE1
1N448HWT
ON2
VCC1
FDMS86500DC
22µF
25V
×2
1µF
ON1
2.4M
CMHZ4701
1
2
10k
38.3k
0.007Ω
2
CMHZ4683
PINS NOT USED IN CIRCUIT
LTM4647 U1: MODE/PLLIN, PGOOD,
PWM, SW, TEMP+, TEMP–
4.7µF
25V
30.1k
4.7µF
25V
2.4M
CMHZ4701
1
2
CLKOUT
GND
GND
30.1k
CLKOUT
GND
CLKOUT
GND
CLK12
PHASMD
SGND
PHASMD
SGND
PHASMD
SGND
PHASMD
SGND
DRVCC
DRVCC
DRVCC
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
INTVCC
INTVCC
INTVCC
1
10
3 UV
4 OV
1
2
3 UV
4 OV
1
2
3 UV
4 OV
1
2
7
4
R185
100Ω
12 11
8
REV
9 13
0.1µF
7
R186
100Ω
12 11
8
0.1µF
REV
9 13
4
LTC4352CDD U9
1µF
10
R184
100Ω
8
LTC4352CDD U8
1µF
10
12 11
REV
9 13
0.1µF
1µF
7
LTC4352CDD U10
2
3 UV
4 OV
7
4
LTC4352CDD U7
1µF
10
4
R183
100Ω
12 11
8
0.1µF
CPO
VCC
DRVCC
VIN
VCC
VIN
REV
REV
REV
VIN
GATE
GATE
GATE
GATE
VCC
CPO
CPO
CPO
REV
INTVCC
GND
REV
9 13
GND
VCC
GND
GND
SOURCE
EP
SOURCE
EP
For more information www.linear.com/LTM4645
VIN
SOURCE
EP
SOURCE
EP
FAULT
OUT
FAULT
OUT
6
6
HIZB4
4645 F27
Q9
BSC010NE2LS
HIZB3
Q8
BSC010NE2LS
HIZB2
Q7
BSC010NE2LS
HIZB1
Q1
BSC010NE2LS
PIN NOT USED IN CIRCUIT
LTC4352CDD U7, U8, U9, U10:
STATUS
FAULT
6
FAULT 6
OUT
30
OUT
2.2Ω
330µF
6.3V
×6
VOUT
1V
75A
LTM4645
Typical Applications
4645f
LTM4645
VIN
6V TO 15V
VIN
22µF
25V
×8
DRVCC
1µF
HIZB
U1 PINS NOT USED: PWM, SW
TEMP+, TEMP–
100k
PGOOD
PGOOD
RUN
COMP
2.2µF
INTVCC
SVIN
PHASMD
CLKOUT
2.2Ω
MODE/PLLIN
Typical Applications
VOUT
LTM4645
U1
TRACK/SS
22pF
VOSNS+
COMPa
VFB
COMPb
VOSNS–
FB
90.9k
100µF
6.3V
×6
VOUT
1.0V
100A
HIZB
PGOOD
RUN
PGOOD
VOUT
TRACK/SS
U2 PINS NOT USED: PWM, SW
TEMP+, TEMP–, VOSNS+
2.2µF
INTVCC
DRVCC
VIN
PHASMD
SVIN
MODE/PLLIN
CLKOUT
GND
48.7k
SGND
FREQ
VFB
LTM4645
U2
COMPa
100µF
6.3V
×6
FB
VOSNS–
COMPb
HIZB
PGOOD
RUN
PGOOD
VOUT
TRACK/SS
U3 PINS NOT USED: PWM, SW
TEMP+, TEMP–, VOSNS+
2.2µF
INTVCC
DRVCC
VIN
PHASMD
SVIN
MODE/PLLIN
GND
CLKOUT
SGND
FREQ
48.7k
VFB
LTM4645
U3
COMPa
100µF
6.3V
×6
FB
VOSNS–
COMPb
HIZB4
HIZB
RUN
PGOOD
PGOOD
VOUT
TRACK/SS
U4 PINS NOT USED: CLKOUT, PWM, SW
TEMP+, TEMP–, VOSNS+
2.2µF
INTVCC
VIN
DRVCC
SVIN
PHASMD
MODE/PLLIN
GND
SGND
FREQ
48.7k
LTM4645
U4
COMPa
COMPb
VFB
FB
VOSNS–
100µF
6.3V
×6
48.7k
SGND
0.1µF
GND
FREQ
4645 F28
Figure 28. 4 Phase 1V at 100A Design
For more information www.linear.com/LTM4645
4645f
31
LTM4645
Package Description
LTM4645 Component BGA Pinout
PIN ID
A1
FUNCTION
PIN ID
VIN
B1
FUNCTION
VIN
PIN ID
C1
FUNCTION
VIN
PIN ID
D1
FUNCTION
GND
PIN ID
FUNCTION
PIN ID
FUNCTION
E1
TEMP–
F1
TEMP+
A2
VIN
B2
VIN
C2
VIN
D2
GND
E2
GND
F2
GND
A3
VIN
B3
GND
C3
GND
D3
GND
E3
GND
F3
SW
A4
GND
B4
PWM
C4
GND
D4
GND
E4
GND
F4
GND
A5
GND
B5
CLKOUT
C5
DRVCC
D5
TEST2
E5
HIZB
F5
TRACK/SS
A6
RUN
B6
TEST1
C6
INTVCC
D6
SVIN
E6
VFB
F6
GND
A7
GND
B7
MODE/PLLIN
C7
PHASMD
D7
FREQ
E7
SGND
F7
TEST3
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
VOUT
K1
VOUT
L1
VOUT
G2
GND
H2
GND
J2
VOUT
K2
VOUT
L2
VOUT
G3
GND
H3
GND
J3
VOUT
K3
VOUT
L3
VOUT
G4
GND
H4
GND
J4
VOUT
K4
VOUT
L4
VOUT
G5
H5
GND
J5
GND
K5
GND
L5
VOUT
G6
VOSNS–
VOSNS+
H6
COMPa
J6
GND
K6
GND
L6
VOUT
G7
PGOOD
H7
COMPb
J7
GND
K7
GND
L7
VOUT
4645f
32
For more information www.linear.com/LTM4645
0.630 ±0.025 Ø 77x
2.540
SUGGESTED PCB LAYOUT
TOP VIEW
1.270
PACKAGE TOP VIEW
0.3175
0.000
0.3175
4
1.270
PIN “A1”
CORNER
E
2.540
aaa Z
3.810
3.810
Y
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTM4645
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
6.350
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
D
X
aaa Z
// bbb Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
H1
SUBSTRATE
A1
NOM
3.51
0.60
2.91
0.75
0.63
15.00
9.00
1.27
12.70
7.62
0.41
2.50
A
A2
MAX
3.71
0.70
3.01
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
0.46
2.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 77
0.36
2.45
MIN
3.31
0.50
2.81
0.60
0.60
b1
DIMENSIONS
ddd M Z X Y
eee M Z
DETAIL A
Øb (77 PLACES)
DETAIL B
H2
MOLD
CAP
ccc Z
Z
Z
(Reference LTC DWG# 05-08-1542 Rev Ø)
BGA Package
77-Lead (15.00mm × 9.00mm × 3.51mm)
F
e
7
5
4
3
2
1
DETAIL A
PACKAGE BOTTOM VIEW
6
G
L
K
J
H
G
F
E
D
C
B
A
PIN 1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
7
!
BGA 77 1016 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu
OR Sn Pb EUTECTIC
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
7
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
b
3
SEE NOTES
LTM4645
Package Description
Please refer to http://www.linear.com/product/LTM4645#packaging for the most recent package drawings.
4645f
33
LTM4645
Package Photo
Design Resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
Related Parts
PART
NUMBER
DESCRIPTION
COMMENTS
LTM4637
20A µModule Regulator
4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm (LGA), 15mm ×
15mm × 4.92mm (BGA)
LTM4647
30A µModule Regulator, Pin Compatible with LTM4645
4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V. 9mm × 15mm × 5.01mm (BGA)
LTM4636
40A µModule Regulator, ±1% VOUT Accuracy
4.75V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.12mm (BGA)
LTM4631
Dual 10A, Single 20A µModule Regulator, 1.91mm
Package Height
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 1.91mm (LGA)
LTM4620A
Dual 13A or Single 26A µModule Regulator, VOUT ≤ 5.3V 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm (LGA), 15mm ×
15mm × 5.01mm (BGA)
LTM4630/ Dual 18A or Single 36A µModule Regulator, External
LTM4630-1 Compensation(–1), ±0.8V VOUT Accuracy (–1A)
LTM4630A
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm ×
16mm × 5.01mm (BGA)
Dual 18A or Single 36A µModule Regulator, VOUT ≤ 5.3V 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V, 16mm × 16mm × 4.41mm (LGA)
LTM4650/ Dual 25A or Single 50A µModule Regulator, External
LTM4650-1 Compensation(–1), ±0.8V VOUT Accuracy (–1A)
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)
LTM4650A
Dual 25A or Single 50A µModule Regulator, VOUT ≤ 5.5V 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.5V. 16mm × 16mm × 5.01mm (BGA)
LTM4676A
Dual 13A or Single 26A µModule Regulator with PSM
4.5V ≤ VIN ≤ 17V, 0.5V ≤ VOUT ≤ 5.5V, 16mm × 16mm × 5.01mm (BGA)
LTM4677
Dual 25A or Single 50A µModule Regulator with PSM
4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)
4645f
34
LT 0917 • PRINTED IN USA
For more information www.linear.com/LTM4645
www.linear.com/LTM4645
 LINEAR TECHNOLOGY CORPORATION 2017
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