HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs REJ03D0052-0300Z (Previous ADE-205-173A(Z)) Rev.3.00 Oct.02.2003 Description The HD74ALVCH162244 is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. • • • • • • VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±12 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors All outputs have equivalent 26 Ω series resistors, so no external resistors are required. Rev.3.00, Oct.02.2003, page 1 of 9 HD74ALVCH162244 Function table Inputs Output Y OE A L H H L L L H X Z H : High level L : Low level X : Immaterial Z : High impedance Rev.3.00, Oct.02.2003, page 2 of 9 HD74ALVCH162244 Pin Arrangement 1OE 1 48 2OE 1Y1 2 47 1A1 1Y2 3 46 1A2 GND 4 45 GND 1Y3 5 44 1A3 1Y4 6 43 1A4 VCC 7 42 VCC 2Y1 8 41 2A1 2Y2 9 40 2A2 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 3Y1 13 36 3A1 3Y2 14 35 3A2 GND 15 34 GND 3Y3 16 33 3A3 3Y4 17 32 3A4 VCC 18 31 VCC 4Y1 19 30 4A1 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE (Top view) Rev.3.00, Oct.02.2003, page 3 of 9 HD74ALVCH162244 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 4.6 V Input voltage *1 VI –0.5 to 4.6 V VO –0.5 to VCC +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin ICC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 0.85 W Storage temperature Tstg –65 to 150 °C Output voltage *1, 2 Conditions TSSOP Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current IOH — –6 mA — –8 VCC = 2.7 V — –12 VCC = 3.0 V — 6 — 8 VCC = 2.7 V — 12 VCC = 3.0 V Low level output current IOL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. Rev.3.00, Oct.02.2003, page 4 of 9 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH162244 Logic Diagram 1OE 1A1 1A2 1A3 1A4 3OE 3A1 3A2 3A3 3A4 1 2OE 47 2 46 3 44 5 43 6 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 25 4OE 36 13 35 14 33 16 32 17 Rev.3.00, Oct.02.2003, page 5 of 9 3Y1 4A1 3Y2 4A2 3Y3 4A3 3Y4 4A4 48 41 8 40 9 38 11 37 12 2Y1 2Y2 2Y3 2Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 HD74ALVCH162244 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Input voltage VIH VIL Output voltage VOH Max Unit Test Conditions 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 2.3 to 3.6 VCC–0.2 — V IOH = –100 µA 2.3 1.9 — IOH = –4 mA, VIH = 1.7 V 2.3 1.7 — IOH = –6 mA, VIH = 1.7 V 3.0 2.4 — IOH = –6 mA, VIH = 2.0 V 2.7 2.0 — IOH = –8 mA, VIH = 2.0 V 3.0 2.0 — IOH = –12 mA, VIH = 2.0 V 2.3 to 3.6 — 0.2 IOL = 100 µA 2.3 — 0.4 IOL = 4 mA, VIL = 0.7 V 2.3 — 0.55 IOL = 6 mA, VIL = 0.7 V 3.0 — 0.55 IOL = 6 mA, VIL = 0.8 V 2.7 — 0.6 IOL = 8 mA, VIL = 0.8 V 3.0 — 0.8 IOL = 12 mA, VIL = 0.8 V IIN 3.6 — ±5 IIN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V *1 VOL Input current Min µA VIN = VCC or GND Off state output current IOZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current ICC 3.6 — 40 µA VIN = VCC or GND ∆ICC 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at VCC or GND Notes: 1. This is the bus hold maximum dynamic current required to switch the input from one state to another. Rev.3.00, Oct.02.2003, page 6 of 9 HD74ALVCH162244 Switching Characteristics (cont) (Ta = –40 to 85°C) Item Symbol VCC (V) Propagation delay time tPLH tPHL Output enable time Output disable time Input capacitance Output capacitance Min Typ Max Unit FROM (Input) TO (Output) 2.5±0.2 1.0 — 4.9 ns A Y 2.7 — 4.7 3.3±0.3 1.0 — 4.2 tZH 2.5±0.2 1.0 — 6.8 ns OE Y tZL 2.7 ns OE Y pF Control inputs — — 6.7 3.3±0.3 1.0 — 5.6 tHZ 2.5±0.2 1.0 — 6.3 tLZ 2.7 — 5.7 3.3±0.3 1.0 — 5.5 3.3 — 3.0 — 3.3 — 6.0 — 3.3 — 7.0 — CIN CO — — Data inputs pF Outputs Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ Note: 1. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 2 × VCC 6.0 V CLincludes probe and jig capacitance. Rev.3.00, Oct.02.2003, page 7 of 9 HD74ALVCH162244 Waveforms – 1 tf tr Input VIH 90 % Vref 90 % Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL Waveforms – 2 tr tf 90 % Vref Output Control VIH 90 % Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B Vref1 VOL t HZ VOH Vref2 Vref ≈VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1 Notes: 1. 2. 3. 4. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V VCC 2.7 V 1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH–0.15 V VOH–0.3 V VCC 3.0 V GND GND All input pulses are supplied by generators having the following characteristics : PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V) PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V) Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. The output are measured one at a time with one transition per measurement. Rev.3.00, Oct.02.2003, page 8 of 9 HD74ALVCH162244 Package Dimensions As of January, 2003 12.5 12.7 Max Unit: mm 25 6.10 48 1 *0.19 ± 0.05 0.50 24 0.08 M 1.0 8.10 ± 0.20 0.65 Max *Ni/Pd/Au plating Rev.3.00, Oct.02.2003, page 9 of 9 0.10 ± 0.05 0.10 *0.15 ± 0.05 1.20 Max 0˚ – 8˚ 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TTP-48DBV — — 0.20 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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