ON NTD4815N Power mosfet Datasheet

NTD4815N, NVD4815N
Power MOSFET
30 V, 35 A, Single N−Channel, DPAK/IPAK
Features
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
15 mW @ 10 V
30 V
D
• CPU Power Delivery
• DC−DC Converters
• High Side Switching
N−Channel
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
8.5
A
Power Dissipation
RqJA (Note 1)
TA = 25°C
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
TA = 85°C
6.5
PD
ID
TA = 85°C
1 2
1.92
6.9
3
A
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
TA = 25°C
PD
1.26
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
35
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
32.6
W
TA = 25°C
IDM
87
A
TA = 25°C
IDmaxPkg
35
A
TJ,
TSTG
−55 to
+175
°C
IS
27
A
Pulsed Drain
Current
tp=10ms
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
27
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
IL = 11 Apk, L = 1.0 mH, RG = 25 W)
EAS
60.5
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 8
1
1
W
5.3
TC = 85°C
4
2 3
3 IPAK
CASE 369AC
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
AYWW
TA = 25°C
4
4815NG
Continuous Drain
Current RqJA
(Note 1)
S
AYWW
Parameter
Power Dissipation
RqJA (Note 2)
35 A
25 mW @ 4.5 V
Applications
Steady
State
ID MAX
2
1 Drain 3
Gate Source
A
Y
WW
4815N
G
4815NG
•
•
•
•
1 2 3
Gate Drain Source
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Publication Order Number:
NTD4815N/D
NTD4815N, NVD4815N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
4.6
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient – Steady State (Note 1)
RqJA
78
Junction−to−Ambient – Steady State (Note 2)
RqJA
119
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
1.5
5.6
VGS = 10 V to
11.5 V
ID = 30 A
12
ID = 15 A
11.5
VGS = 4.5 V
ID = 30 A
21
ID = 15 A
18.3
gFS
VDS = 15 V, ID = 10 A
mV/°C
15
25
6.0
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
108
Total Gate Charge
QG(TOT)
6.0
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
770
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
181
pF
6.6
0.9
VGS = 4.5 V, VDS = 15 V; ID = 30 A
2.5
nC
3.1
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
14.1
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
10.5
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
21.4
11.4
ns
3.5
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4815N, NVD4815N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
6.3
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
17.6
ns
18.4
2.3
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
1.0
TJ = 125°C
0.92
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
15.3
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
8.7
ns
6.6
QRR
5.5
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
2.6
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD4815N, NVD4815N
TYPICAL PERFORMANCE CURVES
80
5.5 V to 10 V
5V
50
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
60
4.5 V
40
4V
30
3.8 V
3.6 V
20
3.4 V
3.2 V
10
3V
0
50
40
30
TJ = 125°C
20
TJ = 25°C
10
TJ = −55°C
1
4
3
2
5
0
2
3
4
5
6
7
8
9
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.030
ID = 30 A
TJ = 25°C
0.025
0.020
0.015
0.010
0.005
0
2
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
3
4
5
6
7
8
9
10
12
11
10
0.030
TJ = 25°C
0.025
0.020
VGS = 4.5 V
0.015
0.010
VGS = 11.5 V
0.005
0
10
5
15
20
25
30
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.0
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
60
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
70
1.5
1.0
0.5
−50 −25
1000
TJ = 125°C
100
10
0
25
50
75
100
125
150
175
4
8
12
16
20
24
28
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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32
NTD4815N, NVD4815N
C, CAPACITANCE (pF)
TJ = 25°C
Ciss
Coss
15
20
25
30
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
6
16
QT
Q1
4
VGS
10
8
3
6
2
4
1
ID = 30 A
TJ = 25°C
0
0
1
2
3
4
5
QG, TOTAL GATE CHARGE (nC)
2
0
7
6
30
1000
100
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
t, TIME (ns)
12
Q2
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
tr
td(off)
10
td(on)
tf
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
25
100
15
10
5
100 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1 ms
10 ms
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.6
0.7
0.8
0.9
1.0
1.1
Figure 10. Diode Forward Voltage vs. Current
1000
10
0.5
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
TJ = 25°C
20
0
0.4
1
I D, DRAIN CURRENT (AMPS)
14
VDS
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1500
VDS = 0 V
VGS = 0 V
1400
1300
1200
1100 Ciss
1000
900
800
700
600
500 Crss
400
300
200
100
Crss
0
5
5
10
0
10
VGS
VDS
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
70
ID = 11 A
60
50
40
30
20
10
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4815N, NVD4815N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
25°C
100°C
125°C
10
1
0.1
10
100
PULSE WIDTH (ms)
1
1000
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4815NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4815N−35G
IPAK Trimmed Lead
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units / Rail
NVD4815NT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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6
NTD4815N, NVD4815N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD4815N, NVD4815N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC
ISSUE O
B
V
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
H
D
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
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NTD4815N/D