® ISO 9001 Registered Process C3017 CMOS 3µm 10 Volt Analog Mixed Mode Electrical Characteristics T=25oC Unless otherwise noted N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTN γN βN LeffN ∆WN BVDSSN VTFP(N) Minimum 0.6 P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTP γP βP LeffP ∆WP BVDSSP VTFP(P) Minimum –0.6 Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Interpoly Oxide Thickness Gate Poly Sheet Resistance Bottom Poly Sheet Res. Metal-1 Sheet Resistance Metal-2 Sheet Resistance Passivation Thickness Symbol ρP-well(f) ρN+ xjN+ ρP+ xjP+ TGOX TP1P2 ρPOLY1 ρPOLY2 ρM1 ρM2 TPASS Minimum 3.2 16 Capacitance Gate Oxide Metal-1 to Poly-1 Metal-1 to Silicon Metal-2 to Metal-1 Poly-1 to Poly-2 Symbol COX CM1P CM1S CMM CP1P2 Minimum 0.66 © IMP, Inc. 42 2.85 Typical 0.8 0.6 47 3.2 0.7 Maximum 1.0 Typical –0.8 0.55 15 3.2 0.9 Maximum –1.0 Typical 4.8 21 0.8 80 0.7 48 60 22 22 50 30 200+900 Maximum 6.5 27 Typical 0.72 0.0523 0.30 0.0384 0.57 Maximum 0.78 52 3.55 12 12 13 2.85 19 3.55 –12 –12 50 44 15 15 0.26 0.033 0.51 100 52 30 30 0.34 0.041 0.63 Unit V V1/2 µA/V2 µm µm V V Comments 100x4µm 100x4µm 100x100µm 100x4µm Per side Unit V V1/2 µA/V2 µm µm V V Comments 100x4µm 100x4µm 100x100µm 100x4µm Per side Unit KΩ/o Ω/o µm Ω/o µm nm nm Ω/o Ω/o mΩ/o mΩ/o nm Comments P-well Unit fF/µm2 fF/µm2 fF/µm2 fF/µm2 fF/µm2 oxide+nit. Comments 91 Process C3017 Physical Characteristics Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Via Size Metal-1 Width/Space Metal-2 Width/Space Gate Poly Width/Space P <100> 15 - 25 Ω-cm 10V P-well 2 2 2.0x2.0µm 2.0x2.0µm 3.5 / 2.5µm 5.0 / 3.0µm 4.0 / 2.5µm N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Metal-1 Overlap Of Via Metal-2 Overlap Of Via Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 3.0 / 3.0µm 12µm 2.5µm 1.5µm 1.0µm 1.0µm 1.75µm 1.5µm 100x100µm 5.0µm 80.0 µm Special Feature of C3017 Process: P-well analog process with double metal CMOS 3.0 µm technology. Second metal Metal 1 VIA Poly gate SIO2 A1 LTO Contact Poly gate Sidewall spacer n-epi N+ substrate p Bottom poly Field Oxide n+ Source p p+ Drain p-well p+ N– substrate contact SIO2 n+ source p-well contact p n+ Drain p+ Cross-sectional view of the C3017 process ID vsVD, W/L = 20/4.0 ID vsVD, W/L = 20/4.0 5 -3 -2.5 VGS = 9.0V 4 Drain Current (mA) IDS Drain Current (mA) IDS VGS = 10V VGS = 8.0V 3 VGS = 7.0V VGS = 6.0V 2 VGS = 5.0V VGS = 4.0V 1 VGS = 3.0V VGS = -10V -2 VGS = -9.0V -1.5 VGS = -8.0V VGS = -7.0V -1 VGS = -6.0V VGS = -5.0V -.5 VGS = -4.0V VGS = -3.0V VGS = 2.0V 0 92 0 1 2 3 4 5 6 7 8 9 VGS = -2.0V 10 0 0 1 2 3 4 5 6 7 8 9 10 Drain Voltage (v) VDS Drain Voltage (v) VDS n-ch Transistor IV characteristics of a 20/4.0 device p-ch Transistor IV characteristics of a 20/4.0 device C3017-4-98