APW7074 Synchronous Buck PWM Controller Features General Description • • • • • • • • • • The APW7074 is a voltage mode synchronous PWM controller with fixed 300kHz switching frequency, which driv- Single 12V Power Supply Required 0.8V Reference with 1% Accuracy ers dual N-channel MOSFETs. The device integrates the controling, monitoring, and protecting functions into a Shutdown and Soft-Start Function single package, which provides a controlled power output with under-voltage and over-current protections. 300kHz Fixed Switching Frequency Voltage Mode PWM Control Design The APW7074 provides excellent regulation for output load variation. The internal 0.8V temperature-com- Up to 100% Duty Cycle Under-Voltage Protection Over-Current Protection pensated reference voltage is designed for the requirements of low output voltage applications. SOP-14 Package The APW7074 has excellent protection functions: POR, Lead Free and Green Devices Available OCP, and UVP. The Power-On-Reset (POR) circuit can monitor the VCC, EN, and OCSET voltage to make sure (RoHS Compliant) the supply voltage exceeds their threshold voltage while the controller is running. The Over-Current Pro- Applications tection (OCP) monitors the output current by using the voltage drop across the upper and lower MOSFET’s RDS • (ON) . When the output current reaches the trip point, the controller will run the soft-start function until the fault Graphic Cards events are removed. The Under-Voltage Protection (UVP) monitors the voltage at FB pin (VFB) for short-circuit protection when the VFB is less 50% VREF, the controller will shutdown the IC directly. Pin Configuration NC 1 14 V CC OCSET 2 13 PV CC SS 3 12 LGA TE COMP 4 11 PGND FB 5 10 BOOT EN 6 9 UGA TE GND 7 8 PHASE SOP-14 TOP V IEW ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 1 www.anpec.com.tw APW7074 Ordering and Marking Information Package Code K : SOP-14 Operating Ambient Temperature Range E : -20 to 70° C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7074 Assembly Material Handling Code Temperature Range Package Code APW7074 K : APW7074 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC, PVCC BOOT UGATE LGATE PHASE OCSET FB, COMP PGND TJ Parameter Rating Unit VCC, PVCC to GND -0.3 to +16 V BOOT to PHASE -0.3 to +16 V UGATE to PHASE <400ns pulse width >400ns pulse width -5 to BOOT+5 -0.3 to BOOT +0.3 V LGATE to PGND <400ns pulse width >400ns pulse width -5 to PVCC+5 -0.3 to BOOT +0.3 V PHASE to GND <400ns pulse width >400ns pulse width -10 to +30 -0.3 to 16 V OCSET to GND VCC+0.3 V FB, COMP to GND -0.3 to 7 V PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to +150 °C -65 ~ 150 °C 260 °C TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 2 www.anpec.com.tw APW7074 Recommended Operating Conditions Symbol Parameter VCC, PVCC IC Supply Voltage VIN Converter Input Voltage Rating Unit 10.8 to 13.2 V 2.2 to 13.2 V VOUT Converter Output Voltage 0.8 to 5 V IOUT Converter Output Current 0 to 25 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7074 Min. Typ. Max. Unit INPUT SUPPLY CURRENT ICC VCC Supply Current (Shutdown Mode) UGATE, LGATE and EN = GND - 0.8 1.6 mA VCC Supply Current UGATE and LGATE Open - 5 10 mA Rising VCC Threshold 9 9.5 10.0 V Falling VCC Threshold 7.5 8 8.5 V Rising VOCSET Threshold - 1.3 - V VOCSET Hysteresis Voltage - 0.1 - V Rising EN threshold Voltage - 1.3 - V EN Hysteresis Voltage - 0.1 - V 255 300 345 kHz - 1.6 - V 0 - 100 % Reference Voltage - 0.80 - V Reference Voltage Tolerance -1 - +1 % POWER-ON-RESET OSCILLATOR FOSC Oscillator Frequency VOSC Ramp Amplitude Duty Duty Cycle Range (nominal 1.35V to 2.95V) (Note2) REFERENCE VREF Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 3 www.anpec.com.tw APW7074 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. APW7074 Symbol Parameter Test Conditions Unit Min. Typ. Max. RL = 10k, CL = 10pF (Note2) - 88 - dB RL = 10k, CL = 10pF (Note2) - 15 - MHz Slew Rate RL = 10k, CL = 10pF (Note2) - 6 - V/µs FB Input Current VFB = 0.8V - 0.1 1 µA PWM ERROR AMPLIFIER Gain Open Loop Gain GBWP Open Loop Bandwidth SR VCOPM COMP High Voltage - 5.5 - V VCOPM COMP Low Voltage - 0 - V ICOMP COMP Source Current VCOMP = 2V - 5 - mA ICOMP COMP Sink Current VCOMP = 2V - 5 - mA BOOT = 12V, VUGATE -VPHASE = 2V - 2.6 - A GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current BOOT = 12V, VUGATE -VPHASE = 2V - 1.05 - A ILGATE Lower Gate Source Current PVCC = 12V, VLGATE = 2V - 4.9 - A ILGATE Lower Gate Sink Current PVCC = 12V, VLGATE = 2V - 1.4 - A RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A - 2 3 Ω RUGATE Upper Gate Sink Impedance BOOT = 12V, IUGATE = 0.1A - 1.6 2.4 Ω RLGATE Lower Gate Source Impedance PVCC = 12V, ILGATE = 0.1A - 1.3 1.95 Ω RLGATE Lower Gate Sink Impedance PVCC = 12V, ILGATE = 0.1A - 1.25 1.88 Ω - 20 - nS TD Dead Time PROTECTION UVFB FB Under Voltage Level Percent of VREF 45 50 55 % IOCSET OCSET Source Current (Hi-Side) VOCSET = 11.5V 170 200 250 µA VOCP OCP Voltage (Low-Side) 270 290 310 mV 8 10 12 µA SOFT-START ISS Soft-Start Charge Current Note 2:Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 4 www.anpec.com.tw APW7074 Typical Application Circuit 1µF 12V VIN 1N4148 1nF PVCC VCC OCSET ON EN 2.37K BOOT OFF 0.1µF SS UGATE 22nF 1µH 1µF 470µFx2 470µF APM2509 2.2µH VOUT PHASE 1.5nF APM2506 COMP LGATE FB 33nF SCD24 1000µFx2 7.5R PGND GND 8.2nF 2.7K 1K 2K 18R 68nF Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 5 www.anpec.com.tw APW7074 Block Diagram OCSET VCC PowerOnReset EN GND BOOT IOCSET 200µA UGATE O.C.P Comparator VCC PHASE 0.29V ISS 10µA Soft-Start O.C.P Comparator SS U.V.P Comparator 50%VREF :2 PVCC PWM Comparator Gate Control Error Amp PGND VREF Oscillator FB LGATE Sawtooth Wave FOSC 300kHz COMP Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 6 www.anpec.com.tw APW7074 Function Pin Description VCC (Pin14) LGATE (Pin12) Power supply input pin. Connect a nominal 12V power supply to this pin. This pin also has a power-on- This pin is the gate driver for the lower MOSFET of PWM output. reset function, which monitors the input voltage. It is recommended that a decoupling capacitor (1 to 10µF) be SS (Pin3) Connect a capacitor to GND and a 10µA current source connected to GND for noise decoupling. charges this capacitor to set the soft-start time. PVCC (Pin13) OCSET (Pin2) This pin provides a supply voltage for the lower gate drive. Connect this pin to VCC pin in normal use. This pin serves two functions: a shutdown control and BOOT (Pin10) the setting of over current limit threshold. Pulling this pin below 1.3V will shutdown the controller, forcing the UGATE This pin provides the bootstrap voltage to the upper gate and LGATE signals to be low. driver in order to drive the N-channel MOSFET. A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over PHASE (Pin8) current limit. An internal 200µA current source will flow through this resistor, creating a voltage drop, which will This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET be compared with the voltage across the high side MOSFET. The threshold of the over current limit is there- for over-current protection. fore given by: GND (Pin7) IPEAK = This pin is the signal ground pin. Connect the GND pin to a good ground plane. IOCSET (200uA ) × R OCSET R DS(ON) PGND (Pin11) EN (Pin6) This pin is the power ground pin for the lower gate driver. Pull this pin above 1.3V to enable the device and below 1.2V to disable the device. In shutdown, the SS is dis- It should be tied to the GND pin on the board. charged and the UGATE and LGATE pins are held low. Note that don’t leave this pin open. COMP (Pin4) This pin is the output of PWM error amplifier. It is used to set the compensation components. FB (Pin5) This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection. If the FB voltage is under 50% of the reference voltage, the device will be shut down. UGATE (Pin9) This pin is the gate driver for the upper MOSFET of PWM output. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 7 www.anpec.com.tw APW7074 Typical Operating Characteristics Power Off Power On VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: Vcc (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 2ms/div CH1: Vcc (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 10ms/div EN (EN=VCC) Shutdown (EN=GND) VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div 8 www.anpec.com.tw APW7074 Typical Operating Characteristics (Cont.) UGATE Rising UGATE Falling VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div Load Transient Response Under Voltage Protection VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH1 CH2 CH3 CH2 CH4 CH1: SS (5V/div) CH2: Io (5A/div) CH3: Vo (1V/div) CH4: Ug (10V/div) Time: 50us/div CH1: Vo (500mV/div, AC) CH2:Io (5A/div) Time: 200us/div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 9 www.anpec.com.tw APW7074 Typical Operating Characteristics (Cont.) Short Test Over Current Protection CH1 Vcc=12V, Vin=12V Vo=1.5V, L=1uH CH1 Vcc=12V, Vin=12V,Vo=1.5V, L=1uH Rocset=1KΩ , Rds(on)=8mΩ CH2 CH2 CH3 CH3 CH4 CH4 CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4:Ug (20V/div) Time: 10ms/div CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4:Ug (20V/div) Time: 10ms/div Reference Voltage vs. Junction Temperature 310 0.804 305 0.802 300 Reference Voltage(V) Switching Frequency(kHz) Switching Frequency vs. Junction Temperature 295 290 285 0.798 0.796 0.794 280 275 -40 0.8 -20 0 20 40 60 80 0.792 -40 100 120 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 -20 0 20 40 60 80 100 120 Junction Temperature (°C) 10 www.anpec.com.tw APW7074 Typical Operating Characteristics (Cont.) UGATE Sink Current vs. UGATE Voltage UGATE Source Current vs. UGATE Voltage 3.5 3 VBOOT=12V VBOOT=12V 2.5 2.5 UGATE Sink Current (A) UGATE Source Current (A) 3 2 1.5 1 0.5 0 2 1.5 1 0.5 0 0 2 4 6 8 10 0 12 2 UGATE Voltage (V) 6 8 10 12 UGATE Voltage (V) LGATE Sink Current vs. LGATE Voltage LGATE Source Current vs. LGATE Voltage 6 3.5 PVCC=12V PVCC=12V 3 LGATE Sink Current (A) 5 LGATE Source Current (A) 4 4 3 2 1 2.5 2 1.5 1 0.5 0 0 0 2 4 6 8 10 0 12 LGATE Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 2 4 6 8 10 12 LGATE Voltage (V) 11 www.anpec.com.tw APW7074 Function Description Power-On-Reset (POR) Voltage The Power-On-Reset (POR) function of APW7074 continually monitors the input supply voltage (VCC), the enable (EN) pin, and OCSET pin. The supply voltage VSS (VCC) must exceed its rising POR threshold voltage. The voltage at OCSET pin is equal to VIN minus a fixed voltage 4.2V drop (Vocset = VIN- VROCSET). EN pin can be pulled high with connecting a resistor to VCC. The POR function initiates soft-start operation after VCC, EN, and OCSET voltages exceed their POR thresholds. For operation with a single VOUT 1.8V +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (EN pin low). With both input supplies above t0 t1 their POR thresholds, the device initiates a soft-start Time t2 Figure 1. Soft-Start Internal interval. Over-Current Protection (monitor upper MOSFET) Soft-Start/EN The APW7074 provides two manners to protect the con- The SS/EN pins control the soft-start and enable or disable the controller. Connect a soft-start capacitor from SS verter from abnormal output load; one monitors the voltage across the upper MOSFET and uses the OCSET pin to GND to set the soft-start interval. Figure1. shows the soft-start interval. When VCC reaches its Power-On-Re- pin to set the over-current trip point, the other monitors the voltage across the lower MOSFET by comparing with set threshold (9.5V), internal 10µA current source starts to charge the capacitor. When the SS reaches the enabled an internal reference voltage (0.29V). threshold about 1.8V, the internal 0.8V reference starts to rise and follows the SS; the error amplifier output A resistor (ROCSET) connected between OCSET pin and the drain of the upper MOSFET will determine the over (COMP) suddenly raises to 1.35V, which is the valley of the triangle wave of the oscillator, leads the VOUT to start current limit. An internal 200µA current source will flow through this resistor, creating a voltage drop, which will up. Until the SS reaches about 4.2V, the internal reference completes the soft-start interval and reaches to 0. be compared with the voltage across the upper MOSFET. When the voltage across the upper MOSFET exceeds the 8V; then VOUT is in regulation. The SS still rises to 5.5V and then stops. voltage drop across the ROCSET, an over-current will be detected. The threshold of the over current limit is there- TSoft − Start = t 2 − t 1 = fore given by: C SS ⋅ 2 .4 V ISS ILIMIT = Where: CSS = external Soft-Start capacitor IOCSET × R OCSET R DS (ON ) The over-current never occurs in the normal operating load range; the variation of all parameters in the above ISS = Soft-Start current=10µA equation should be determined. - The MOSFET’ RDS(ON) is varied by the temperature and the gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’s datasheet. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 12 www.anpec.com.tw APW7074 Function Description (Cont.) Over-Current Protection (Cont.) - The minimum IOCSET (170µA) and minimum ROCSET should be used in the above equation. - Note that the ILIMIT is the current flow through the upper MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. An over current condition will shut down the device and discharge the CSS with a 10µA sink current and then initiate the soft-start sequence. If the over current condition is not removed during the soft-start interval, the device will be shut down while the over current is detected and the SS still rises to 4V to complete its cycle. The soft-start function will be cycled until the over-current condition is removed. Both over-current protections have the same behavior while an over current condition is detected. Over-Current Protection (monitor lower MOSFET) The other over-current protection monitors the output current by using the voltage drop across the lower MOSFET’s RDS(ON) and this voltage drop will be compared with the internal 0.29V reference voltage. If the voltage drop across the lower MOSFET’s RDS(ON) is larger than 0.29V, an overcurrent condition is detected. The threshold of the over current limit is given by: ILIMIT = 0.29V R DS(ON) For the over-current is never occurred in the normal operating load range; the parameters RDS(ON) and ILIMIT in the above equation also have the same notices as the previous section. Under Voltage Protection The FB pin is monitored during converter operation by their own Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0. 8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter’s output is latched to float. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 13 www.anpec.com.tw APW7074 Application Information Output Voltage Selection Output Capacitor Selection The output voltage can be programmed with a resistive divider. The use of 1% or better resistors for the resistive Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, select- divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. ing high performance low ESR capacitors is intended for switching regulator applications. In some applications, The output voltage is determined by: multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel R VOUT = 0.8 × 1 + OUT R GND for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be Where ROUT is the resistor connected from VOUT to FB and considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, RGND is the resistor connected from FB to GND. consult the capacitors manufacturer. Output Inductor Selection Input Capacitor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher in- The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times ductor value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/ and the ripple voltage can be approximated by: IRIPPLE = VIN − VOUT VOUT × FS × L VIN 2, where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult ∆VOUT = IRIPPLE × ESR the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can connect between where FS is the switching frequency of the regulator. Although the increase of the inductor value and frequency reduces the ripple current and voltage, there is a tradeoff the drain of upper MOSFET and the source of lower MOSFET. between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the R DS(ON), reverse transfer capacitance (CRSS) Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switch- and maximum output current requirement. There are two components of loss in the MOSFETs: conduction ing loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the fol- maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of lowing equations: 2 PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of 2 PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) carrying the required peak current without going into saturation. In some types of inductors, especially those Where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency with ferrite core, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple tSW is the switching interval D is the duty cycle voltage. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 14 www.anpec.com.tw APW7074 Application Information (Cont.) MOSFET Selection (Cont.) F LC Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW, is the function of the reverse trans- -40dB/dec GAIN (dB) fer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. F ESR -20dB/dec PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes to -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT Frequency(Hz) Figure 3. The LC Filter GAIN and Frequency should be added. The compensation network is shown in Fig. 5. The output LC filter consists of the output induc- The PWM modulator is shown in Figure 4. The input is tor and output capacitors. The transfer function of the LC filter is given by: the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modu- GAIN lator is given by: 1 + s × ESR × C OUT = 2 s × L × C OUT + s × ESR × C OUT + 1 LC GAIN PWM = VIN ∆ V OSC V IN The poles and zero of this transfer functions are: FLC = 1 OSC 2 × π × L × C OUT FESR = ΔV OSC 1 2 × π × ESR × C OUT Driver PWM Comparator The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. PHASE L PHASE Output of Error Amplifier Driver Figure 4. The PWM Modulator OUTPUT The compensation network is shown in Figure 5. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. C OUT The transfer function of error amplifier is given by: ESR 1 1 // R2 + sC1 sC2 GAIN AMP = 1 R1// R3 + sC3 1 1 s + × s + ( R2 × C2 R1 + R3 ) × C3 R1 + R3 = × C1 + C2 1 R1 × R3 × C1 s s + × s + R2 × C1 × C2 R3 × C3 V = COMP V OUT Figure 2. The Output LC Filter Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 15 www.anpec.com.tw APW7074 Application Information (Cont.) PWM Compensation (Cont.) C2 = The poles and zeros of the transfer function are: 1 F Z1 = 2 × π × R2 × C2 F Z2 FP1 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR 1 = 2 × π × (R1 + R3 ) × C3 Calculate the C1 by the equation: C1 = 1 = C1 × C2 2 × π × R2 × C1 + C2 FP2 = LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the C1 C3 C2 2 × π × R2 × C2 × FESR − 1 5.Set the second pole FP2 at the half of the switching frequency and also set the second zero F Z2 at the output 1 2 × π × R3 × C3 R3 1 2 × π × R2 × FLC × 0.75 R2 compensation gain at FP2 with the capabilities of the error amplifier. C2 V OUT FP2 = 0.5 X FS R1 FB V COMP FZ2 = FLC V REF Combine the two equations will get the following com- Figure 5. Compensation Network ponent calculations: The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS Figure 6. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. F Z1 F Z2 F P1 F P2 1.Choose a value for R1, usually between 1K and 5K. GAIN (dB) 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: R2 = ∆ VOSC FO × × R1 VIN FLC 20log (V IN /Δ V OSC ) Compensation Gain F LC F ESR 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. Converter Gain PWM & Filter Gain FZ1 = 0.75 X FLC Frequency(Hz) Figure 6. Converter Gain and Frequency Calculate the C2 by the equation: Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 20log (R2/R1) 16 www.anpec.com.tw APW7074 Application Information (Cont.) Layout Consideration - The input capacitor should be near the drain of the In any high switching frequency converter, a correct lay- upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close out is important to ensure proper operation of the regulator. With power devices switching at 300kHz,the to the output capacitor GND and the lower MOSFET GND. resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit - The drain of the MOSFETs (VIN and Phase nodes) elements. As an example, consider the turn-off transition should be a large plane for heat sinking. of the PWM MOSFET. Before turn-off, the MOSFET is carrying a full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower APW7074 MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the VCC PVCC switching interval. In general, using short and wide printed circuit traces should minimize interconnecting im- BOOT pedances and the magnitude of voltage spike. Also, signal and power grounds are to be kept separate till com- UGATE V IN L O A D PHASE bined using ground plane construction or single point grounding. Figure 7. illustrates the layout, with bold lines LGATE V OUT indicating high current paths; these traces must be short and wide. Components along the bold lines should be Figure 7.Layout Guidelines placed closely together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 17 www.anpec.com.tw APW7074 Package Information SOP–14 D E E1 SEE VIEW A h X 45 ° e c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 b L VIEW A S Y M B O L SOP-14 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° 8° Note: 1. Follow JEDEC MS-012 AB. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 18 www.anpec.com.tw APW7074 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. T1 C d D E1 F 16.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 -0.00 -0.20 P0 P1 P2 D0 D1 4.0±0.10 8.0±0.10 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. SOP-14 W T A0 B0 K0 0.6+0.00 6.40±0.20 9.00±0.20 2.10±0.20 -0.40 (mm) Cover Tape Dimensions Package Type Unit Quantity SOP-14 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 19 www.anpec.com.tw APW7074 Taping Direction Information SOP-14 USER DIRECTION OF FEED Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat t 25°C to Peak 25 Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 20 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APW7074 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2008 21 www.anpec.com.tw