LTC2657 Octal I2C 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference DESCRIPTION FEATURES n n n n n n n n n n The LTC®2657 is a family of octal I2C 16-/12-Bit Rail-toRail DACs with Integrated 10ppm/°C Max Reference. The DACs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. The LTC2657-L has a full-scale output of 2.5V with the integrated reference and operates from a single 2.7V to 5.5V supply. The LTC2657-H has a full-scale output of 4.096V with the integrated reference and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. Integrated Reference 10ppm/°C Max Maximum INL Error: ±4LSB Guaranteed Monotonic Over Temperature Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2657-L) Integrated Reference Buffers Ultralow Crosstalk between DACs(0.8nV•s) Power-On-Reset to Zero-Scale/Mid-Scale 400kHz I2C Interface Tiny 20-Lead 4mm × 5mm QFN and 20-Lead Thermally enhanced TSSOP packages The parts use a 2-wire I2C compatible serial interface. The LTC2657 operates in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum clock rate of 400kHz). The LTC2657 incorporates a power-on reset circuit that is controlled by the PORSEL pin. If PORSEL is tied to GND the DACs reset to zero-scale at power-up. If PORSEL is tied to VCC , the DACs reset to mid-scale at power-up. APPLICATIONS n n n n n Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment Automotive L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 6891433 and patent pending. BLOCK DIAGRAM REFCOMP INTERNAL REFERENCE REF REFIN/OUT INL vs Code (LTC2657-16) GND REGISTER DAC A REGISTER VOUTA REGISTER REFLO REGISTER VCC 4 DAC H VOUTH 3 DAC G VOUTG INL (LSB) REGISTER REGISTER DAC B REGISTER VOUTB REGISTER 2 1 0 REGISTER REGISTER DAC C REGISTER VOUTC REGISTER –1 DAC F VOUTF DAC A DAC B DAC C DAC D –2 CA2 LDAC DAC E POWER-ON RESET CA0 CA1 REGISTER REGISTER DAC D REGISTER VOUTD REGISTER –3 VOUTE PORSEL –4 128 16384 32768 DAC E DAC F DAC G DAC H 49152 65535 CODE 2657 TA01 32-BIT SHIFT REGISTER 2-WIRE INTERFACE SDA SCL 2657 BD 2657f 1 LTC2657 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V SCL, SDA, LDAC, REFLO.............................. –0.3V to 6V VOUTA to VOUTH ................. –0.3V to Min(VCC + 0.3V, 6V) REFIN/OUT, REFCOMP ...... –0.3V to Min(VCC + 0.3V, 6V) PORSEL, CA0, CA1, CA2 ... –0.3V to Min(VCC + 0.3V, 6V) Operating Temperature Range LTC2657C ................................................ 0°C to 70°C LTC2657I..............................................–40°C to 85°C Maximum Junction Temperature........................... 150°C Storage Temperature Range.......................–65 to 150°C Lead Temperature (Soldering FE-Package, 10 sec) .. 300°C PIN CONFIGURATION VCC GND VOUTA REFLO TOP VIEW TOP VIEW REFLO 1 20 GND VOUTA 2 19 VCC VOUTB 3 18 VOUTH VOUTB 1 16 VOUTH REFCOMP 4 17 VOUTG REFCOMP 2 15 VOUTG VOUTC 5 16 VOUTF VOUTC 3 VOUTD 6 15 VOUTE VOUTD 4 8 13 CA0 CA2 9 12 CA1 SCL 10 11 SDA FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 11 CA0 7 8 9 10 CA1 LDAC 12 PORSEL LDAC 6 SDA 14 PORSEL 13 VOUTE REFIN/OUT 5 SCL 7 14 VOUTF 21 CA2 REFIN/OUT 21 20 19 18 17 UFD PACKAGE 20-LEAD (4mm s 5mm) PLASTIC QFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 2657f 2 LTC2657 PRODUCT SELECTOR GUIDE LTC2657 B C UFD -L 16 #TR PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = Tape and Reel RESOLUTION 16 = 16-Bit 12 = 12-Bit FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UFD = 20-Lead (4mm × 5mm) Plastic QFN FE = 20-Lead Thermally Enhanced TSSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) ELECTRICAL GRADE (OPTIONAL) B = ±4LSB INL (MAX) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2657f 3 LTC2657 ORDER INFORMATION TEMPERATURE RANGE MAXIMUM INL LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION LTC2657BCFE-L16#PBF LTC2657BCFE-L16#TRPBF LTC2657FE-L16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±4 LTC2657BIFE-L16#PBF LTC2657BIFE-L16#TRPBF LTC2657FE-L16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±4 LTC2657BCUFD-L16#PBF LTC2657BCUFD-L16#TRPBF 57L16 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±4 LTC2657BIUFD-L16#PBF LTC2657BIUFD-L16#TRPBF 57L16 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±4 LTC2657BCFE-H16#PBF LTC2657BCFE-H16#TRPBF LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±4 LTC2657BIFE-H16#PBF LTC2657BIFE-H16#TRPBF LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±4 LTC2657BCUFD-H16#PBF LTC2657BCUFD-H16#TRPBF 57H16 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±4 LTC2657BIUFD-H16#PBF LTC2657BIUFD-H16#TRPBF 57H16 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±4 LTC2657CFE-L12#PBF LTC2657CFE-L12#TRPBF LTC2657FE-L12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±1 LTC2657IFE-L12#PBF LTC2657IFE-L12#TRPBF LTC2657FE-L12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±1 LTC2657CUFD-L12#PBF LTC2657CUFD-L12#TRPBF 57L12 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±1 LTC2657IUFD-L12#PBF LTC2657IUFD-L12#TRPBF 57L12 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±1 LTC2657CFE-H12#PBF LTC2657CFE-H12#TRPBF LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±1 LTC2657IFE-H12#PBF LTC2657IFE-H12#TRPBF LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±1 LTC2657CUFD-H12#PBF LTC2657CUFD-H12#TRPBF 57H12 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±1 LTC2657IUFD-H12#PBF LTC2657IUFD-H12#TRPBF 57H12 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±1 Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V) SYMBOL PARAMETER LTC2657-12 MIN TYP MAX CONDITIONS LTC2657B-16 MIN TYP MAX UNITS DC Performance l 12 16 Bits Monotonicity (Note 3) l 12 16 Bits Differential Nonlinearity (Note 3) l ±0.1 ±0.5 Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l ±0.5 ±1 Load Regulation VCC = 5V ±10%, Internal Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA l 0.04 0.125 VCC = 3V ±10%, Internal Reference, Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA l 0.06 l l Resolution DNL INL ZSE Zero-Scale Error VOS Offset Error GE Gain Error (Note 4) VREF = 1.25V VOS Temperature Coefficient Gain Temperature Coefficient ±1 LSB ±2 ±4 LSB 0.6 2 LSB/mA 0.25 1 4 LSB/mA 1 3 1 3 mV ±1 ±2 ±1 ±2 mV 2 l ±0.3 ±0.02 ±0.1 1 2 ±0.02 ±0.1 1 μV/°C %FSR ppm/°C 2657f 4 LTC2657 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOUT DAC Output Span Internal Reference External Reference = VEXTREF PSR Power Supply Rejection VCC ±10% ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA l 0.04 0.15 Ω VCC = 3V ±10%, Internal Reference, Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA l 0.04 0.15 Ω ISC 0 to 2.5 0 to 2 • VEXTREF V V –80 dB DC Crosstalk (Note 5) Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) ±1.5 ±2 ±1 μV μV/mA μV Short-Circuit Output Current (Note 6) VCC = 5.5V, VEXTREF = 2.8V Code: Zero-Scale, Forcing Output to VCC Code: Full-Scale, Forcing Output to GND l l 20 20 65 65 mA mA VCC = 2.7V, VEXTREF = 1.4V Code: Zero-Scale, Forcing Output to VCC Code: Full-Scale, Forcing Output to GND l l 10 10 40 40 mA mA Reference Reference Output Voltage 1.248 Reference Temperature Coefficient (Note 7) C-Grade Only Reference Line Regulation VCC ±10% Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND l REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100μA Sourcing External Reference Mode (Note 14) ±2 ±10 200 40 0.5 0.001 (Note 9) ppm/°C mA μA mV/mA 30 l V dB 5 l Reference Input Current Reference Input Capacitance 1.252 –80 Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1μF at f = 1kHz Reference Input Range 1.25 nV/√Hz VCC/2 V 1 μA 40 pF Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 8) VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off VCC = 3V, Internal Reference On VCC = 3V, Internal Reference Off l l l l ISD Supply Current in Shutdown Mode (Note 8) VCC = 5V 2.7 5.5 V 4.25 3.7 3.8 3.2 mA mA mA mA l 3 μA 0.3VCC V 3.1 2.7 3 2.6 Digital I/O VIL Low Level Input Voltage (SDA and SCL) l VIH High Level Input Voltage (SDA and SCL) l VIL(LDAC) Low Level Input Voltage (LDAC) VIH(LDAC) High Level Input Voltage (LDAC) 0.7VCC V VCC = 4.5V to 5.5V l 0.8 V VCC = 2.7V to 4.5V l 0.6 V VCC = 3.6V to 5.5V l 2.4 V VCC = 2.7V to 3.6V l 2 V 2657f 5 LTC2657 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIL(CA) Low Level Input Voltage (CA0 and CA2) See Test Circuit 1 l VIH(CA) High Level Input Voltage (CA0 and CA2) See Test Circuit 1 l RINH Resistance from CAn (n = 0,1, 2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n = 0,1, 2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n = 0,1, 2) to VCC or GND to Set CAn=FLOAT See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 13) l 20+0.1CB 250 ns l 50 ns 0.15VCC V 0.85VCC V MΩ tOF Output Fall Time tSP Pulse Width of Spikes Suppressed by Input Filter IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l 1 μA CIN I/O Pin Capacitance (Note 9) l 10 pF CB Capacitance Load for Each Bus Line l 400 pF CCAn External Capacitive Load on Address Pins CA0, CA1 and CA2 l 10 pF 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V) SYMBOL PARAMETER LTC2657-12 MIN TYP MAX CONDITIONS LTC2657B-16 MIN TYP MAX UNITS DC Performance l 12 16 Bits Monotonicity (Note 3) l 12 16 Bits Differential Nonlinearity (Note 3) l ±0.1 ±0.5 Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l ±0.5 ±1 Load Regulation VCC = 5V ±10%, Internal Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA l 0.04 0.125 Resolution DNL INL ZSE Zero-Scale Error VOS Offset Error GE Gain Error (Note 4) VREF = 2.048V ±1 LSB ±2 ±4 LSB 0.6 2 LSB/mA l 1 3 1 3 mV l ±1 ±2 ±1 ±2 mV VOS Temperature Coefficient Gain Temperature Coefficient ±0.3 2 l ±0.02 ±0.1 1 2 ±0.02 ±0.1 1 μV/°C %FSR ppm/°C 2657f 6 LTC2657 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V) SYMBOL PARAMETER VOUT DAC Output Span CONDITIONS Internal Reference External Reference = VEXTREF PSR Power Supply Rejection VCC ±10% ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, MidScale, –15mA ≤ IOUT ≤ 15mA DC Crosstalk Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) Short-Circuit Output Current (Note 4) VCC = 5.5V, VEXTREF = 2.8V Code: Zero-Scale, Forcing Output to VCC Code: Full-Scale, Forcing Output to GND ISC MIN TYP MAX 0 to 4.096 0 to 2 • VEXTREF V V –80 l 0.04 dB 0.15 ±1.5 ±2 ±1 l l 20 20 UNITS Ω μV μV/mA μV 65 65 mA mA Reference Reference Output Voltage 2.044 Reference Temperature Coefficient (Note 7) C-Grade Only Reference Line Regulation VCC ±10% Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100μA Sourcing Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1μF at f = 1kHz External Reference Mode (Note 14) ±10 l V ppm/°C dB 5 mA 200 μA 40 mV/mA 35 nV/√Hz 0.5 l 0.001 (Note 9) l 40 Reference Input Current Reference Input Capacitance 2.052 ±2 –80 l Reference Input Range 2.048 VCC/2 V 1 μA pF Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 8) VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off l l ISD Supply Current in Shutdown Mode (Note 8) VCC = 5V VIL VIH 4.5 5.5 V 4.25 3.7 mA mA l 3 μA Low Level Input Voltage (SDA and SCL) l 0.3VCC V High Level Input Voltage (SDA and SCL) l 3.3 3 Digital I/O VIL(LDAC) Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V l VIH(LDAC) High Level Input Voltage (LDAC) VCC = 4.5V to 5.5V l See Test Circuit 1 l VIL(CA) Low Level Input Voltage (CA0 to CA2) 0.7VCC V 0.8V 2.4 V V 0.15VCC V VIH(CA) High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l RINH Resistance from CAn (n = 0,1, 2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n = 0,1, 2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n = 0,1, 2) to VCC or GND to Set CAn = FLOAT See Test Circuit 2 l 2 VOL Low Level Ouput Voltage Sink Current = 3mA l 0 0.85VCC V MΩ 0.4 V 2657f 7 LTC2657 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V) SYMBOL PARAMETER CONDITIONS VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 13) MIN TYP MAX UNITS l 20+0.1CB 250 ns l 50 ns 1 μA tOF Output Fall Time tSP Pulse Width of Spikes Suppressed by Input Filter IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l CIN I/O Pin Capacitance (Note 9) l 10 pF CB Capacitance Load for Each Bus Line l 400 pF CCAn External Capacitive Load on Address Pins CA0, CA1 and CA2 l 10 pF 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657B-H16/LTC2657-H12/ LTC2657B-L16/LTC2657-L12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance tS Settling Time (Note 10) ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 3.9 9.1 μs μs Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 2.4 4.5 μs μs 1.8 V/μs Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse (Note 11) DAC-to-DAC Crosstalk (Note 12) 1000 At Mid-Scale Transition, L-Option nV•s At Mid-Scale Transition, H-Option 7 nV•s CREFCOMP = CREFIN/OUT = 0.22μF 0.8 nV•s Multiplying Bandwidth en 4 pF 150 kHz Output Voltage Noise Density At f = 1kHz At f = 10kHz 85 80 nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, Internal Reference (L-Options) 0.1Hz to 10Hz, Internal Reference (H-Options) 0.1Hz to 200kHz, Internal Reference (L-Options) 0.1Hz to 200kHz, Internal Reference (H-Options) 8 12 600 650 μVP-P μVP-P μVP-P μVP-P 2657f 8 LTC2657 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTC2657B-L16/LTC2657-L12/LTC2657B-H16/LTC2657-H12 (see Figure 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz VCC = 2.7V to 5.5V fSCL SCL Clock Frequency l 0 tHD(STA) Hold Time (Repeated) Start Condition l 0.6 μs tLOW Low Period of the SCL Clock Pin l 1.3 μs tHIGH High Period of the SCL Clock Pin l 0.6 μs tSU(STA) Set-Up Time for a Repeated Start Program l 0.6 μs tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 tr Rise Time of Both SDA and SCL Signals l tf Fall Time of Both SDA and SCL Signals 0.9 μs 20+0.1CB 300 ns l 20+0.1CB 300 ns ns tSU(STO) Set-Up Time for Stop Condition l 0.6 μs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 μs t1 Falling edge of the 9th Clock of the 3rd Input Byte to LDAC High or Low Transition l 400 ns t2 LDAC Low Pulse Width l 20 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is the lower end code for which no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is defined from code 128 to code 65535. For VREF = 2.5V and N = 12, kL = 8 and linearity is defined from code 8 to code 4,095. Note 4: Inferred from measurement at code 128 (LTC2657-16) or code 8 (LTC2657-12). Note 5: DC crosstalk is measured with VCC = 5V and using internal reference with the measured DAC at mid-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 8: Digital inputs at 0V or VCC. Note 9: Guaranteed by design and not production tested. Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND. Note 11: VCC = 5V (H-Options) or VCC = 3V (L-Options), internal reference mode. DAC is stepped ±1LSB between half-scale and half-scale –1. Load is 2k in parallel with 200pF to GND. Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output of one DAC due to a full-scale change at the output of another DAC. It is measured with VCC = 5V, using internal reference, with the measured DAC at mid-scale. Note 13: CB = capacitance of one bus line in pF. Note 14: Gain error specification may be degraded for reference input voltages less than 1V. See Gain Error vs Reference Input curve in the Typical Performance Characteristics section. 2657f 9 LTC2657 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) 4 LTC2657-L16, TA = 25°C unless otherwise noted. Differential Nonlinearity (DNL) 1 VCC = 3V INL vs Temperature 4 VCC = 3V 3 VCC = 3V 3 2 0.5 2 0 –1 –2 INL (LSB) DNL (LSB) INL (LSB) INL (POS) 1 0 0 INL (NEG) –1 –0.5 –2 –3 –4 128 1 –3 16384 32768 CODE 49152 65535 –1 128 16384 32768 CODE 65535 49152 2657 G01 2657 G03 REFIN/OUT Output Voltage vs Temperature 1.253 VCC = 3V VCC = 3V 1.252 0.5 VREFIN/OUT (V) DNL (POS) DNL (LSB) 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G02 DNL vs Temperature 1 –4 –50 –30 –10 0 DNL (NEG) –0.5 1.251 1.250 1.249 1.248 –1 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 1.247 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 3586 G35 2657 G05 Settling to ±1LSB Rising SCL 3V/DIV Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 9TH CLOCK OF 3RD DATA BYTE 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS VOUT 100μV/DIV 8.6μs SCL 3V/DIV VOUT 150μV/DIV 9TH CLOCK OF 3RD DATA BYTE 9μs 2μs/DIV 2μs/DIV 2657 G07 2657 G08 2657f 10 LTC2657 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) 4 LTC2657-H16, TA = 25°C unless otherwise noted. Differential Nonlinearity (DNL) 1 VCC = 5V INL vs Temperature 4 VCC = 5V 3 0.5 DNL (LSB) 1 0 –1 INL (LSB) 2 0 INL (POS) 1 0 –1 INL (NEG) –0.5 –2 –2 –3 –3 16384 32768 CODE 49152 65535 –1 128 16384 32768 CODE 49152 2657 G10 65535 1 –4 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G011 3586 G35 REFIN/OUT Output Voltage vs Temperature DNL vs Temperature 2.054 VCC = 5V VCC = 5V 2.052 VREFIN/OUT (V) 0.5 DNL (LSB) INL (LSB) 2 –4 128 VCC = 5V 3 DNL (POS) 0 DNL (NEG) 2.050 2.048 2.046 –0.5 2.044 –1 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2.042 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G14 2657 G13 Settling to ±1LSB Rising SCL 5V/DIV Settling to ±1LSB Falling 9TH CLOCK OF 3RD DATA BYTE 9.2μs VOUT 250μV/DIV 9.7μs VOUT 250μV/DIV 9TH CLOCK OF 3RD DATA BYTE 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS SCL 5V/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2μs/DIV 2μs/DIV 2657 G16 2657 G17 2657f 11 LTC2657 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL) 1 VCC = 5V VREF = 2.048V 0.5 Settling to ±1LSB VCC = 5V VREF = 2.048V 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 0.5 VOUT 500μV/DIV DNL(LSB) INL(LSB) LTC2657-12, TA = 25°C unless otherwise noted. 0 3.5μs 0 –0.5 –0.5 –1 SCL 3V/DIV –1 8 1024 2048 CODE 3072 8 4095 1024 2048 CODE 2657 G19 3072 4095 2μs/DIV 2657 G21 2657 G20 LTC2657 Load Regulation 5.0 0.20 6 4 VCC = 5V (LTC2657-H) VCC = 3V (LTC2657-L) 0.15 VCC = 5V (LTC2657-H) VCC = 3V (LTC2657-L) INTERNAL REF. CODE = MID-SCALE 0.10 INTERNAL REF. CODE = MID-SCALE ΔVOUT (V) 2 0 –2 5V SOURCING 4.5 4.0 3V SOURCING (LTC2657-L) 3.5 0.05 VOUT (V) 8 0 –0.05 3.0 2.5 2.0 1.5 –4 –0.10 –6 1.0 –0.15 –8 –10 –50 –40 –30 –20 –10 0 10 20 30 40 50 IOUT (mA) 0 –0.20 –50 –40 –30 –20 –10 0 10 20 30 40 50 IOUT (mA) 2657 G22 Offset Error vs Temperature Zero-Scale Error vs Temperature 0.75 ZERO-SCALE ERROR (mV) –0.25 –0.5 –1 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G25 3 4 5 6 IOUT (mA) 7 8 9 10 Gain Eror vs Temperature 48 32 2 1.5 1 16 0 –16 –32 0.5 –0.75 2 64 2.5 0 1 2657 G24 3 0.25 0 2657 G23 1 0.5 5V SINKING 3V SINKING (LTC2657-L) 0.5 GAIN ERROR (LSB) ΔVOUT (mV) Headroom at Rails vs Output Current Current Limiting 10 OFFSET ERROR (mV) 9TH CLOCK OF 3RD DATA BYTE –48 0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G26 –64 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G27 2657f 12 LTC2657 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs Reference Input VCC = 5.5V GAIN ERROR OF 8 CHANNELS 350 0 – 0.5 0 –16 –1 –32 –1.5 –48 2 1 1.5 REFERENCE VOLTAGE (V) 300 16 ICC (nA) 0.5 –2 0.5 50 2 1 1.5 REFERENCE VOLTAGE (V) 0 2.5 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 2657 G29 Supply Current vs Logic Voltage VCC = 5V (LTC2657-H) 200 100 –64 0.5 2.5 250 150 2657 G28 Supply Current vs Temperature SWEEP SCL, SDA BETWEEN OV AND VCC 5.5 2657 G30 ICC Shutdown vs Temperature 4.0 3 3.5 SUPPLY CURRENT (mA) 3.6 ICC (mA) 400 32 1 4.0 ICC Shutdown vs VCC 450 VCC = 5.5V 48 GAIN ERROR OF 8 CHANNELS GAIN ERROR (LSB) OFFSET ERROR (mV) 1.5 Gain Error vs Reference Input 64 3.2 2.8 LTC2657-H VCC = 5V, CODE = MID-SCALE INTERNAL REFERENCE 3.0 2.5 VCC = 3V (LTC2657-L) 2.4 2.0 0 1 2 3 LOGIC VOLTAGE (V) 4 5 LTC2657-L VCC = 3V, CODE = MID-SCALE INTERNAL REFERENCE 2.0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G31 ICC SHUTDOWN (μA) 2 LTC2657, TA = 25°C unless otherwise noted. 2 1 LTC2657-H VCC = 5V LTC2657-L VCC = 3V 0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2657 G32 Multiplying Bandwidth 2657 G33 Large Signal Response Mid-Scale Glitch Impulse 8 6 SCL 5V/DIV AMPLITUDE (dB) 4 9th CLOCK OF 3RD DATA BYTE 2 0 VOUT 0.5V/DIV –2 –4 –6 –8 VCC = 5V VREF(DC) = 2V –10 VREF(AC) = 0.2VPP CODE = FULL-SCALE –12 1k 100k 10k FREQUENCY (Hz) 1M LTC2657-H16, VCC = 5V 7nV-s TYP VCC = 5V VREF = 2.048V ZERO SCALE TO FULL SCALE VOUT 5mV/DIV LTC2657-L16, VCC = 3V 4nV-s TYP 2μs/DIV 2μs/DIV 2657 G35 2657 G36 2657 G34 2657f 13 LTC2657 TYPICAL PERFORMANCE CHARACTERISTICS DAC to DAC Crosstalk (Dynamic) LTC2657 Power On Reset to Zero-Scale Power On Reset to Mid-Scale LTC2657-H ONE DAC SWITCH FS-0 2V/DIV VCC 2V/DIV LTC2657-H16, VCC = 5V, 0.8nV • s TYP CREFCOMP = CREFOUT = 0.22μF VOUT 0.5mV/DIV VOUT 10mV/DIV VCC 2V/DIV ZERO-SCALE Noise Voltage Density vs Frequency NOISE VOLTAGE (nV/√Hz) 2657 G39 2657 G38 2657 G37 DAC Output 0.1Hz to 10Hz Voltage Noise VCC = 5V CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1μF 1000 250μs/DIV 200μs/DIV 2μs/DIV 1200 VOUT 1V/DIV Reference Output 0.1Hz to 10Hz Voltage Noise VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1μF VREFOUT = 1.25V CREFCOMP = CREFOUT = 0.1μF 800 5μV/DIV 600 2μV/DIV 400 LTC2657-H 200 LTC2657-L 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1 SEC/DIV 1 SEC/DIV 2657 G41 2657 G42 2657 G40 2657f 14 LTC2657 PIN FUNCTIONS (QFN/TSSOP) VOUTA to VOUTH (Pins 1, 3, 4, 13, 14, 15, 16, 20/Pins 2, 3, 5, 6, 15, 16, 17, 18): DAC Analog Voltage Outputs. The output range is 0V to 2 times the voltage at the REFIN/OUT pin. REFCOMP(Pin2/Pin4):InternalReferenceCompensation pin. For low noise and reference stability, tie 0.1μF cap to GND. Connect to GND to use an external reference at start-up. Command 0111b must still be issued to turn off internal reference. REFIN/OUT (Pin 5/Pin 7): This pin acts as the Internal Reference output in Internal Reference mode and acts as the Reference Input pin in External Reference mode. When acting as an output the nominal voltage at this pin is 1.25V for-L Options and 2.048V for-H Options. For low noise and reference stability tie a capacitor to GND. Capacitor value must be <= CREFCOMP. In External Reference mode, the allowable reference input voltage range is 0.5V to VCC/2. LDAC (Pin 6/Pin 8): Asynchronous DAC Update Pin. A falling edge on this input after four bytes have been written into the part immediately updates the DAC register with the contents of the input register. A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. Software powerdown is disabled when LDAC is low. CA2 (Pin 9/Pin 7): Chip Address Bit 2. Tie this pin to VCC , GND or leave it floating to select an I2C slave address for the part (See Table 2). This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 9/Pin 11 ): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This is a high impedance pin while data is shifted in. It is an open-drain N-channel output during acknowledgement. This pin requires a pull-up resistor or current source to VCC. CA1 (Pin 10/Pin 12): Chip Address Bit 1. Tie this pin to VCC , GND or leave it floating to select an I2C slave address for the part (See Table 2) CA0 (Pin 11/Pin 13): Chip Address Bit 0. Tie this pin to VCC , GND or leave it floating to select an I2C slave address for the part (See Table 2). PORSEL (Pin 12/Pin 14): Power-On-Reset Select pin. If tied to GND, the part resets to Zero-Scale at power up. If tied to VCC , the part resets to Mid-Scale at power up. VCC (Pin 17/Pin 19): Supply Voltage Input. For –L Options, 2.7V ≤ VCC ≤ 5.5V, and for –H Options, 4.5V ≤ VCC ≤ 5.5V. Bypass to ground with a 0.1μF capacitor placed as close to pin as possible. GND (Pin 18/Pin 20): Ground. REFLO (Pin 19/Pin 1): Reference Low pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin should be tied to GND. Exposed Pad (Pin 21/Pin 21): Ground. Must be Soldered to PCB Ground. SCL (Pin 8/Pin 10): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. 2657f 15 LTC2657 BLOCK DIAGRAM REFCOMP INTERNAL REFERENCE REF REFIN/OUT GND REGISTER REGISTER DAC B REGISTER REGISTER REGISTER VOUTC DAC C REGISTER REGISTER REGISTER VOUTD DAC D REGISTER REGISTER REGISTER REGISTER REGISTER VOUTB DAC H VOUTH REGISTER DAC A DAC G VOUTG REGISTER VOUTA DAC F VOUTF REGISTER VCC REFLO DAC E VOUTE POWER-ON RESET CA0 PORSEL 32-BIT SHIFT REGISTER CA1 SDA 2-WIRE INTERFACE CA2 SCL LDAC 2657 BD TEST CIRCUIT Test Circuit 1 Test Circuit 2 VDD 1007 CAn VIH(CAn)/VIL(CAn) RINH/RINL/RINF CAn 2606 TC GND 2657f 16 LTC2657 TIMING DIAGRAM SDA tLOW tf tf tSU(DAT) tr tHD(STA) tSP tr tBUF SCL S tHD(STA) tHD(DAT) tHIGH tSU(STA) tSU(STO) Sr P S 2657 F01 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS 9TH CLOCK OF 3RD DATA BYTE SCL t1 LDAC 2657 F01b Figure 1 2657f 17 LTC2657 OPERATION The LTC2657 is a family of octal voltage output DACs in 20-lead 4mm × 5mm QFN and in 20-lead thermally enhanced TSSOP packages. Each DAC can operate railto-rail in external reference mode, or with its full-scale voltage set by an integrated reference. Four combinations of accuracy (16- and 12-bit), and full-scale voltage (2.5V or 4.096V) are available. The LTC2657 is controlled using a 2-wire I2C compatible interface. Power-On Reset The LTC2657-L/-H clear the output to zero-scale if the PORSEL pin is tied to GND when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2657 contains circuitry to reduce the power-on glitch. The analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. Alternatively, if PORSEL is tied to VCC , The LTC2657-L/-H set the output to mid-scale when power is first applied. Power Supply Sequencing and Start-Up For the LTC2657 family of parts, the internal reference is powered-up at start-up by default. If an external reference is to be used, the REFCOMP pin (Pin 4 –TSSOP, Pin 2 -QFN ) must be hardwired to GND. This configuration allows the use of an external reference at start-up and converts the REFIN/OUT pin to an input. However, the internal reference will still be ON and draw supply current. In order to use an external reference, command 0111b should be used to turn the Internal Reference OFF.(See Table1.) The voltage at REFIN/OUT (Pin 7 –TSSOP, Pin 5 -QFN) should be kept within the range –0.3V ≤ REFIN/OUT ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 19 –TSSOP, Pin 17 -QFN ) is in transition. Transfer Function The digital-to-analog transfer function is: ⎛k⎞ VOUT(IDEAL) = ⎜ ⎟ • 2 • ⎡⎣VREF − REFLO⎤⎦ + REFLO ⎝2N ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is the voltage at the REFIN/OUT Pin. The resulting DAC output span is 0V to 2 • VREF, as it is necessary to tie REFLO to GND. VREF is nominally 1.25V for LTC2657-L and 2.048V for LTC2657-H, in Internal Reference Mode. Table 1. Command and Address Codes C3 0 0 0 0 0 0 0 0 COMMAND* C2 C1 C0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) n Power Down n Power Down Chip (All DACs and Reference) Select Internal Reference (Power-Up Reference) Select External Reference (Power-Down Reference) No Operation DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs *Command and address codes not shown are reserved and should not be used. Serial Interface The LTC2657 communicates with a host using the standard 2-wire I2C interface. The Timing Diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of 2657f 18 LTC2657 OPERATION these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2657 is a receive-only (slave) device. The master can write to the LTC2657. The LTC2657 does not respond to a read command from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition (See Figure 1). A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2657 responds to a write by a master in this manner. The LTC2657 does not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC , GND or float. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 2. Table 2. Slave Address Map CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0 GND GND GND GND 0 0 1 0 0 0 0 GND FLOAT 0 0 1 0 0 0 1 GND GND VCC 0 0 1 0 0 1 0 GND FLOAT GND 0 0 1 0 0 1 1 GND FLOAT FLOAT 0 1 0 0 0 0 0 GND FLOAT VCC 0 1 0 0 0 0 1 GND VCC GND 0 1 0 0 0 1 0 GND VCC FLOAT 0 1 0 0 0 1 1 GND VCC VCC 0 1 1 0 0 0 0 FLOAT GND GND 0 1 1 0 0 0 1 FLOAT GND FLOAT 0 1 1 0 0 1 0 FLOAT GND FLOAT FLOAT VCC 0 1 1 0 0 1 1 GND 1 0 0 0 0 0 0 FLOAT FLOAT FLOAT 1 0 0 0 0 0 1 FLOAT FLOAT VCC 1 0 0 0 0 1 0 FLOAT VCC GND 1 0 0 0 0 1 1 FLOAT VCC FLOAT 1 0 1 0 0 0 0 FLOAT VCC VCC 1 0 1 0 0 0 1 VCC GND GND 1 0 1 0 0 1 0 VCC GND FLOAT 1 0 1 0 0 1 1 VCC GND VCC 1 1 0 0 0 0 0 VCC FLOAT GND 1 1 0 0 0 0 1 VCC FLOAT FLOAT 1 1 0 0 0 1 0 VCC FLOAT VCC 1 1 0 0 0 1 1 VCC VCC GND 1 1 1 0 0 0 0 VCC VCC FLOAT 1 1 1 0 0 0 1 VCC VCC VCC GLOBAL ADDRESS 1 1 1 0 0 1 0 1 1 1 0 0 1 1 In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2657 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit on-chip hardwired address and is not selectable by CA0, CA1 and CA2. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 2. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. 2657f 19 LTC2657 OPERATION Write Word Protocol combination with the appropriate DAC address, (n). The integrated reference is automatically powered down when external reference mode is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using “Power-Down Chip” command 0101b. For all powerdown commands the 16-bit data word is ignored, but still required in order to complete a full communication cycle. The master initiates communication with the LTC2657 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2657 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of write data. The LTC2657 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2657 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2657 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The first byte of the input word consists of the 4-bit command followed by 4-bit address. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16- or 12-bit input code, MSB to LSB, followed by 0 or 4 don’t care bits (LTC265716 and LTC2657-12, respectively). A typical LTC2657 write transaction is shown in Figure 2. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Normal operation resumes by executing any command which includes a DAC update, in software as shown in Table 1 or using the asynchronous LDAC pin. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay time is 12μs. If on the other hand, all eight DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power up delay time is 14μs. The power up of the integrated reference depends on the command that powered it down. If the reference is powered down using the “Select External Reference” command (0111b), then it can only be powered back up by sending “Select Internal Reference” command (0110b). However if the reference was powered down by sending “Power Down Chip” command (0101b), then in addition to “Select Internal Reference” command (0110b), any command that powers up the DACs will also power up the integrated reference. Power-Down Mode Reference Modes For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. Input- and DAC-register contents are not disturbed during power-down. For applications where an accurate external reference is not available, the LTC2657 has a user-selectable, integrated reference. The LTC2657-L has a 1.25V reference that provides a full-scale output of 2.5V. The LTC2657-H has a 2.048V reference that provides a full-scale output of 4.096V. Both references exhibit a typical temperature drift of 2ppm/°C. Internal Reference mode can be selected by using command 0110b, and is the power-on default. A buffer is needed if the internal reference is required to drive external circuitry. For reference stability and low noise, it is recommended that a 0.1μF capacitor be tied between REFCOMP and GND. In this configuration, the Any channel or combination of channels can be put into power-down mode by using command 0100b in 2657f 20 LTC2657 OPERATION internal reference can drive up to 0.1μF capacitive load without any stability problems. In order to ensure stable operation, the capacitive load on the REFIN/OUT pin should not exceed the capacitive load on the REFCOMP pin. The amplifiers are stable driving capacitive loads of up to 1000pF. The DAC can also operate in External Reference mode using command 0111b. In this mode, the REFIN/OUT pin acts as an input that sets the DAC’s reference voltage. The input is high impedance and does not load the external reference source. The acceptable voltage range at this pin is 0.5V ≤ REFIN/OUT ≤ VCC/2. The resulting full-scale output voltage is 2 • VREFIN/OUT. For using External Reference at Start-Up, see the Power Supply Sequencing and Start-Up Section. The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separate. Integrated Reference Buffers Each of the eight DACs in LTC2657 has its own integrated high performance reference buffer. The buffers have very high input impedance and do not load the reference voltage source. These buffers shield the Reference Voltage from glitches caused by DAC switching and thus minimize DAC-to-DAC Dynamic Crosstalk. See the curve DACto-DAC Crosstalk (Dynamic) in the Typical Performance Characteristics section. Voltage Outputs Each of the eight rail-to-rail amplifiers contained in LTC2657 has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.040Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30Ω • 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be con-nected to analog ground. The REFLO pin should be connected to system star ground. Resistance from the REFLO pin to system star ground should be as low as possible. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur in External Reference mode near full-scale when the REFIN/OUT pin is at VCC/2 . If VREFIN/OUT = VCC/2 and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREFIN/OUT ≤ (VCC – FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2657f 21 22 2 1 SCL VOUT SA5 SA6 SA5 SDA START SA6 3 SA4 4 SA3 SA3 5 SA2 SA2 6 SA1 SA1 SLAVE ADDRESS SA4 7 SA0 SA0 8 WR 1 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 A3 A3 6 A2 A2 COMMAND/ADDRESS BYTE 7 A1 A1 8 A0 A0 9 ACK 1 D15 2 D14 3 D13 4 D12 5 D11 MS DATA BYTE 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 3 D5 Figure 2. Typical LTC2657 Input Waveform –Programming DAC Output for Full-Scale 9 ACK C3 4 D4 5 D3 LS DATA BYTE 6 D2 7 D1 8 D0 9 ACK OPERATION ZERO-SCALE VOLTAGE 2657 F02 FULL-SCALE VOLTAGE STOP LTC2657 2657f LTC2657 OPERATION VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 2657 F03 OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 0V NEGATIVE OFFSET 65, 535 INPUT CODE (b) Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale PACKAGE DESCRIPTION FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CB 6.40 – 6.60* (.252 – .260) 3.86 (.152) 3.86 (.152) 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 2657f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2657 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 4.00 ± 0.10 (2 SIDES) 0.70 ±0.05 0.75 ± 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 4.50 ± 0.05 1.50 REF 3.10 ± 0.05 2.65 ± 0.05 5.00 ± 0.10 (2 SIDES) 3.65 ± 0.05 2.50 REF 3.65 ± 0.10 2.65 ± 0.10 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 4.10 ± 0.05 5.50 ± 0.05 (UFD20) QFN 0506 REV B 0.25 ± 0.05 0.200 REF R = 0.115 TYP 0.00 – 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE NOTE: MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 5. EXPOSED PAD SHALL BE SOLDER PLATED 2. DRAWING NOT TO SCALE 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION 3. ALL DIMENSIONS ARE IN MILLIMETERS ON THE TOP AND BOTTOM OF PACKAGE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1821 Single 16-Bit VOUT DAC with ±1LSB INL, DNL Parallel Interface, Precision 16-Bit Settling in 2μs for 10V Step LTC2600/LTC2610/ LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2601/LTC2611/ LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2602/LTC2612/ LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2604/LTC2614/ LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2605/LTC2615/ LTC2625 Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output LTC2606/LTC2616/ LTC2626 Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output LTC2609/LTC2619/ LTC2629 Quad 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC LTC2637 Octal I2C 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, I2C Interface LTC2641/LTC2642 Single 16-/14-/12-Bit VOUT DACs with ±1LSB INL, DNL ±1LSB (Max) INL, DNL, 3mm × 3mm DFN and MSOP Packages, 120μA Supply Current, SPI Interface LTC2704 Quad 16-/14-/12-Bit VOUT DACs with ±2LSB INL, ±1LSB DNL Software Programmable Output Ranges Up to ±10V, SPI Interface LTC2754 Quad 16-/14-/12-Bit IOUT DACs with ±1LSB INL, ±1LSB DNL Software Programmable Output Ranges Up to ±10V, SPI Interface LTC2656 Octal 16-/12-Bit VOUT DACs with ±4 LSB INL, ±1 LSB DNL 4mm × 5mm QFN-20, TSSOP-20 Packages, SPI Packages, Internal 10ppm/°C (Max) Reference 2657f 24 Linear Technology Corporation LT 0909 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009