AD EVAL-AD4000FMCZ 16-bit, 2 msps precision pseudo differential adc Datasheet

16-Bit, 2 MSPS Precision
Pseudo Differential ADC
AD4000
Data Sheet
FEATURES
GENERAL DESCRIPTION
Throughput: 2 MSPS maximum
INL: ±1.0 LSB maximum
Guaranteed 16-bit no missing codes
Low power
9.75 mW at 2 MSPS (VDD only)
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
SNR: 93 dB typical at 1 kHz, 90 dB typical at 100 kHz
THD: −115 dB typical at 1 kHz, −95 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range: 0 V to
VREF with VREF between 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay
Guaranteed operation: −40°C to 125°C
Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: 3 mm × 3 mm LFCSP and 3 mm × 4.90 mm
MSOP
The AD4000 is a low noise, low power, high speed, 16-bit,
2 MSPS precision successive approximation register (SAR)
analog-to-digital converter (ADC). It incorporates ease of use
features that lower the signal chain power, reduce signal chain
complexity, and enable higher channel density. The high-Z mode,
coupled with a long acquisition phase, eliminates the need for a
dedicated high power, high speed ADC driver, thus broadening the
range of low power precision amplifiers that can drive this ADC
directly while still achieving optimum performance. The input span
compression feature enables the ADC driver amplifier and the
ADC to operate off common supply rails without the need for a
negative supply while preserving the full ADC code range. The low
serial peripheral interface (SPI) clock rate requirement reduces the
digital input/output power consumption, broadens processor
options, and simplifies the task of sending data across digital
isolation.
Operating from a 1.8 V supply, the AD4000 samples an analog
input (IN+) between 0 V to VREF with respect to a ground sense
(IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000
consumes only 14 mW at 2 MSPS with a minimum of 75 MHz
SCK rate in turbo mode and achieves ±1.0 LSB INL maximum,
no missing codes at 16 bits with 93 dB SNR. The reference voltage
is applied externally and can be set independently of the supply
voltage.
The SPI-compatible versatile serial interface features seven
different modes including the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus and provides an
optional busy indicator. The AD4000 is compatible with 1.8 V,
2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
The AD4000 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +125°C. The device is
pin compatible with the 18-bit, 2 MSPS AD4003.
FUNCTIONAL BLOCK DIAGRAM
2.5V TO 5V
10µF
REF
HIGH-Z
MODE
IN+
IN–
CLAMP
VDD
VIO
AD4000
TURBO
MODE
18-BIT
SAR ADC
SERIAL
INTERFACE
STATUS
BITS
SPAN
COMPRESSON
GND
1.8V TO 5V
SDI
SCK
SDO
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
CNV
14956-001
VREF
VREF /2
0
1.8V
Figure 1.
Rev. 0
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Last Content Update: 11/01/2016
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AD4000
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs.............................................................................. 17
Applications ....................................................................................... 1
Driver Amplifier Choice ........................................................... 18
General Description ......................................................................... 1
Ease of Drive Features ............................................................... 18
Functional Block Diagram .............................................................. 1
Voltage Reference Input ............................................................ 20
Revision History ............................................................................... 2
Power Supply............................................................................... 20
Specifications..................................................................................... 3
Digital Interface .......................................................................... 20
Timing Specifications .................................................................. 5
Register Read/Write Functionality........................................... 21
Absolute Maximum Ratings ............................................................ 7
Status Word ................................................................................. 23
Thermal Resistance ...................................................................... 7
CS Mode, 3-Wire Turbo Mode ................................................. 24
ESD Caution .................................................................................. 7
CS Mode, 3-Wire Without Busy Indicator ............................. 25
Pin Configurations and Function Descriptions ........................... 8
CS Mode, 3-Wire with Busy Indicator .................................... 26
Terminology ...................................................................................... 9
CS Mode, 4-Wire Turbo Mode ................................................. 27
Typical Performance Characteristics ........................................... 10
CS Mode, 4-Wire Without Busy Indicator ............................. 28
Theory of Operation ...................................................................... 14
Circuit Information .................................................................... 14
Converter Operation .................................................................. 14
Transfer Functions...................................................................... 15
Applications Information .............................................................. 16
Typical Application Diagrams .................................................. 16
CS Mode, 4-Wire with Busy Indicator .................................... 29
Daisy-Chain Mode ..................................................................... 30
Layout Guidelines....................................................................... 31
Evaluating the AD4000 Performance ...................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD4000
SPECIFICATIONS
VDD = 1.8 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and
turbo mode enabled, (fS = 2 MSPS), unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Input Leakage Current
Test Conditions/Comments
Min
16
VIN+ − VIN−
VIN+ to GND
VIN− to GND
Span compression enabled
Acquisition phase, T = 25°C
High-Z mode enabled, converting dc input
at 2 MSPS
0
−0.1
−0.1
0.1 × VREF
THROUGHPUT
Complete Cycle
Conversion Time
Acquisition Phase 1
Throughput Rate 2
Transient Response 3
DC ACCURACY
No Missing Codes
Integral Linearity Error
Max
Unit
Bits
VREF
VREF + 0.1
+0.1
0.9 × VREF
V
V
V
V
nA
µA
0.3
1
500
290
290
0
320
2
150
16
−1.0
−0.8
−0.5
T = 0°C to 85°C
Differential Linearity Error
Transition Noise
Zero Error
Zero Error Drift 4
Gain Error
Gain Error Drift4
Power Supply Sensitivity
1/f Noise 5
AC ACCURACY
Dynamic Range
Total RMS Noise
fIN = 1 kHz, −0.5 dBFS, VREF = 5 V
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
Oversampled Dynamic Range
fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V
SNR
SFDR
THD
SINAD
fIN = 100 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
fIN = 400 kHz, −0.5 dBFS, VREF = 5 V
SNR
THD
SINAD
Typ
−4.5
−0.55
−20
−0.92
VDD = 1.8 V ± 5%
Bandwidth = 0.1 Hz to 10 Hz
91
91
Oversampling ratio (OSR) = 256, VREF = 5 V
85.5
85.5
Rev. 0 | Page 3 of 32
ns
ns
ns
MSPS
ns
0.5
6
Bits
LSB
LSB
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
µV p-p
93.5
37
dB
µV rms
93
112
−115
92.5
dB
dB
dB
dB
117
dB
87.5
115
−113
87
dB
dB
dB
dB
90
−95
89
dB
dB
dB
85
−91
84
dB
dB
dB
±0.2
±0.2
±0.15
0.5
±3
+1.0
+0.8
+0.5
+4.5
+0.55
+20
+0.92
AD4000
Parameter
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
REFERENCE
Voltage Range (VREF)
Current
OVERVOLTAGE CLAMP
IIN+/IIN−
VIN+/VIN− at Maximum IIN+/IIN−
VIN+/VIN− Clamp On/Off Threshold
Deactivation Time
REF Current at Maximum IIN+
DIGITAL INPUTS
Logic Levels
Input Low Voltage, VIL
Input High Voltage, VIH
Data Sheet
Test Conditions/Comments
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
Typ
10
1
1
2.4
2 MSPS, VREF = 5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VIN+ > VREF
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
Max
Unit
MHz
ns
ps rms
5.1
V
mA
50
50
mA
mA
V
V
V
V
ns
µA
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
pF
0.75
5.25
2.68
5.4
3.1
5.4
2.8
360
100
−0.3
−0.3
0.7 × VIO
0.8 × VIO
−1
−1
Input Low Current, IIL
Input High Current, IIH
Input Pin Capacitance
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Output Low Voltage, VOL
Output High Voltage, VOH
POWER SUPPLIES
VDD
VIO
Standby Current
Power Dissipation
Min
6
ISINK = 500 µA
ISOURCE = −500 µA
Serial 16 bits, straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
1.71
1.71
VDD and VIO = 1.8 V, T = 25°C
VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
1 MSPS, high-Z mode enabled
2 MSPS, high-Z mode enabled
2 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
TMIN to TMAX
−40
1.8
1.89
5.5
V
V
1.6
V
V
µA
70
7
14
8
16
9.75
3.75
0.5
7
19
µW
mW
mW
mW
mW
mW
mW
mW
nJ/sample
+125
°C
16
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3
Transient response is the time required for the ADC to acquire a full scale input step to ±0.5 LSB accuracy.
4
The minimum and maximum values are guaranteed by characterization, not production tested.
5
See the 1/f noise plot in Figure 18.
1
2
Rev. 0 | Page 4 of 32
Data Sheet
AD4000
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. 1
Table 2. Digital Interface Timing
Parameter
Conversion Time—CNV Rising Edge to Data Available
Acquisition Phase 2
Time Between Conversions
CNV Pulse Width (CS Mode) 3
SCK Period (CS Mode) 4
VIO > 2.7 V
VIO > 1.7 V
SCK Period (Daisy-Chain Mode) 5
VIO > 2.7 V
VIO > 1.7 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid Delay
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
VIO > 1.7 V
CNV or SDI Low to SDO D15 MSB Valid Delay (CS Mode)
VIO > 2.7 V
VIO > 1.7 V
CNV Rising Edge to First SCK Rising Edge Delay
Last SCK Falling Edge to CNV Rising Edge Delay 6
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode)
SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode)
SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
Typ
290
Max
320
290
500
10
Unit
ns
ns
ns
ns
9.8
12.3
ns
ns
20
25
3
3
1.5
ns
ns
ns
ns
ns
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
7.5
10.5
ns
ns
10
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tQUIET1
tQUIET2
tDIS
tSSDICNV
tHSDICNV
tHSCKCNV
tSSDISCK
tHSDISCK
190
60
20
2
2
12
2
2
See Figure 2 for the timing voltage levels.
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
For turbo mode, tCNVH must match the tQUIET1 minimum.
4
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz.
5
A 50% duty cycle is assumed for SCK.
6
See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2.
1
2
3
Rev. 0 | Page 5 of 32
AD4000
Data Sheet
Table 3. Register Read/Write Timing
Parameter
READ/WRITE OPERATION
CNV Pulse Width 1
SCK Period
VIO > 2.7 V
VIO > 1.7 V
SCK Low Time
SCK High Time
READ OPERATION
CNV Low to SDO D15 MSB Valid Delay
VIO > 2.7 V
VIO > 1.7 V
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
VIO > 1.7 V
CNV Rising Edge to SDO High Impedance
WRITE OPERATION
SDI Valid Setup Time from SCK Rising Edge
SDI Valid Hold Time from SCK Rising Edge
CNV Rising Edge to SCK Edge Hold Time
CNV Falling Edge to SCK Active Edge Setup Time
1
Symbol
Min
tCNVH
tSCK
10
ns
9.8
12.3
3
3
ns
ns
ns
ns
tSCKL
tSCKH
Typ
Max
Unit
tEN
tHSDO
tDSDO
10
13
ns
ns
ns
7.5
10.5
20
ns
ns
ns
1.5
tDIS
tSSDISCK
tHSDISCK
tHCNVSCK
tSCNVSCK
2
2
0
6
ns
ns
ns
ns
For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1
X% VIO1
tDELAY
tDELAY
VIH2
VIL2
1FOR
VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 1.
2MINIMUM
14956-002
VIH2
VIL2
Figure 2. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation
Parameter
THROUGHPUT, CS MODE
3-Wire and 4-Wire Turbo Mode
3-Wire and 4-Wire Turbo Mode and Six Status Bits
3-Wire and 4-Wire Mode
3-Wire and 4-Wire Mode and Six Status Bits
Test Conditions/Comments
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
Rev. 0 | Page 6 of 32
Min
Typ
Max
Unit
2
2
2
1.86
1.82
1.69
1.64
1.5
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Data Sheet
AD4000
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Analog Inputs
IN+, IN− to GND1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature Soldering
ESD Ratings
Human Body Model
Machine Model
Field-Induced Charged Device Model
1
Rating
−0.3 V to VREF + 0.4 V
or ± 50 mA
−0.3 V to +6.0 V
−0.3 V to +2.1 V
−6 V to +2.4 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
260°C reflow as per
JEDEC J-STD-020
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 6. Thermal Resistance
Package Type
RM-101
CP-10-91
1
θJA
147
114
θJC
38
33
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
ESD CAUTION
4 kV
200 V
1.25 kV
See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Note that the clamp cannot sustain the overvoltage condition
for an indefinite time.
Rev. 0 | Page 7 of 32
AD4000
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
IN+ 3
VDD 2
IN+ 3
IN– 4
10 VIO
AD4000
9
SDI
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
GND 5
GND 5
AD4000
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE SPECIFIED PERFORMANCE.
14956-003
REF 1
IN– 4
10 VIO
14956-004
VDD 2
Figure 4. 10-Lead LFCSP Pin Configuration
Figure 3. 10-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin
No.
1
Mnemonic
REF
Type1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
N/A2
EPAD
P
1
2
Description
Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor.
1.8 V Power Supply. The range of VDD is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects
the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when
CNV is low. In daisy-chain mode, the data is read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows.
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is
output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In
this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the
conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed
by clocking in a 16-bit word on SDI on the rising edge of SCK.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
Bypass VIO to GND with a 0.1 μF ceramic capacitor.
Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the
specified performance.
AI is analog input, P is power, DI is digital input, and DO is digital output.
N/A means not applicable.
Rev. 0 | Page 8 of 32
Data Sheet
AD4000
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 30).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) occurs at a level
½ LSB above nominal negative full scale (−4.999981 V for the
±5 V range). The last transition (from 011 … 10 to 011 … 11)
occurs for an analog voltage 1½ LSB below the nominal full
scale (+4.999943 V for the ±5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Effective Resolution = log2(2N/RMS Input Noise)
Effective resolution is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured. The value for dynamic range is
expressed in decibels. It is measured with a signal at −60 dBFS
so that it includes all noise sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
Transient Response
Transient response is the time required for the ADC to to acquire a
full-scale input step to ±0.5 LSB accuracy.
ENOB = (SINADdB − 1.76)/6.02
ENOB is expressed in bits.
Noise Free Code Resolution
Noise free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Noise free code resolution is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Power Supply Rejection Ratio (PSRR)
PSRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the ADC VDD supply of frequency, f.
PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)
where:
PVDD_IN is the power at the frequency, f, at the VDD pin.
PADC_OUT is the power at the frequency, f, in the ADC output.
Rev. 0 | Page 9 of 32
AD4000
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 1.8 V; VIO = 3.3 V; VREF = 5 V; T = 25°C, high-Z mode disabled, span compression disabled and turbo mode enabled
(fS = 2 MSPS), unless otherwise noted.
0.5
0.20
+125°C
+25°C
–40°C
0.4
0.15
0.3
0.10
0.1
DNL (LSB)
INL (LSB)
0.2
0
–0.1
0.05
0
–0.05
–0.2
–0.10
–0.3
8192
16384
24576
32768
40960
49152
57344
65536
CODE
–0.20
0
8192
16384
24576
32768
40960
49152
57344
65536
CODE
Figure 5. INL vs. Code and Temperature, VREF = 5 V
14956-203
0
14956-200
–0.5
+125°C
+25°C
–40°C
–0.15
–0.4
Figure 8. DNL vs. Code and Temperature, VREF = 5 V
0.3
0.20
+125°C
+25°C
–40°C
0.2
0.15
0.10
DNL (LSB)
INL (LSB)
0.1
0
–0.1
0.05
0
–0.05
–0.10
0
8192
16384
24576
32768
40960
49152
57344
65536
CODE
–0.20
14956-201
0
24576
32768
40960
49152
57344
65536
Figure 9. DNL vs. Code and Temperature, VREF = 2.5 V
0.4
0.20
0.3
0.15
0.2
0.10
0.1
0.05
DNL (LSB)
INL (LSB)
16384
CODE
Figure 6. INL vs. Code and Temperature, VREF = 2.5 V
0
–0.1
–0.2
0
–0.05
–0.10
–0.3
–0.15
SPAN COMPRESSION ENABLED
HIGH-Z ENABLED
0
8192
16384
24576
32768
CODE
40960
49152
57344
65536
–0.20
14956-202
–0.4
8192
Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
SPAN COMPRESSION ENABLED
HIGH-Z ENABLED
0
8192
16384
24576
32768
CODE
40960
49152
57344
65536
14956-205
–0.3
+125°C
+25°C
–40°C
–0.15
14956-204
–0.2
Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V
Rev. 0 | Page 10 of 32
Data Sheet
AD4000
50000
90000
VREF = 2.5V
VREF = 5V
45000
40000
70000
60000
CODE COUNT
30000
25000
20000
40000
30000
15000
0
0
14956-206
ADC CODE
32760
32761
32762
32763
32764
32765
32766
32767
32768
32769
32770
32771
32772
32773
32774
32775
32776
32777
32778
32779
32780
10000
32760
32761
32762
32763
32764
32765
32766
32767
32768
32769
32770
32771
32772
32773
32774
32775
32776
32777
32778
32779
32780
5000
Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V, 5 V
ADC CODE
14956-209
20000
10000
Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V, 5 V
0
0
VREF = 5V
SNR = 92.47dB
THD = –115.10dB
SINAD = 92.41dB
–40
VREF = 2.5V
SNR = 87.54dB
THD = –112.33dB
SINAD = 87.49dB
–20
FUNDAMENTAL AMPLITUDE (dB)
–20
–60
–80
–100
–120
–140
–160
–40
–60
–80
–100
–120
–140
–160
1k
10k
100k
1M
FREQUENCY (Hz)
–180
100
14956-207
–180
100
1M
0
VREF = 5V
SNR = 90.16 dB
THD = –94.52dB
SINAD = 88.33dB
FUNDAMENTAL AMPLITUDE (dB)
–20
–60
–80
–100
–120
–140
–160
–40
VREF = 5V
SNR = 84.65 dB
THD = –90.80dB
SINAD = 83.89dB
–60
–80
–100
–120
–140
–160
10k
100k
FREQUENCY (Hz)
1M
14956-211
–180
1k
100k
Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V
0
–40
10k
FREQUENCY (Hz)
Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View
–20
1k
14956-210
FUNDAMENTAL AMPLITUDE (dB)
50000
Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View
–180
1k
10k
100k
FREQUENCY (Hz)
Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View
Rev. 0 | Page 11 of 32
1M
14956-208
CODE COUNT
35000
FUNDAMENTAL AMPLITUDE (dB)
VREF = 2.5V
VREF = 5V
80000
AD4000
Data Sheet
–110
15.3
93
15.2
113
THD
SFDR
–111
112
15.1
15.0
14.8
90
14.7
110
–113
THD (dB)
14.9
91
ENOB (Bits)
SNR, SINAD (dB)
111
–112
92
109
–114
108
–115
107
14.6
89
–116
108
14.5
88
–117
14.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
14.3
5.1
REFERENCE VOLTAGE (V)
107
–118
2.4
14956-213
87
2.4
SFDR (dB)
ENOB
SINAD
SNR
Figure 17. SNR, SINAD, and ENOB vs. Reference Voltage
2.7
3.0
3.3
3.6
3.9
4.2
REFERENCE VOLTAGE (V)
4.5
106
5.1
4.8
14956-216
94
Figure 20. THD and SFDR vs. Reference Voltage
955
800
750
REFERENCE CURRENT (µA)
953
952
951
950
949
700
650
600
550
500
450
400
350
0
2
4
6
8
10
TIME (Seconds)
300
2.4
14956-218
948
2.7
3.0
3.3
3.9
3.6
4.2
4.5
4.8
5.1
REFERENCE VOLTAGE (V)
Figure 18. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples
Averaged per Reading
Figure 21. Reference Current vs. Reference Voltage
125
93.4
DYNAMIC RANGE
fIN = 1kHz
fIN = 10kHz
120
14956-219
ADC OUTPUT READING (µV)
954
15.25
93.2
15.20
115
15.10
92.6
15.05
95
92.4
90
92.2
85
0
2
4
8
16
32
64
128
256
512 1024 2048
DECIMATION RATE
ENOB (Bits)
100
14956-214
SNR (dB)
105
15.15
92.8
15.00
ENOB
SINAD
SNR
92.0
14.95
0
10
20
30
40
50
60
tQUIET2 (ns)
Figure 22. SINAD, SNR, and ENOB vs. tQUIET2
Figure 19. SNR vs. Decimation Rate for Various Input Frequencies
Rev. 0 | Page 12 of 32
70
14956-217
SNR, SINAD (dB)
93.0
110
Data Sheet
AD4000
–102
15.10
92.8
92.4
92.2
15.00
THD (dB)
15.05
ENOB (Bits)
92.6
92.0
91.8
14.95
91.6
14.90
–20
0
20
40
60
80
100
14956-220
91.4
–40
111
THD
SFDR
120
TEMPERATURE (°C)
110
–104
109
–106
108
–108
107
–110
106
–112
105
–114
104
–116
103
–118
–40
SFDR (dB)
93.0
102
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 23. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz
Figure 26. THD and SFDR vs. Temperature, fIN = 1 kHz
12
8
11
7
6
STANDBY CURRENT (µA)
OPERATING CURRENT (mA)
10
5
VDD HIGH-Z ENABLED
VDD HIGH-Z DISABLED
REF HIGH-Z ENABLED
REF HIGH-Z DISABLED
VIO HIGH-Z ENABLED
VIO HIGH-Z DISABLED
4
3
2
9
8
7
6
5
4
3
2
1
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
–40
14956-226
–20
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 24. Operating Currents vs. Temperature
14956-224
1
0
–40
Figure 27. Standby Current vs. Temperature
23
1.0
ZERO ERROR
GAIN ERROR
0.8
VIO = 5.0V
VIO = 3.3V
VIO = 1.8V
21
0.6
19
0.4
17
tDSDO (ns)
0.2
0
–0.2
15
13
11
–0.4
9
–0.6
–1.0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
5
0
20
40
60
80
100
120
140
160
180
LOAD CAPACITANCE (pF)
Figure 28. tDSDO vs. Load Capacitance
Figure 25. Zero Error and Gain Error vs. Temperature
Rev. 0 | Page 13 of 32
200
220
14956-228
7
–0.8
14956-223
ZERO ERROR AND GAIN ERROR (LSB)
SNR, SINAD (dB)
–100
15.15
SNR
SINAD
ENOB
14956-222
93.2
AD4000
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
LSB
MSB
REF
32,768C
16,384C
4C
2C
C
SW+
C
BUSY
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
C
MSB
OUTPUT CODE
LSB
SW–
14956-006
CNV
IN–
Figure 29. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD4000 is a high speed, low power, single-supply, precise,
16-bit pseudo differential ADC using a successive
approximation architecture.
The AD4000 is capable of converting 2,000,000 samples per
second (2 MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it typically consumes 70 µW,
making it ideal for battery-powered applications because its
power scales linearly with throughput. The AD4000 has a valid
first conversion after being powered down for long periods.
The fast conversion time of the AD4000, along with turbo
mode, allows low clock rates to read back conversions even when
running at the full 2 MSPS throughput rate. Note that a throughput
rate of 2 MSPS can be achieved only with turbo mode.
The AD4000 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP
that allows space savings and flexible configurations.
It is pin for pin-compatible with the 14-/16-/18-bit precision
SAR ADCs listed in Table 8.
Table 8. MSOP, LFCSP 14-/16-/18-Bit Precision SAR ADCs
The AD4000 provides the user with an on-chip track-and-hold
circuit and does not exhibit any pipeline delay or latency,
making it ideal for multiplexed applications.
Bits 100 kSPS
181 AD7989-12
250 kSPS
AD7691
400 kSPS to 500 kSPS
AD7690, AD7989-5
The AD4000 incorporates a multitude of unique ease of use
features that result in a lower system power and footprint.
161
AD7684
AD7687
The AD4000 has an internal voltage clamp that protects the
device from overvoltage damage on the analog inputs.
163
AD7685,
AD7694
The analog input incorporates circuitry that reduces the
nonlinear charge kickback seen from a typical switched capacitor
SAR input. This reduction in kickback, combined with a longer
acquisition phase, means reduced settling requirements on the
driving amplifier. This combination allows the use of lower
bandwidth and lower power amplifiers as drivers. It has the
additional benefit of allowing a larger resistor value in the input
RC filter and a corresponding smaller capacitor, which results
in a smaller RC load for the amplifier, improving stability and
power dissipation.
143
AD7680,
AD7683,
AD7988-1
AD7940
AD7688, AD7693,
AD7916
AD7686, AD7988-5
High-Z mode can be enabled via the SPI interface by programming
a register bit (see Table 14). When high-Z mode is enabled, the
ADC input has low input charging current at low input signal
frequencies as well as improved distortion over a wide frequency
range up to 100 kHz. For frequencies above 100 kHz and
multiplexing, disable high-Z mode.
For single-supply applications, a span compression feature
creates additional headroom and footroom for the driving
amplifier to access the full range of the ADC.
1
2
3
AD7942
≥1000 kSPS
AD4003,
AD7982,
AD7984
AD7915
AD4000,
AD7980,
AD7983
AD7946
True differential.
Pin for pin-compatible.
Pseudo differential.
CONVERTER OPERATION
The AD4000 is a successive approximation register (SAR)based ADC using a charge redistribution digital-to-analogconverter (DAC). Figure 29 shows the simplified schematic of
the ADC. The capacitive DAC consists of two identical arrays of
16 binary weighted capacitors, which are connected to the two
comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
Rev. 0 | Page 14 of 32
Data Sheet
AD4000
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the IN+ and IN− inputs captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and VREF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the control logic generates the ADC output code and a busy
signal indicator.
Because the AD4000 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Table 9. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1
111...111
111...110
111...101
000...010
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
14956-007
ADC CODE (STRAIGHT BINARY)
The ideal transfer characteristics for the AD4000 are shown in
Figure 30 and Table 9.
–FSR + 0.5 LSB
VREF = 5 V
with Span
Compression
Enabled (V)
4.499939
2.500061
2.5
2.499939
0.50006103
0.5
Digital
Output
Code
(Hex)
FFFF1
8001
8000
7FFF
0001
00002
This output code is also the code for an overranged analog input (VIN+ − VIN−
above VREF − 0 V).
2
This output code is also the code for an underranged analog input (VIN+ −
VIN− below 0 V).
TRANSFER FUNCTIONS
000...001
000...000
–FSR
Analog
Input,
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 μV
0V
Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Rev. 0 | Page 15 of 32
AD4000
Data Sheet
APPLICATIONS INFORMATION
Figure 32 shows a recommended connection diagram when
using a single-supply system. This setup is preferable when only
a limited number of rails are available in the system and power
dissipation is of critical importance.
TYPICAL APPLICATION DIAGRAMS
Figure 31 shows an example of the recommended connection
diagram for the AD4000 when multiple supplies are available.
This configuration is used for best performance because the
amplifier supplies can be selected to allow the maximum signal
range.
V+ ≥ +6.5V
REF1
LDO
1.8V
AMP
VCM = VREF/2
5V
10kΩ
100nF
10kΩ
VREF
VCM = VREF/2
1.8V TO 5V
100nF
HOST
SUPPLY
10µF
V+
R
AMP
REF
C
0V
VDD
VIO
SDI
IN+
V–
SCK
AD4000
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
SDO
IN–
CNV
GND
14956-008
3-WIRE/4-WIRE
INTERFACE
V– ≤ –0.5V
Figure 31. Typical Application Diagram with Multiple Supplies
V+ = 5V
REF1
LDO
AMP
VCM = VREF/2
4.096V
10kΩ
10kΩ
V+
0.9 × VREF
VCM = VREF/2
0.1 × VREF
AMP
1.8V
100nF
100nF
1.8V TO 5V
HOST
SUPPLY
10µF1
R
REF
C
VDD
VIO
SDI
IN+
AD40002
3
SCK
SDO
IN–
GND
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
CNV
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).
2SPAN COMPRESSION MODE ENABLED.
3SEE TABLE 9 FOR RC FILTER AND AMPLIFIER SELECTION.
Figure 32. Typical Application Diagram with a Single Supply
Rev. 0 | Page 16 of 32
14956-009
3-WIRE/4-WIRE
INTERFACE
Data Sheet
AD4000
ANALOG INPUTS
Figure 33 shows an equivalent circuit of the analog input
structure, including the overvoltage clamp of the AD4000.
Overvoltage Clamp Circuit
Most ADC analog inputs, IN+ and IN−, have no overvoltage
protection circuitry apart from ESD protection diodes. During
an overvoltage event, an ESD protection diode from an analog
input (IN+) pin to REF forward biases and shorts the input pin
to REF, potentially overloading the reference or causing damage
to the device. The AD4000 internal overvoltage clamp circuit
with a larger external resistor (REXT = 200 Ω) eliminates the
need for external protection diodes and protects the ADC
inputs against dc overvoltages.
In applications where the amplifier rails are greater than VREF
and less than GND, it is possible for the output to exceed the
input voltage range of the device. In this case, the AD4000
internal voltage clamp circuit ensures that the voltage on the
input pin does not exceed VREF + 0.4 V and prevents damage to
the device by clamping the input voltage in a safe operating
range and avoiding disturbance of the reference; this is
particularly important for systems that share the reference
among multiple ADCs.
If the analog input exceeds the reference voltage by 0.4 V, the
internal clamp circuit turns on and the current flows through
the clamp into ground, preventing the input from rising further
and potentially causing damage to the device. The clamp turns
on before D1 (see Figure 33) and can sink up to 50 mA of current.
When the clamp is active, it sets the OV clamp flag bit in the
register that can be read back (see Table 14), which is a sticky bit
that must be read to be cleared. The status of the clamp can also
be checked in the status bits using an overvoltage clamp flag (see
Table 15). The clamp circuit does not dissipate static power in the
off state. Note that the clamp cannot sustain the overvoltage
condition for an indefinite time.
The external RC filter is usually present at the ADC input to
band limit the input signal. During an overvoltage event,
excessive voltage is dropped across REXT and REXT becomes part
of a protection circuit. The REXT value can vary from 200 Ω to
20 kΩ for 15 V protection. The CEXT value can be as low as 100
pF for correct operation of the clamp. See Table 1 for input
overvoltage clamp specifications.
REF
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
By using IN− to sense a remote signal ground, ground potential
differences between the sensor and the local ADC ground are
eliminated.
Switched Capacitor Input
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 40 pF and
is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are open, the
input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and
limits noise.
RC Filter Values
The value of the RC filter and driving amplifier can be selected
depending on the input signal bandwidth of interest at the full
2 MSPS throughput. Lower input signal bandwidth means that
the RC cutoff can be lower, thereby reducing noise into the
converter. For optimum performance at various throughputs,
use the recommended RC values (200 Ω, 180 pF) and the
ADA4805-1.
The RC values in Table 10 are chosen for ease of drive
considerations and also greater ADC input protection. The
combination of a large R value (200 Ω) and small C value result
in a reduced dynamic load for the amplifier to drive. The smaller
value of C means less stability/phase margin concerns with the
amplifier. The large value of R limits the current into the ADC
input when the amplifier output exceeds the ADC input range.
Table 10. RC Filter and Amplifier Selection for Various
Input Bandwidths
Input Signal
Bandwidth (kHz)
<10
R (Ω)
C (pF)
<200
>200
Multiplexed
200
200
200
180
120
120
D1
VIN
REXT
RIN CIN
IN+
CEXT
CPIN
D2
CLAMP
GND
14956-010
0V TO 15V
Figure 33. Equivalent Analog Input Circuit
Rev. 0 | Page 17 of 32
Recommended Amplifier
See the High-Z Mode
section
ADA4805-1
ADA4897-1
ADA4897-1
AD4000
Data Sheet
94
DRIVER AMPLIFIER CHOICE
Although the AD4000 is easy to drive, the driver amplifier must
meet the following requirements:
ENOB (Bits)
14.4
88
14.2
86
14.0
13.8
13.6
82
13.4
10k
13.2
1M
100k
14956-212
80
1k
INPUT FREQUENCY (Hz)
Figure 34. SNR, THD, and SINAD vs. Frequency, VIO = 3.3 V, VREF = 5 V
–80
For ac applications, the driver must have a THD performance commensurate with the AD4000.
For multichannel multiplexed applications, the driver
amplifier and the AD4000 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0001525%, 15.25 ppm). In the data sheet of the amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
time may differ significantly from the settling time at a
16-bit level and must be verified prior to driver selection.
High Frequency Input Signals
The AD4000 typical ac performance over a wide input frequency
range using a 5 V reference voltage (−0.5 dBFS) is shown in
Figure 34 and Figure 35. Unlike other traditional SAR ADCs,
the AD4000 ac performance holds up to the Nyquist frequency
with minimal performance degradation.
120
THD
SFDR
115
–90
110
–95
105
–100
100
–105
95
–110
90
–115
85
–120
1k
10k
100k
SFDR (dB)
–85
80
1M
INPUT FREQUENCY (Hz)
14956-215

14.6
84






where:
f−3 dB is the input bandwidth, in megahertz, of the AD4000
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.

14.8
Figure 35. THD and SFDR vs. Input Frequency, VIO = 3.3 V, VREF = 5 V
EASE OF DRIVE FEATURES
Input Span Compression
In single-supply applications, it is desirable to use the full range
of the ADC; however, the amplifier can have some headroom
and footroom requirements, which can be a problem, even if it
is a rail-to-rail input and output amplifier. The use of span
compression increases the headroom and footroom available to
the amplifier by reducing the input range by 10% from the top
and bottom of the range while still accessing all available ADC
codes (see Figure 36). The SNR decreases by approximately
1.9 dB (20 × log(4/5)) for the reduced input range when span
compression is enabled. Span compression is disabled by
default, but can be enabled by writing to the relevant register bit
(see the Digital Interface section).
90% OF VREF = 3.69V
VREF = 4.096V
5V
10% OF VREF = 0.41V
IN+
ALL 2N
CODES
ADC
ANALOG
INPUT
–FSR
Figure 36. Span Compression
Rev. 0 | Page 18 of 32
DIGITAL OUTPUT
+FSR
14956-300
SNRLOSS


37
 20 log 
π
 37 2  f  3 dB (NeN )2
2

15.0
90
SNR, SINAD (dB)
The noise generated by the driver amplifier must be kept
low enough to preserve the SNR and transition noise
performance of the AD4000. The noise from the driver is
filtered by the single-pole, low-pass filter of the analog
input circuit made by RIN and CIN, or by the external filter,
if one is used. Because the typical noise of the AD4000 is
37 μV rms, the SNR degradation due to the amplifier is
92
THD (dB)

15.2
ENOB
SINAD
SNR
Data Sheet
AD4000
High-Z Mode
The AD4000 incorporates high-Z mode, which reduces the
nonlinear charge kickback when the capacitor DAC switches
back to the input at the start of acquisition. Figure 37 shows the
input current of the AD4000 with high-Z mode enabled and
disabled. The low input current makes the ADC easier to drive
than the traditional SAR ADCs available in the market, even
with high-Z mode disabled. The input current reduces further
to sub microampere range when high-Z mode is enabled. The
high-Z mode is disabled by default, but can be enabled by
writing to the register (see Table 14). Disable high-Z mode for
input frequencies above 100 kHz or multiplexing.
25
HIGH-Z DISABLED
HIGH-Z ENABLED
20
INPUT CURRENT (µA)
15
10
5
0
–5
–10
–15
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
–25
INPUT DIFFERENTIAL VOLTAGE (V)
14956-221
–20
Figure 37. Input Current vs. Input Differential Voltage,
VIO = 3.3 V, VREF = 5 V
–75
–80
ADC, removing the need for dedicated high speed ADC
drivers, which saves system power, size, and cost in precision,
low bandwidth applications. High-Z mode allows the amplifier
and RC filter in front of the ADC to be chosen based on the signal
bandwidth of interest and not based on the settling requirements of
the switched capacitor SAR ADC inputs.
Additionally, the AD4000 can be driven with a much higher
source impedance than traditional SARs, which means the
resistor in the RC filter can have a value 10 times larger than
previous SAR designs and with high-Z mode enabled can
tolerate even larger impedance. Figure 38 shows the THD performance for various source impedances with high-Z mode disabled
and enabled. Figure 39 and Figure 40 show the AD4000 SNR and
THD performance using the ADA4077-1 (IQUIESCENT = 400 µA/
amplifier), and ADA4610-1 (IQUIESCENT = 1.5 mA/amplifier)
precision amplifiers when driving the AD4000 at the full
throughput of 2 MSPS for both high-Z mode enabled and
disabled with various RC filter values. These amplifiers achieve
91 dB to 92 dB typical SNR and close to −100 dB typical THD
with high-Z enabled for a 2.27 MHz RC bandwidth. THD is
approximately 5 dB better with high-Z mode enabled, even for
large R values greater than 200 Ω. SNR holds up close to 85 dB
even with a very low RC filter cutoff.
When high-Z mode is enabled, the ADC consumes approximately
2 mW extra power; however, this is still significantly lower than
using dedicated ADC drivers like the ADA4807-1. For any system,
the front end usually limits the overall ac/dc performance of the
signal chain. It is evident from the data sheet of the selected
precision amplifiers shown in Figure 39 and Figure 40 that their
own noise and distortion performance dominates the SNR and
THD specification at a certain input frequency.
–85
95
THD (dB)
–90
500Ω HIGH-Z OFF
500Ω HIGH-Z ON
1000Ω HIGH-Z OFF
1000Ω HIGH-Z ON
–95
90
–100
–115
1
2
5
10
INPUT FREQUENCY (kHz)
20
50
14956-225
–110
85
80
75
Figure 38. THD vs. Input Frequency for Various Source Impedances, VREF = 5 V
System designers looking to achieve the optimum data sheet
performance from high resolution precision SAR ADCs are
often forced to use a dedicated high power, high speed amplifier
to drive the traditional switched capacitor SAR ADC inputs for
their precision applications, which is one of the common pain
points encountered in designing a precision data acquisition
signal chain. The benefits of high-Z mode are low input current
for slow (<10 kHz) or dc type signals and improved distortion
(THD) performance over a frequency up to 100 kHz. High-Z
mode allows a choice of lower power and lower bandwidth
precision amplifiers with a lower RC filter cutoff to drive the
70
ADA4077-1 HIGH-Z
ADA4077-1 HIGH-Z
ADA4610-1 HIGH-Z
ADA4610-1 HIGH-Z
260.482kHz 497.981kHz
1.3MHz
2.27MHz
1.3kΩ
680Ω
680Ω
390Ω
470pF
470pF
180pF
180pF
RC FILTER BANDWIDTHS (Hz),
RESISTOR (Ω), CAPACITOR (pF)
ENABLED
DISABLED
ENABLED
DISABLED
4.42MHz
200Ω
180pF
14956-229
SNR (dB)
200Ω HIGH-Z OFF
200Ω HIGH-Z ON
–105
Figure 39. SNR vs. RC Filter Bandwidth for Various Precision ADC Drivers, VREF = 5 V,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VIO = 3.3 V
Rev. 0 | Page 19 of 32
AD4000
Data Sheet
VDD and VIO pins. The AD4000 is independent of power supply
sequencing between VIO and VDD. Additionally, the AD4000 is
insensitive to power supply variations over a wide frequency
range, as shown in Figure 41.
–70
–75
–80
THD (dB)
–85
80
–90
–95
75
PSRR (dB)
–100
260.482kHz 497.981kHz
1.3MHz
2.27MHz
1.3kΩ
680Ω
680Ω
390Ω
470pF
470pF
180pF
180pF
RC FILTER BANDWIDTHS (Hz),
RESISTOR (Ω), CAPACITOR (pF)
4.42MHz
200Ω
180pF
70
65
60
Figure 40. THD vs. RC Bandwidth for Various Precision ADC Drivers, VREF = 5 V,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled)
55
100
1k
10k
100k
1M
FREQUENCY (Hz)
Long Acquisition Phase
See Table 10 for details on setting the RC filter bandwidth and
choosing a suitable amplifier.
Figure 41. PSRR vs. Frequency, VIO = 3.3 V, VREF = 5 V
The AD4000 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. This feature makes the device ideal for low
sampling rates (even of a few hertz) and low battery-powered
applications. Figure 42 shows the AD4000 total power
dissipation and individual power dissipation for each rail.
100k
10k
POWER DISSIPATION (µW)
The AD4000 also features a very fast conversion time of 290 ns,
which results in a long acquisition phase. The acquisition is further
extended by a key feature of the AD4000: the ADC returns back
to the acquisition phase typically 100 ns before the end of the
conversion. This feature provides an even longer time for the ADC
to acquire the new input voltage. A longer acquisition phase
reduces the settling requirement on the driving amplifier, and a
lower power/bandwidth amplifier can be chosen. The longer
acquisition phase means that a lower RC filter cutoff can be used,
which means a noisier amplifier can also be tolerated. A larger
value of R can be used in the RC filter with a corresponding smaller
value of C, reducing amplifier stability concerns without impacting
distortion performance significantly. A larger value of R also
results in reduced dynamic power dissipation in the amplifier.
VOLTAGE REFERENCE INPUT
VDD
VIO
VREF
TOTAL POWER
1k
100
10
1
0.1
A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate
for the optimum performance of the reference input.
For higher performance and lower drift, use a reference such as
the ADR4550. Use a low power reference such as the ADR3450
at the expense of a slight decrease in the noise performance. It is
recommended to use a reference buffer such as the ADA4807-1
between the reference and the ADC reference input. It is important
to consider the optimum size of capacitance necessary to keep
the reference buffer stable as well as to meet the minimum ADC
requirement stated previously in this section.
POWER SUPPLY
The AD4000 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, VIO and VDD can be tied together
for 1.8 V operation. The ADP7118 low noise, CMOS, low
dropout (LDO) linear regulator is recommended to power the
0.01
10
100
1k
10k
100k
1M
THROUGHPUT (Hz)
14956-227
–115
ENABLED
DISABLED
ENABLED
DISABLED
14956-231
–110
ADA4077-1 HIGH-Z
ADA4077-1 HIGH-Z
ADA4610-1 HIGH-Z
ADA4610-1 HIGH-Z
14956-230
–105
Figure 42. Power Dissipation vs. Throughput, VIO = 1.8 V, VREF = 5 V
DIGITAL INTERFACE
Although the AD4000 has a reduced number of pins, it offers
flexibility in its serial interface modes. The AD4000 can also be
programmed via 16-bit SPI writes to the configuration registers.
When in CS mode, the AD4000 is compatible with SPI, QSPI™,
digital hosts, and DSPs. In this mode, the AD4000 can use either a
3-wire or 4-wire interface. A 3-wire interface using the CNV,
SCK, and SDO signals minimizes wiring connections, which is
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This interface is useful in low jitter sampling or
simultaneous sampling applications.
Rev. 0 | Page 20 of 32
Data Sheet
AD4000
The AD4000 provides a daisy-chain feature using the SDI input
for cascading multiple ADCs on a single data line similar to a
shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and daisy-chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, daisy-chain mode is always selected.
In either 3-wire or 4-wire mode, the AD4000 offers the option
of forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator, the
user must time out the maximum conversion time prior to
readback.
Table 14. The overvoltage clamp flag is a read only sticky bit,
and it is cleared only if the register is read and the overvoltage
condition is no longer present. It gives an indication of
overvoltage condition when it is set to 0.
Table 12. Register Bits
Register Bits
Overvoltage (OV) Clamp Flag
Span Compression
High-Z Mode
Turbo Mode
Enable Six Status Bits
Default Status
1 bit (default 1: inactive)
1 bit (default 0: disabled)
1 bit (default 0:disabled)
1 bit (default 0: disabled)
1 bit (default 0: disabled)
The state of the SDO on power-up is either low or high-Z,
depending on the states of CNV and SDI, as shown in in Table 11.
All access to the register map must start with a write to the 8-bit
command register in the SPI interface block. The AD4000
ignores all 1s until the first 0 is clocked in; the value loaded into
the command register is always a 0 followed by seven command
bits. This command determines whether that operation is a
write or a read. The AD4000 command register is shown in
Table 13.
Table 11. State of SDO on Power-Up
Table 13. Command Register
The busy indicator feature is enabled in CS mode if CNV or SDI
is low when the ADC conversion ends.
CNV
0
0
1
1
SDI
0
1
0
1
Bit 7
WEN
SDO
Low
High-Z
Low
High-Z
The AD4000 has turbo mode capability in both 3-wire and
4-wire mode. Turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when
enabled. Turbo mode allows a slower SPI clock rate, making
interfacing simpler. A throughput rate of 2 MSPS can be
achieved only with turbo mode enabled and a minimum SCK
rate of 70 MHz.
Status bits can also be clocked out at the end of the conversion
data if the status bits are enabled in the configuration register.
There are six status bits in total as described in Table 15.
The AD4000 is configured by 16-bit SPI writes to the desired
configuration register. The 16-bit word can be written via the
SDI line while CNV is held low. The 16-bit word consists of an
8-bit header and 8-bit register data. For isolated systems, the
ADuM141D is recommended, which has a maximum clock rate
of 70 MHz and allows the AD4000 to run at 2 MSPS.
REGISTER READ/WRITE FUNCTIONALITY
The AD4000 register bits are programmable and their default
statuses are shown in Table 12. The register map is shown in
Bit 6
R/W
Bit 5
0
Bit 4
1
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
All register read/writes must occur while CNV is low. Data on
SDI is clocked in on the rising edge of SCK. Data on SDO is
clocked out on the falling edge of SCK. At the end of the data
transfer, SDO is put in a high impedance state on the rising
edge of CNV if daisy-chain mode is not enabled. If daisy-chain
mode is enabled, SDO goes low on the rising edge of CNV.
Register reads are not allowed in daisy-chain mode.
Register write requires three signal lines: SCK, CNV, and SDI.
During register write, to read the current conversion results on
SDO, the CNV pin must be brought low after the conversion is
completed; otherwise, the conversion results may be incorrect
on SDO; however, the register write occurs regardless.
The LSB of each configuration register is reserved because a
user reading 16-bit conversion data may be limited to a 16-bit
SPI frame. The state of SDI on the last bit in the SDI frame may
be the state that then persists as CNV rises. Because the state of
SDI when CNV rises is part of how the user sets the interface
mode, the user in this scenario may need to set the final SDI
state on that basis.
The timing diagrams in Figure 43 through Figure 45 show how
data is read and written when AD4000 devices are configured in
3-wire, 4-wire, and daisy-chain mode.
Table 14. Register Map
ADDR[1:0]
0x0
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Enable six
status bits
Bit 3
Span
compression
Rev. 0 | Page 21 of 32
Bit 2
High-Z mode
Bit 1
Turbo
mode
Bit 0
Overvoltage (OV) clamp
flag (read only sticky bit)
Reset
0xE1
AD4000
Data Sheet
tCYC
tCNVH
tSCK
CNV
tSCNVSCK
1
2
3
4
5
6
8
7
9
10
11
tHSDISCK
tSSDISCK
SDI
1
WEN
0
1
0
1
ADDR[1:0]
1
0
1
0
1
0
0
D15
D14
14
15
16
tHSDO
tDSDO
tEN
SDO
13
tSCKH
R/W
0
12
D13
D12
D11
D10
D9
D8
tDIS
b6
b7
b5
b4
b3
b2
b1
b0
14956-018
SCK
tSCKL
X
Figure 43. Register Read Timing Diagram
tCYC
tSCK
tCNVH
tHCNVSCK
CNV
tSCNVSCK
SCK
1
tSCKL
2
3
4
6
5
7
8
10
9
11
tHSDISCK
12
13
14
15
16
tSCKH
tSSDISCK
1
WEN
R/W
0
1
0
1
0
0
1
0
1
0
ADDR[1:0]
0
b7
b6
0
b5
b4
b3
b2
b1
1
b0
tHSDO
tEN
tDSDO
SDO
D15
D14
D13
D12
D11
D10
D8
D9
D7
D6
D5
D4
D3
D2
D1
D0
14956-019
SDI
CONVERSION RESULT ON D15:0
Figure 44. Register Write Timing Diagram
tCYC
tCNVH
tSCK
CNV
tSCNVSCK
SCK
tSCKL
1
24
tSCKH
SDIA
SDOA/SDIB
0
COMMAND (0x14)
0
DATA (0xAB)
COMMAND (0x14)
0
DATA (0xAB)
0
0
COMMAND (0x14)
Figure 45. Register Write Timing Diagram, Daisy-Chain Mode
Rev. 0 | Page 22 of 32
0
14956-020
tDIS
SDOB
Data Sheet
AD4000
STATUS WORD
The SDO line goes to high-Z after the sixth status bit is clocked
out (except in daisy-chain mode). The user is not required to
clock out all status bits to start the next conversion. The serial
interface timing for CS mode, 3-wire without busy indicator,
including status bits, is shown in Figure 46.
The 6-bit status word can be appended to the end of a
conversion result, and the default conditions of these bits are
defined in Table 15. The status bits must be enabled in the
register setting. When the overvoltage clamp flag is a 0, it
indicates an overvoltage condition. The overvoltage clamp flag
status bit updates on a per conversion basis.
Table 15. Status Bits (Default Conditions)
Bit 5
Overvoltage (OV) clamp flag
Bit 4
Span compression
Bit 3
High-Z mode
Bit 2
Turbo mode
Bit 1
Reserved
Bit 0
Reserved
SDI = 1
tCYC
tCNVH
CN V
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tCONV
tQUIET2
tSCKL
2
1
3
14
21
22
tSCKH
tHSDO
tEN
SDO
20
16
15
tDSDO
D15
D14
D13
tDIS
D1
D0
b1
STATUS BITS B[5:0]
Figure 46. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
Rev. 0 | Page 23 of 32
b0
14956-021
SCK
AD4000
Data Sheet
CS MODE, 3-WIRE TURBO MODE
after the CNV rising edge. The user must wait tQUIET1 time after
CNV is brought high before bringing CNV low to clock out the
previous conversion result. The user must also wait tQUIET2 time
after the last falling edge of SCK to when CNV is brought high.
This mode is typically used when a single AD4000 is connected
to an SPI-compatible digital host. It provides additional time
during the end of the ADC conversion process to clock out the
previous conversion result, providing a lower SCK rate. The
AD4000 can achieve a throughput rate of 2 MSPS only when
turbo mode is enabled and using a minimum SCK rate of 70 MHz.
The timing diagram is shown in Figure 47.
When the conversion is complete, the AD4000 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output to SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
This mode replaces the 3-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
When SDI is forced high, a rising edge on CNV initiates a
conversion. The previous conversion data is available to read
SDI = 1
tCYC
CNV
tACQ
AQUISITION
AQUISITION
CONVERSION
tSCK
CONV
tSCKL
QUIET2
tQUIET1
1
2
3
14
15
tSCKH
tHSDO
tEN
SDO
16
tDSDO
D15
D14
D13
tDIS
D1
D0
Figure 47. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 24 of 32
14956-026
SCK
Data Sheet
AD4000
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD4000 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when a single AD4000 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 48, and the corresponding timing diagram is
shown in Figure 49.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion is initiated, it continues until
completion irrespective of the state of CNV. This feature can be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
There must not be any digital activity on SCK during the
conversion.
CONVERT
DIGITAL HOST
CNV
VIO
AD4000
SDI
DATA IN
SDO
14956-022
SCK
CLK
Figure 48. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
CONVERSION
ACQUISITION
tSCK
tCONV
tSCKL
SCK
1
2
3
14
tHSDO
15
16
tSCKH
tEN
SDO
tQUIET2
tDSDO
D15
D14
D13
tDIS
D1
Figure 49. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 25 of 32
D0
14956-023
ACQUISITION
AD4000
Data Sheet
SDO line, this transition can be used as an interrupt signal to
initiate the data reading controlled by the digital host. The
AD4000 then enters the acquisition phase and powers down.
The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge
or when CNV goes high (whichever occurs first), SDO returns
to high impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4000 is connected
to an SPI-compatible digital host with an interrupt input.
The connection diagram is shown in Figure 50, and the
corresponding timing diagram is shown in Figure 51.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can select other
SPI devices, such as analog multiplexers; however, CNV must
be returned low before the minimum conversion time elapses
and then held low for the maximum possible conversion time to
guarantee the generation of the busy signal indicator.
If multiple AD4000 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up resistor on the
There must not be any digital activity on the SCK during the
conversion.
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
AD4000
SDO
DATA IN
IRQ
SCK
14956-024
SDI
CLK
Figure 50. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
CONVERSION
ACQUISITION
tSCK
tCONV
tSCKL
SCK
1
2
3
tQUIET2
15
tHSDO
16
17
tSCKH
tDSDO
SDO
D15
D14
tDIS
D1
Figure 51. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 26 of 32
D0
14956-025
ACQUISITION
Data Sheet
AD4000
CS MODE, 4-WIRE TURBO MODE
brought high before bringing SDI low to clock out the previous
conversion result. The user must also wait tQUIET2 time after the
last falling edge of SCK to when CNV is brought high.
This mode is typically used when a single AD4000 is connected
to an SPI-compatible digital host. It provides additional time
during the end of the ADC conversion process to clock out the
previous conversion result, giving a lower SCK rate. The AD4000
can achieve a throughput rate of 2 MSPS only when turbo mode
is enabled and using a minimum SCK rate of 70 MHz. The
timing diagram is shown in Figure 52.
When the conversion is complete, the AD4000 enters the
acquisition phase and powers down. The ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when SDI goes high (whichever occurs first),
SDO returns to high impedance.
This mode replaces the 4-wire with busy indicator mode by
programming the turbo mode register, Bit 1 (see Table 14).
With SDI high, a rising edge on CNV initiates a conversion.
The previous conversion data is available to read after the CNV
rising edge. The user must wait tQUIET1 time after CNV is
CNV
tCYC
tSSDICNV
SDI
tHSDICNV
ACQUISITION
tACQ
ACQUISITION
CONVERSION
tSCK
tCONV
tSCKL
tQUIET2
tQUIET1
1
2
3
14
tHSDO
16
tSCKH
tEN
SDO
15
tDIS
tDSDO
D15
D14
D13
Figure 52. CS Mode, 4-Wire Turbo Mode Timing Diagram
Rev. 0 | Page 27 of 32
D1
D0
14956-031
SCK
AD4000
Data Sheet
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when multiple AD4000 devices are
connected to an SPI-compatible digital host.
When the conversion is complete, the AD4000 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th SCK
falling edge or when SDI goes high (whichever occurs first), SDO
returns to high impedance and another AD4000 can be read.
A connection diagram example using two AD4000 devices is
shown in Figure 53, and the corresponding timing is shown in
Figure 54.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
SDI
CNV
AD4000
SDO
SDI
DIGITAL HOST
AD4000
DEVICE A
DEVICE B
SCK
SCK
DATA IN
SDO
14956-027
CNV
CLK
Figure 53. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tCONV
tQUIET2
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
1
2
14
3
tHSDO
16
17
18
30
31
32
tSCKH
tDSDO
tEN
SDO
15
D15
D14
D13
tDIS
D1
D0
D15
D14
Figure 54. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram
Rev. 0 | Page 28 of 32
D1
D0
14956-028
SCK
Data Sheet
AD4000
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is typically used when a single AD4000 is connected
to an SPI-compatible digital host with an interrupt input, and
when it is desired to keep CNV, which samples the analog input,
independent of the signal used to select the data reading. This
independence is particularly important in applications where
low jitter on CNV is desired.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up resistor on the
SDO line, this transition can be used as an interrupt signal to
initiate the data readback controlled by the digital host. The
AD4000 then enters the acquisition phase and powers down.
The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance.
The connection diagram is shown in Figure 55, and the
corresponding timing is shown in Figure 56.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
CS1
CONVERT
VIO
DIGITAL HOST
CNV
47kΩ
AD4000
SDO
DATA IN
IRQ
SCK
14956-029
SDI
CLK
Figure 55. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tCONV
tQUIET2
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
1
2
3
15
16
17
tSCKH
tHSDO
tDSDO
tDIS
SDO
D15
D14
D1
Figure 56. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram
Rev. 0 | Page 29 of 32
D0
14956-030
tEN
AD4000
Data Sheet
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
The maximum conversion rate is reduced due to the total
readback time.
DAISY-CHAIN MODE
Use this mode to daisy-chain multiple AD4000 devices on a
3-wire or 4-wire serial interface. This feature is useful for
reducing component count and wiring connections, for
example, in isolated multiconverter applications or for systems
with a limited interfacing capacity. Data readback is analogous
to clocking a shift register.
It is possible to write to each ADC register in daisy-chain mode.
The timing diagram is shown in Figure 45. This mode requires
4-wire operation because data is clocked in on the SDI line with
CNV held low. The same command byte and register data can
be shifted through the entire chain to program all ADCs in the
chain with the same register contents, which requires 8 × (N + 1)
clocks for N ADCs. It is possible to write different register contents
to each ADC in the chain by writing to the furthest ADC in the
chain, first using 8 × (N + 1) clocks, and then the second
furthest ADC with 8 × N clocks, and so forth until reaching the
nearest ADC in the chain, which requires 16 clocks for the
command and register data. It is not possible to read register
contents in daisy-chain mode; however the 6 status bits can be
enabled if the user wants to know the ADC configuration. Note
that enabling the status bits requires 6 extra clocks to clock out
the ADC result and the status bits per ADC in the chain. Turbo
mode cannot be used in daisy-chain mode.
A connection diagram example using two AD4000 devices is
shown in Figure 57, and the corresponding timing is shown in
Figure 58.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects daisy-chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
When the conversion is complete, the MSB is output onto SDO
and the AD4000 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked out of SDO by subsequent SCK falling edges. For each
ADC, SDI feeds the input of the internal shift register and is
clocked by the SCK rising edges. Each ADC in the daisy-chain
CONVERT
SDI
CNV
AD4000
SDO
DIGITAL HOST
AD4000
SDI
DEVICE A
DEVICE B
SCK
SCK
SDO
DATA IN
14956-032
CNV
CLK
Figure 57. Daisy-Chain Mode, Connection Diagram
SDIA = 0
tCYC
CNV
tACQ
CONVERSION
ACQUISITION
tCONV
tSCK
tSCKL
tQUIET2
SCK
1
2
3
14
15
tSSDISCK
tHSCKCNV
tQUIET2
16
17
18
30
31
32
tSCKH
tHSDISCK
tEN
D A15
SDOA = SDIB
DA14
DA13
DA1
DA0
tHSDO
tDIS
tDSDO
SDOB
D B15
DB14
DB13
DB1
DB0
DA15
Figure 58. Daisy-Chain Mode, Serial Interface Timing Diagram
Rev. 0 | Page 30 of 32
DA14
DA1
DA0
14956-033
ACQUISITION
Data Sheet
AD4000
LAYOUT GUIDELINES
The PCB that houses the AD4000 must be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. The pinout of the AD4000, with its
analog signals on the left side and its digital signals on the right
side, eases this task.
At least one ground plane must be used. It can be common or
split between the digital and analog sections. In the latter case,
join the planes underneath the AD4000 devices.
14956-034
Avoid running digital lines under the device because they
couple noise onto the die, unless a ground plane under the
AD4000 is used as a shield. Fast switching signals, such as CNV
or clocks, must not run near analog signal paths. Avoid
crossover of digital and analog signals.
Figure 59. Example Layout of the AD4000 (Top Layer)
The AD4000 voltage reference input (REF) has a dynamic
input impedance. Decouple the REF pin with minimal parasitic
inductances by placing the reference decoupling ceramic capacitor
close to (ideally right up against) the REF and GND pins and
connect them with wide, low impedance traces.
14956-035
Finally, decouple the VDD and VIO power supplies of the
AD4000 with ceramic capacitors, typically 100 nF, placed close
to the AD4000 and connected using short, wide traces to provide
low impedance paths and to reduce the effect of glitches on the
power supply lines.
An example of a layout following these rules is shown in
Figure 59 and Figure 60.
Figure 60. Example Layout of the AD4000 (Bottom Layer)
EVALUATING THE AD4000 PERFORMANCE
Other recommended layouts for the AD4000 are outlined
in the documentation of the evaluation board for the AD4000
(EVAL-AD4000FMCZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CH1Z.
Rev. 0 | Page 31 of 32
AD4000
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.23
0.13
6°
0°
0.30
0.15
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 61. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 62. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD4000BRMZ
AD4000BRMZ-RL7
AD4000BCPZ-RL7
EVAL-AD4000FMCZ
1
Integral
Nonlinearity (INL)
±1.0 LSB
±1.0 LSB
±1.0 LSB
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Ordering
Quantity
Tube, 50
Reel, 1000
Reel, 1500
Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14956-0-10/16(0)
Rev. 0 | Page 32 of 32
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
AD4000 Evaluation Board
compatible with EVAL-SDP-CH1Z
Package
Option
RM-10
RM-10
CP-10-9
Branding
Y61
Y61
Y61