ATMEL MMK2-67025EV-30-E Rad. tolerant high speed 8 kb x 16 dual port ram Datasheet

Features
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Fast Access Time: 30/45 ns
Wide Temperature Range: -55°C to +125°C
Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility
Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
More Than One Device
On-chip Arbitration Logic
Versatile Pin Select for Master or Slave:
– M/S = H for Busy Output Flag On Master
– M/S = L for Busy Input Flag On Slave
INT Flag for Port to Port Communication
Full Hardware Support of Semaphore Signaling Between Ports
Fully Asynchronous Operation From Either Port
Battery Back-up Operation: 2V Data Retention
TTL Compatible
Single 5V + 10% Power Supply
QML Q and V with SMD 5962-91617
Rad. Tolerant
High Speed
8 Kb x 16
Dual Port RAM
Introduction
The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit
× 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as
a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.
M67025E
Master and slave devices provide two independent ports with separate control,
address and I/O pins that permit independent, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
power mode.
Using an array of eight transistors (8T) memory cell, the M67025E combines an
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns
over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 µW.
For military/space applications that demand superior levels of performance and reliability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.
Rev. 4146J–AERO–06/03
1
M67025E
Block Diagram
Notes:
1. (MASTER): BUSY is output. (SLAVE): BUSY is input.
2. LB = Lower Byte
UB = Upper Byte
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Pin Configuration
Pin Description
Left Port
Right Port
Names
CSL
CSR
Chip select
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0R – 12R
Address
I/O0L – 15L
I/O0R – 15R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
A0L –
3
12L
M/S
Master or Slave Select
Vcc
Power
GND
Ground
M67025E
4146J–AERO–06/03
M67025E
Functional Description
The M67025E has two ports with separate control, address and I/O pins that permit
independent read/write access to any memory location. These devices have an automatic power-down feature controlled by CS. CS controls on-chip power-down circuitry
which causes the port concerned to go into stand-by mode when not selected (CS high).
When a port is selected access to the full memory array is permitted. Each port has its
own Output Enable control (OE). In read mode, the port’s OE turns the Output drivers on
when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1.
The interrupt flag (INT) allows communication between ports or systems. If the user
chooses to use the interrupt function, a memory location (mail box or message center) is
assigned to each port. The left port interrupt flag (INTL) is set when the right port writes
to memory location 1FFE (HEX). The left port clears the interrupt by reading address
location 1FFE. Similarly, the right port interrupt flag (INTR) is set when the left port writes
to memory location 1FFF (HEX), and the right port must read memory location 1FFF in
order to clear the interrupt flag (INTR). The 16-bit message at 1FFE or 1FFF is userdefined. If the interrupt function is not used, address locations 1FFE and 1FFF are not
reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt
function.
Arbitration Logic
The arbitration logic will resolve an address match or a chip select match down to a minimum of 5 ns determine which port has access. In all cases, an active BUSY flag will be
set for the inhibited port.
The BUSY flags are required when both ports attempt to access the same location
simultaneously. Should this conflict arise, on-chip arbitration logic will determine which
port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that
allow the processor to hold the operation with its associated address and data. It should
be noted that the operation is invalid for the port for which BUSY is set LOW. The inhibited port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are active and the two addresses coincide. The on-chip arbitration determines access in these circumstances. Two modes of
arbitration are provided: (1) if the addresses match and are valid before CS on-chip control logic arbitrates between CSL and CSR for access; or (2) if the CS are low before an
address match, on-chip control logic arbitrates between the left and right addresses for
access (refer to Table 4). The inhibited port’s BUSY flag is set and will reset when the
port granted access completes its operation in both arbitration modes.
Data Bus Width
Expansion
Expanding the data bus width to 32 or more bits in a dual-port RAM system means that
several chips may be active simultaneously. If every chips has a hardware arbitrator,
and the addresses for each arrive at the same time one chip may activate in L BUSY
signal while another activates its R BUSY signal. Both sides are now busy and the
CPUs will wait indefinitely for their port to become free.
To overcome this “Busy Lock-Out’ problem, Atmel has developed a MASTER/SLAVE
system which uses a single hardware arbitrator located on the MASTER. The SLAVE has
BUSY inputs which allow direct interface to the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented
from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a conflict situation. Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is
inherent in all dual-port memory systems where more than one chip is active at the same time.
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4146J–AERO–06/03
The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER’s BUSY signal.
Semaphore Logic
The M67025E is an extremely fast dual-port 4 Kb × 16 CMOS static RAM with an additional
locations dedicated to binary semaphore flags. These flags allow either of the processors on the
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by one processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.
The dual-port RAM has a fast access time, and the two ports are completely independent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict arising from simultaneous writing to, or a simultaneous READ/WRITE operation on, a nonsemaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in Table 1 where CS and SEM are both high.
Systems best able to exploit the M67025E are based around multiple processors or controllers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.
Software handshaking between processors offers the maximum level of system flexibility by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more usual methods of hardware
arbitration is that neither processor ever incurs wait states. This can prove to be a considerable advantage in very high speed systems.
How The Semaphore
Flags Work
The semaphore logic is a set of eight latches independent of the dual-port RAM. These
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provides the hardware context for the “Token
Passing Allocation’ method of use assignment. This method uses the state of a semaphore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left processor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the status of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.
The semaphore flags are active low. A token is requested by writing a zero to a semaphore latch, and is relinquished again when the same side writes a one to the latch.
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M67025E
4146J–AERO–06/03
M67025E
The eight semaphore flags are located in a separate memory space from the dual-port
RAM in the M67025E. The address space is accessed by placing a low input on the
SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins
(address, OE and R/W) as normally used in accessing a standard static RAM. Each of the flags
has a unique address accessed by either side through address pins A0-A2. None of the other
address pins has any effect when accessing the semaphores. Only data pin D0 is used when
writing to a semaphore. If a low level is written to an unused semaphore location, the flag will be
set to zero on that side and to one on the other side (see Table 5). The semaphore can now
only be modified by the side showing the zero. Once a one is written to this location from the
same side, the flag will be set to one for both sides (unless a request is pending from the other
side) and the semaphore can then be written to by either side.
The effect the side writing a zero to a semaphore location has of locking out the other
side is the reason for the use of semaphore logic in interprocessor communication. (A
thorough discussion of the use of this feature follows below). A zero written to the semaphore location from the locked-out side will be stored in the semaphore request latch for
that side until the semaphore is relinquished by the side having control. When a semaphore flag is read its value is distributed to all data bits so that a flag set at one reads as
one in all data bits and a flag set at zero reads as all zeros. The read value is latched
into the output register of one side when its semaphore select (SEM) and output enable
(OE) signals go active. This prevents the semaphore changing state in the middle of a read
cycle as a result of a write issued by the other side. Because of this latch, a repeated read of a
semaphore flag in a test loop must cause either signal (SEM or OE) to go inactive, otherwise
the output will never change.
The semaphore must use a WRITE/READ sequence in order to ensure that no system
level conflict will occur. A processor requests access to shared resources by attempting
to write a zero to a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as a one, and
the processor will detect this status in the subsequent read (see Table 5). For example,
assume a processor writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written successfully to that location
and will assume control over the resource concerned. If a processor on the right side
then attempts to write a zero to the same semaphore flag it will fail, as will be verified by
a subsequent read returning a one from the semaphore location on the right side has a
READ/WRITE sequence been used instead, system conflict problems could have
occurred during the interval between the read and write cycles.
It must be noted that a failed semaphore request needs to be followed by either
repeated reads or by writing a one to the same location. The simple logic diagram for
the semaphore flag in Figure 2 illustrates the reason for this quite clearly. Two semaphore request latches feed into a semaphore flag. The first latch to send a zero to the
semaphore flag will force its side of the semaphore flag low and other side high. This
status will be maintained until a one is written to the same semaphore request latch.
Should a zero be written to the other side’s semaphore request latch in the meantime,
the semaphore flag will flip over to this second side as soon as a one is written to the
first side’s request latch. The second side’s flag will now stay low until its semaphore
request latch is changed to a one. Thus, clearly, if a semaphore flag is requested and
the processor requesting it no longer requires access to the resource, the entire system
can hang up until a one is written to the semaphore request latch concerned.
Semaphore timing becomes critical when both sides request the same token by
attempting to write a zero to it at the same time. Semaphore logic is specially conceived
to resolve this problem. The logic ensures that only one side will receive the token if
simultaneous requests are made. The first side to make a request will receive the token
where request do not arrive at the same time. Where they do arrive at the same time,
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the logic will assign the token arbitrarily to one of the ports. It should be noted, however,
that semaphores alone do not guarantee that access to a resource is secure. As with
any powerful programming technique, errors can be introduced if semaphores are misused or misinterpreted. Code integrity is of the utmost performance when semaphores
are being used instead of slower, more restrictive hardware-intensive systems.
Semaphore initialization is not automatic and must therefore be incorporated in the
power up initialization procedures. Since any semaphore flag containing a zero must be
reset to one, initialization should write a one to all request flags from both sides to
ensure that they will be available when required.
Using Semaphores –
Some Examples
Perhaps the simplest application of semaphores is their use as resource markers for the
M67025E’s dual-port RAM. If it is necessary to split the 8 Kb × 16 RAM into two 4 Kb × 16
blocks which are to be dedicated to serving either the left or right port at any one time. Semaphore 0 can be used to indicate which side is controlling the lower segment of memory and
semaphore 1 can be defined as indicating the upper segment of memory.
To take control of a resource, in this case the lower 4 Kb of a dual-port RAM, the left port
processor would then write a zero into semaphore flag 0 and then read it back. If successful in taking the token (reading back a zero rather than a one), the left processor
could then take control of the lower 4 Kb of RAM. If the right processor attempts to perform the same function to take control of the resource after the left processor has
already done so, it will read back a one in response to the attempted write of a zero into
semaphore 0. At this point the software may choose to attempt to gain control of the
second 4 Kb segment of RAM by writing and then reading a zero in semaphore 1. If successful, it will lock out the left processor.
Once the left side has completed its task it will write a one to semaphore 0 and may then
attempt to access semaphore 1. If semaphore 1 is still occupied by the right side, the left
side may abandon its semaphore request and perform other operations until it is able to
write and then read a zero in semaphore 1. If the right processor performs the same
operation with semaphore 0, this protocol would then allow the two processes to swap
4 Kb blocks of dual-port RAM between one another.
The blocks do not have to be any particular size, and may even be of variable size
depending on the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the dual-port RAM or other shared resources into eight
parts. Semaphores can even be assigned different meanings on each side, rather than
having a common meaning as is described in the above example.
Semaphores are a useful form of arbitration in systems such as disk interfaces where
the CPU must be locked out of a segment of memory during a data transfer operation,
and the I/0 device cannot tolerate any wait states. If semaphores are used, both the
CPU and the I/0 device can access assigned memory segments, without the need for
wait states, once the two devices have determined which memory area is barred to the
CPU.
Semaphores are also useful in applications where no memory WAIT state is available
on one or both sides. On a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in complex data structures. Block arbitration is very important in
this case, since one processor may be responsible for building and updating a data
structure whilst the other processor reads and interprets it. A major error condition may
be created if the interpreting processor reads an incomplete data structure. Some sort of
arbitration between the two different processors is therefore necessary. The building
processor requests access to the block, locks it and is then able to enter the block to
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M67025E
4146J–AERO–06/03
M67025E
update the data structure. Once the update is completed the data structure may be
released.
This allows the interpreting processor, to return to read the complete data structure, thus
ensuring a consistent data structure.
Truth Table
Table 1. Non Contention Read/Write Control
Note: Inputs(1)
Outputs
CS
R/W
OE
UB
LB
SEM
IO8 - IO15
I/O0- I/O7
Mode
H
X
X
X
X
H
Hi-Z
Hi-Z
Deselected: Power Down
X
X
X
H
H
H
Hi-Z
Hi-Z
Deselected: Power Down
L
L
X
H
L
H
Hi-Z
DATA IN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATA IN
Write to Both Bytes
L
H
L
L
H
H
DATAOUT
Hi-Z
Read Upper Byte Only
L
H
L
H
L
H
Hi-Z
DATAOUT
Read Lower Byte Only
L
H
L
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
X
X
H
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
H
H
L
X
X
L
DATAOUT
DATAOUT
Read Data in Sema. Flag
X
H
L
H
H
L
DATAOUT
DATAOUT
Read Data in Sema. Flag
H
X
X
X
L
DATAIN
DATA IN
Write DIN0 into Sema. Flag
X
X
H
H
L
DATAIN
DATA IN
Write DIN0 into Sema. Flag
L
X
X
L
X
L
–
–
Not Allowed
L
X
X
X
L
L
–
–
Not Allowed
Note:
1. AOL - A12 ≠ A OR n- A12R
Table 2. Arbitration Options
Inputs
Options
Outputs
CS
UB
LB
M/S
SEM
BUSY
INT
L
X
L
H
H
Output
–
L
L
X
H
H
Signal
L
X
L
L
H
Input
–
L
L
X
L
H
Signal
–
L
X
L
X
H
–
Output
L
L
X
X
H
H
X
X
H
L
H
H
X
X
L
L
Hi-Z
Busy Logic Master
Busy Logic Slave
Interrupt Logic
Semaphore Logic(1)
Note:
Signal
–
1. Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
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4146J–AERO–06/03
Table 3. Interrupt Flag(1) (4)
Left Port
Right Port
R/WL
CSL
OEL
AOL-A12L
INT L
R/WR
CSR
OER
AOR-A12R
INTR
L
L
X
1FFF
X
X
X
X
X
L(2)
Set Right INTR Flag
X
X
X
X
X
X
L
L
1FFF
H(3)
Reset Right INTR Flag
X
X
X
X
L(3)
L
L
X
1FFE
X
Set Left INTL Flag
X
L
L
1FFE
H(2)
X
X
X
X
X
Reset Left INTL Flag
Notes:
1.
2.
3.
4.
Function
Assumes BUSYL = BUSYR = H.
If BUSYL = L, then NC.
If BUSYR = L, then NC.
H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
Table 4. Arbitration(2)
Left Port
Flags (1)
Right Port
CSL
A0L – A12L
CSR
A0R – A12R
BUSYL
BUSYR
Function
H
X
H
X
H
H
No Contention
L
Any
H
X
H
H
No Contention
H
X
L
Any
H
H
No Contention
L
≠ A0R – A12R
L
≠ A 0L – A12L
H
H
No Contention
Address Arbitration With CS Low Before Address Match
L
LV5R
L
LV5R
H
L
L-Port Wins
L
RV5L
L
RV5L
L
H
R-Port Wins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CS Arbitration With Address Match Before CS
LL5R
= A0R – A12R
LL5R
= A0L – A12L
H
L
L-Port Wins
RL5L
= A0R – A12R
RL5L
= A 0L – A12L
L
H
R-Port Wins
LW5R
= A0R – A12R
LW5R
= A0L – A12L
H
L
Arbitration Resolved
LW5R
= A0R – A12R
LW5R
= A0L – A12L
L
H
Arbitration Resolved
Notes:
9
1. INT Flags Don’t Care.
2. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right Address Valid ≥ 5 ns before left address
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
M67025E
4146J–AERO–06/03
M67025E
Table 5. Example Semaphore Procurement Sequence
Function
D0 - D15 Left
D0 - D15 Right
No Action
1
1
Semaphore free
Left Port Writes ’0’ to Semaphore
0
1
Left Port has semaphore token
Right Port Writes ’0’ to Semaphore
0
1
No change. Right side has no write
access to semaphore
Left Port Writes ’1’ to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes ’0’ to Semaphore
1
0
No change. Left port has no write
access to semaphore
Right Port Writes ’1’ to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes ’1’ to Semaphore
1
1
Semaphore free
Right Port Writes ’0’ to Semaphore
1
0
Right port has semaphore token
Right Port Writes ’1’ to Semaphore
1
1
Semaphore free
Left Port Writes ’0’ to Semaphore
0
1
Left Port has semaphore token
Left Port Writes ’1’ to Semaphore
1
1
Semaphore free
Note:
Status
1. This table denotes a sequence of events for only one of the 8 semaphores on the M67025E.
Figure 1. Semaphore Logic
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Electrical Characteristics
Absolute Maximum Ratings
*NOTE:
Supply voltage (VCC-GND): ............................... -0.5V to 7.0V
Input or output voltage applied: (GND - 0.5V) to (VCC + 0.5V)
Storage temperature: ..................................... -65°C to +150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Parameters
Table 6. DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter
Description
Unit
Value
Standby supply current (Both ports TTL level inputs)
10
10
mA
Max
ICCSB1 (2)
Standby supply current (Both ports CMOS level
inputs)
500
500
µA
Max
ICCOP(3)
Operating supply current (Both ports active)
320
260
mA
Max
ICCOP1(4)
Operating supply current (One port active - One
port standby)
200
180
mA
Max
1.
2.
3.
4.
CSL = CSR > 2.2V.
CSL = CSR > VCC - 0.2V.
Both ports active - Maximum frequency - Outputs open - OE = VIH.
One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CSL = CSR > 2.2V
Parameter
67025E
Unit
Value
Input/Output leakage current
±5
µA
Max
VIL (2)
Input low voltage
0.8
V
Max
VIH(2)
Input high voltage
2.2
V
Min.
VOL (3)
Output low voltage (I/O0 - I/O15)
0.4
V
Max
VOH(3)
Output high voltage
2.4
V
Min.
Input capacitance
5
pF
Max
Output capacitance
7
pF
Max
IL I/O (1)
C IN
C OUT
11
67025-45
ICCSB(1)
Notes:
1.
2.
3.
67025-30
Description
Vcc = 5.5V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
VIH max = Vcc + 0.5V, VIL min = -0.5V or -1V pulse width 50 ns.
Vcc Min., IOL = 4 mA, IOH = -4 mA.
M67025E
4146J–AERO–06/03
M67025E
Data-retention Mode
Atmel CMOS RAMs are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules ensure data
retention:
1. Chip select (CSL, CSR) must be held high during data retention; within VCC to
VCC - 0.2V.
2. CSL, CSR must be kept between VCC - 0.2V and 70% of VCC during the power
up and power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the minimum operating
voltage (4.5 volts).
Timing
Parameter
Description
Minimum
Maximum
Unit
VDR
Data Retention
Voltage
2.0
–
V
TCDR
Chip deselect to
data retention
time
0
–
ns
TR
Operation
recovery time
TAVAV (1)
–
ns
–
400
µA
Data retention
current
TAVAV = Read cycle time.
VIN (CSL/R) = Vcc
Vcc = 2V
VIL = 0V
VIH = Vcc
ICCDR1 (2)
1.
2.
12
4146J–AERO–06/03
AC Parameters
AC Test Conditions
Input Pulse Levels: GND to 3.0V
Output Reference Levels: 1.5V
Input Rise/Fall Times: 5 ns
Output Load: See Figures 2, 3
Input Timing Reference Levels: 1.5V
Figure 2. Output Load
Figure 3. Output Load (for tHZ, tLZ, tWZ, and tOW)
1(1)
(1)
1
Note:
1. Including scope and jig.
AC Read Characteristics
Table 7. Over the Full Operating Temperature and Supply Voltage Range
M
67025-30
Read Cycle
Symbol(4)
Symbol(5)
TAVAVR
tRC
TAVQV
Min.
Max.
Min.
Max.
Unit
Read cycle time
30
–
45
–
ns
tAA
Address access time
–
30
–
45
ns
TELQV
tACS
Chip Select access time(3)
–
30
–
45
ns
TBLQV
tABE
Byte enable access time(3)
–
30
–
45
ns
TGLQV
tAOE
Output enable access time
–
15
–
25
ns
TAVQX
tOH
Output hold from address change
3
–
3
–
ns
TELQX
tLZ
Output low Z time (1) (2)
3
–
5
–
ns
TEHQZ
tHZ
Output high Z time (1) (2)
–
15
–
20
ns
TPU
tPU
Chip Select to power up time (2)
0
–
0
–
ns
TPD
tPD
Chip disable to power down time (2)
–
50
–
50
ns
TSOP
tSOP
SEM flag update pulse (OE or SEM)
15
–
15
–
ns
TSLQV
tACS
Semaphore Access time(3)
–
30
–
45
ns
Notes:
13
1.
2.
3.
4.
5.
Parameter
M
67025-45
Transition is measured +500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).
This parameter is guaranteed but not tested.
To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to Table 1.
STD symbol.
ALT symbol.
M67025E
4146J–AERO–06/03
M67025E
Timing Waveform of Read
Cycle number 1, Either
Side (1) (2)(4)
Timing Waveform of Read
Cycle number 2, Either Side
(1) (3) (4) (5)
O
Timing Waveform of Read
Cycle number 3, Either Side
(1)(3)(4)(5)
1.
2.
3.
4.
5.
R/W is high for read cycles.
Device is continuously enabled, CS=VIL, UB or LB VIL. This waveform cannot be used for semaphore reads.
Addresses valid prior to or coincident with CS transition low.
OE = VIL
To access RAM, CS=VIL, UB or LB = VIL, SEM = V IH. To access semaphore, CS = VIH, SEM = VIL. Refer to Table 1.
14
4146J–AERO–06/03
AC Write Characteristics
Table 8. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
M
67025-30
Write Cycle
1.
2.
3.
4.
5.
6.
15
Symbol (1)
Symbol (2)
TAVAVW
tWC
TELWH
Parameter
M
67025-45
Unit
Min.
Max.
Min.
Max.
Write cycle time
30
–
45
–
ns
tSW
Chip select to end of write (3)
25
–
40
–
ns
TAVWH
tAW
Address valid to end of write
25
–
40
–
ns
TAVWL
tAS
Address Set-up Time
0
–
0
–
ns
TWLWH
tWP
Write Pulse Width
25
–
35
–
ns
TWHAX
tWR
Write Recovery Time
0
–
0
–
ns
TDVWH
tDW
Data Valid to end of write
20
–
25
–
ns
TGHQZ
tHZ
Output high Z time (4)
–
15
–
20
ns
TWHDX
tDH
Data hold time (6)
0
–
0
–
ns
TWLQZ
tWZ
Write enable to output in high Z
–
15
–
20
ns
TWHQX
tOW
Output active from end of write
0
–
0
–
ns
TSWRD
tSWRD
SEM flag write to read time
10
–
10
–
ns
TSPS
tSPS
SEM flag contention window
10
–
10
–
ns
(5)
(4) (5)
(4) (5) (6)
STD symbol.
ALT symbol.
To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. This condition must be valid
for entire tSW time.
Transition is measured ± 500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).
The parameters is guaranteed but not tested.
The specification fot tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
M67025E
4146J–AERO–06/03
M67025E
Timing Waveform of Write
Cycle number 1, R/W
Controlled Timing (1) (2) (3) (7)
Timing Waveform of Write
Cycle number 2, CS
Controlled Timing (1) (2) (3) (5)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
R/WC or CS must be high during all address transitions.
A write occurs during the overlap (tSW or tWP) of a low CS or SEM and a low R/W.
tWR is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
Transition is measured ± 500 mV from steady state with a 5 pF load (including scope and jig).This parameter is sampled and
not 100% tested.
If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O
drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle,
this requirement does not apply and the write pulse can be as short as the specified tWP.
To access RAM, CS = VIL. SEM = VIH .
To access upper byte CS = V IL, UB = VIL, SEM = V IH.
To access lower byte CS = VIL, LB = V IL, SEM = VIH .
16
4146J–AERO–06/03
AC Busy Characteristics
Table 9. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
M
67025-30
Write Cycle
Parameter
M
67025-45
Min.
Max.
Min.
Max.
Unit
Busy Timing (For Master 67025 only)
tBAA
BUSY Access time
to address
–
30
–
35
ns
tBDA
BUSY Disable time
to address
–
25
–
30
ns
tBAC
BUSY Access time
to Chip Select
–
25
–
30
ns
tBDC
BUSY Disable time
to Chip Select
–
20
–
25
ns
tWDD
Write Pulse to data Delay (1)
–
55
–
70
ns
tDDD
Write data valid to read data delay(1)
–
40
–
55
ns
tAPS
Arbitration priority set-up time (2)
5
–
5
–
ns
tBDD
BUSY disable to valid data
–
(3)
–
(3)
ns
tWB
Write to BUSY input (4)
0
–
0
–
ns
tWH
Write hold after BUSY (5)
20
–
25
–
ns
tWDD
Write pulse to data delay (6)
–
55
–
70
ns
tDDD
Write data valid to read data delay(6)
–
40
–
55
ns
1.
2.
3.
4.
5.
6.
17
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Master 67025 only)’.
To ensure that the earlier of the two ports wins.
tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) to tDDD - tDW (actual).
To ensure that the write cycle is inhibited during contention.
To ensure that a write cycle is completed after contention.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)’.
M67025E
4146J–AERO–06/03
M67025E
Timing Waveform of Read
with BUSY (2) (3) (4) (For Master
67025)
Notes:
1.
2.
3.
4.
To ensure that the earlier of the two port wins.
Write cycle parameters should be adhered to, to ensure proper writing.
Device is continuously enabled for both ports.
OE = L for the reading port.
Notes:
1. Assume BUSY = H for the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
Timing Waveform of Write
with Port-to-Port (1) (2) (3) (For
Slave 67025 Only)
18
4146J–AERO–06/03
Timing Waveform of Write
with BUSY (For Slave 67025)
Timing Waveform of
Contention Cycle number 1,
CS Arbitration
(For Master 67025 only)
19
M67025E
4146J–AERO–06/03
M67025E
Timing Waveform of
Contention Cycle number 2,
Address Valid Arbitration
(For Master 67025 only) (1)
Left Address Valid First:
Right Address Valid First:
Note:
1. CSL = CSR = V IL
20
4146J–AERO–06/03
AC Interrupt Characteristics
Interrupt
Timing
Symbol
Waveform of Interrupt Timing
Notes:
21
1.
2.
3.
4.
67025-30
Parameter
67025-45
Min.
Max.
Min.
Max.
Unit
tAS
Address set-up time
0
–
0
–
ns
tWR
Write recovery time
0
–
0
–
ns
tINS
Interrupt set time
–
25
–
35
ns
tINR
Interrupt reset time
–
25
–
35
ns
(1)
All timing is the same for left and right ports. Port “A’ may be either the left or right port. Port “B’ is the port opposite from “A’.
See interrupt truth table.
Timing depends on which enable signal is asserted last.
Timing depends on which enable signal is de-asserted first.
M67025E
4146J–AERO–06/03
M67025E
32-bit Master/Slave Dual-port
Memory Systems
Note:
1. No arbitration in M67025E (SLAVE). BUSY-IN inhibits write in M67025E SLAVE.
Timing Waveform of
Semaphore Read after Write
Timing, Either Side(1)
Note:
1. CS = VIH for the duration of the above timing (both write and read cycle).
22
4146J–AERO–06/03
Timing Waveform of
Semaphore Contention
Notes:
23
1.
2.
3.
4.
(1) (3) (4)
DOR = D OL VIL, CSR = CSL = V IH, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
Either side “A’ = left and side “B’ = right, or side “A’ = right and side “B’ = left.
This parameter is measured from the point where R/WA or SEMA goes high until R/WB or SEMB goes high.
IF tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain
the flag.
M67025E
4146J–AERO–06/03
M67025E
Ordering Information
Temperature
Range
Speed
Package
Quality Flow
25°C
30 ns
MQFPF84
Engineering Samples
MMK2-67025EV-30
-55 to +125°C
30 ns
MQFPF84
Standard Mil.
MMK2-67025EV-45
-55 to +125°C
45 ns
MQFPF84
Standard Mil.
SMK2-67025EV-30SB
-55 to +125°C
30 ns
MQFPF84
SCC B
SMK2-67025EV-45SB
-55 to +125°C
45 ns
MQFPF84
SCC B
5962-9161709QZC
-55 to +125°C
30 ns
MQFPF84
QML Q
5962-9161706QZC
-55 to +125°C
45 ns
MQFPF84
QML Q
5962-9161709VZC
-55 to +125°C
30 ns
MQFPF84
QML V
5962-9161706VZC
-55 to +125°C
45 ns
MQFPF84
QML V
25°C
30 ns
Die
Engineering Samples
5962-9161709Q9A(1)
-55 to +125°C
30 ns
Die
QML Q
5962-9161709V9A(1)
-55 to +125°C
30 ns
Die
QML V
Part Number
MMK2-67025EV-30-E(1)
MM0-67025EV-30-E(1)
Note:
1. Contact Atmel for availability.
24
4146J–AERO–06/03
Package Drawings
84 lead MQFPF (1.15 inch square)
25
M67025E
4146J–AERO–06/03
M67025E
26
4146J–AERO–06/03
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4146J–AERO–06/03
/xM