ISD5116
Advance Information
Single-Chip Voice Record/Playback Device Up to
16-Minute Duration with Digital Storage Capability
Features Summary
Fully-Integrated Solution
! Single-chip voice record/playback solution
! Dual storage of digital and analog information
Low Power Consumption
! +2.7 to +3.3V (VCC) Supply Voltage
! Supports 2.0V and 3.0V interface logic
! Operating Current:
" ICC Play = 15 mA (typical)
" ICC Rec = 30 mA (typical)
" ICC Feedthrough = 12 mA (typical)
! Standby Current:
" ISB = 1µA (typical)
! Most stages can be individually powered down
to minimize power consumption
Enhanced Voice Features
! One or two-way conversation record
! One or two-way message playback
! Voice memo record and playback
! Private call screening
! In-terminal answering machine
! Personalized outgoing message
! Private call announce while on call
Digital Memory Features
! Up to 4 MB available
! Storage of phone numbers, system configuration
parameters and message address table in cellular
application
Easy-to-use and Control
! No compression algorithm development required
! User-controllable sampling rates
! Programmable analog interface
2
! Fast mode I C serial interface (400 kHz)
! Fully addressable to handle multiple messages
High Quality Solution
! High quality voice and music reproduction
! ISD’s standard 100-year message retention
(typical)
! 100K record cycles (typical) for analog data
! 10K record cycles (typical) for digital data
Options
! Available in die form, µBGA (available upon
request), TSOP and SOIC
! Extended (-20 to +70C) and Industrial (-40 to
+85C) available
ISD5116
ISD5116
28-PIN TSOP
October 2000
SOIC
Page 1
ISD5116
Advance Information
Single-Chip Voice Record/Playback Device Up to
16-Minute Duration with Digital Storage Capability
Features Summary
Fully-Integrated Solution
! Single-chip voice record/playback solution
! Dual storage of digital and analog information
Low Power Consumption
! +2.7 to +3.3V (VCC) Supply Voltage
! Supports 2.0V and 3.0V interface logic
! Operating Current:
" ICC Play = 15 mA (typical)
" ICC Rec = 30 mA (typical)
" ICC Feedthrough = 12 mA (typical)
! Standby Current:
" ISB = 1µA (typical)
! Most stages can be individually powered down
to minimize power consumption
Enhanced Voice Features
! One or two-way conversation record
! One or two-way message playback
! Voice memo record and playback
! Private call screening
! In-terminal answering machine
! Personalized outgoing message
! Private call announce while on call
Digital Memory Features
! Up to 4 MB available
! Storage of phone numbers, system configuration
parameters and message address table in cellular
application
Easy-to-use and Control
! No compression algorithm development required
! User-controllable sampling rates
! Programmable analog interface
2
! Fast mode I C serial interface (400 kHz)
! Fully addressable to handle multiple messages
High Quality Solution
! High quality voice and music reproduction
! ISD’s standard 100-year message retention
(typical)
! 100K record cycles (typical) for analog data
! 10K record cycles (typical) for digital data
Options
! Available in die form, µBGA (available upon
request), TSOP and SOIC
! Extended (-20 to +70C) and Industrial (-40 to
+85C) available
ISD5116
ISD5116
28-PIN TSOP
October 2000
SOIC
Page 1
Product Description
The ISD5116 ChipCorder Product provides high
quality,
fully
integrated,
single-chip
Record/Playback solutions for 8- to 16-minute
messaging applications that are ideal for use in
cellular phones, automotive communications,
GPS/navigation systems and other portable
products. The ISD5116 product is an enhancement
2
of the ISD5000 architecture, providing: 1) the I C
serial port - address, control and duration selection
2
are accomplished through an I C interface to
minimize pin count (ONLY two control lines
required); 2) the capability of the storage array to
store digital, in addition to analog, information.
These features allow customers to store phone
book numbers, system configuration parameters
and message address pointers for message
management capability.
information from the host chipset 2) a private call
announce while on call can be heard from the host
by giving caller-ID on call waiting information from
the host chipset.
Logic Interface Options of 2.0V and 3.0V are
supported by the ISD5116 to accommodate
portable communication products customers (2.0and 3.0-volt required).
®
Like other ChipCorder products, the ISD5116
integrates the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array
on a single-chip. For enhanced voice features, the
ISD5116 eliminates external circuitry by integrating
automatic gain control (AGC), a
power
amplifier/speaker driver, volume control, summing
amplifiers, analog switches, and a car kit interface.
Input level adjustable amplifiers are also included,
providing a flexible interface for multiple
applications.
Analog functions and audio gating have also been
integrated into the ISD5116 product to allow easy
interface with integrated digital cellular chip sets on
the market. Audio paths have been designed to
enable full duplex conversation record, voice
memo, answering machine (including outgoing
message playback) and call screening features.
This product enables playback of messages while
the phone is in standby, AND both simplex and
duplex playback of messages while on a phone call.
Recordings are stored in on-chip nonvolatile
memory cells, providing zero-power message
storage. This unique, single-chip solution is made
possible through ISD’s patented multilevel storage
technology. Voice and audio signals are stored
directly into solid-state memory in their natural,
uncompressed form, providing superior quality
voice and music reproduction.
Additional voice storage features for digital cellular
include: 1) a personalized outgoing message can
be sent to the person by getting caller-ID
ISD5116 Block Diagram
FTHRU
INP
FILTO
MICROPHONE
MIC IN
MIC -
1
(AGPD)
AGCCAP
FILTO
ANA IN
(INS0)
ARRAY
1
SUM1
ARRAY
(
2
( AXG0
AXG1)
FLD0
FLD1
2
(ANALOG)
)
( )
AOS0
AOS1
AOS2
Multilevel/Digital
Storage Array
Array I/O Mux
SUM2
64-bit/samp.
ARRAY OUTPUT MUX
VOL
ARRAY OUT
(DIGITAL)
(ANALOG)
1
INP
ANA IN
2
SUM2
Volume
Control
2
1
(VLPD)
3
VSSA
VSSA
VSSD
VSSD
VCCD
( OPS0
OPS1 )
( )
VOL0
VOL1
VOL2
SP+
SP-
2
(
OPA0
OPA1
)
( VLS0
VLS1 )
Power Conditioning
VCCA
SPEAKER
2
SUM1
(AIPD)
AUX OUT
Spkr.
AMP
ANA IN
ANA IN
AMP
Vol MUX
0.625/0.883/1.25/1.76
ARRAY OUT
AUX
OUT
AMP
FILTO
64-bit/samp.
(DIGITAL)
( AIG0
AIG1 )
October 2000
)
(AOPD)
3
Output MUX
CTRL
(
ANA OUT-
1
SUM2
S2M0
S2M1
ANA OUT+
ANA
OUT
AMP
2
SUM2
( S1S0
S1S1 )
VOL
Σ
ANA IN
1 (FLPD)
1 (FLS0)
Internal
Clock
(AXPD)
XCLK
ANA IN
2
SUM2
Summing
AMP
FILTO
Low Pass
Filter
ARRAY
INPUT
MUX
2
( S1M0
S1M1 )
1
AUX IN
AMP
Σ
SUM1 MUX
SUM1
SUM1 MUX
1.0 / 1.4 / 2.0 / 2.8
AUX IN
AUX IN
INP
Filter
MUX
AGC
Input Source MUX
MIC+
SUM1
Summing
AMP
ANA OUT MUX
6dB
Device Control
VCCD
SCL
SDA
INT
RAC
A0
A1
Page 2
Table of Contents
ISD5116............................................................................................................................................1
1
Overview....................................................................................................................................5
1.1
Speech/Sound Quality .......................................................................................................5
1.2
Duration..............................................................................................................................5
1.3
Flash Storage.....................................................................................................................5
1.4
Microcontroller Interface ....................................................................................................5
1.5
Programming......................................................................................................................5
2
Functional Description ...........................................................................................................6
2.1
Internal Registers...............................................................................................................7
2.2
Memory Organization.........................................................................................................7
2.3
Pinout Table .......................................................................................................................8
3
Operational Modes Description .............................................................................................9
2
3.1
I C Interface .......................................................................................................................9
3.2
Command Byte ................................................................................................................11
3.3
Opcode Summary............................................................................................................11
3.4
Data Bytes........................................................................................................................13
3.5
Configuration Register Bytes ...........................................................................................13
3.6
Power-up Sequence.........................................................................................................15
3.7
Feed through mMde.........................................................................................................15
3.8
Call Record ......................................................................................................................17
3.9
Memo Record...................................................................................................................18
3.10 Memo and Call Playback .................................................................................................19
3.11 Message Cueing ..............................................................................................................20
4
Analog Mode..........................................................................................................................21
4.1
Aux In and Ana In Description .........................................................................................21
4.2
Analog Structure (left half) description.............................................................................22
4.3
Analog Structure (right half) description...........................................................................22
4.4
Volume Control Description .............................................................................................23
4.5
Apeaker and Aux Out Description....................................................................................23
4.6
Ana Out Description.........................................................................................................24
4.7
Analog Inputs ...................................................................................................................24
5
Digital Mode ...........................................................................................................................27
5.1
Writing Data .....................................................................................................................27
5.2
Reading Data ...................................................................................................................27
5.3
Erasing Data ....................................................................................................................27
5.4
Example Command Sequences ......................................................................................28
6
Pin Descriptions ....................................................................................................................31
6.1
Digital I/O Pins .................................................................................................................31
6.2
Analog I/O Pins ................................................................................................................33
6.3
Power and Ground Pins...................................................................................................36
6.4
Sample PC Layout ...........................................................................................................36
7
Electrical Characteristics and Parameters .........................................................................37
7.1
Electrical Characteristics..................................................................................................37
7.2
Parameters.......................................................................................................................38
8
Timing Diagrams ...................................................................................................................45
2
8.1
I C Timing Diagram..........................................................................................................45
8.2
Playback and Stop Cycle .................................................................................................45
8.3
Example of Power Up Command (first 12 bits)................................................................46
October 2000
Page 3
9
I2C Serial Interface Technical Information ..........................................................................47
2
9.1
Characteristics of the I C Serial Interface ........................................................................47
2
9.2
I C Protocol ......................................................................................................................49
10
Device Physical Dimensions ............................................................................................51
10.1.
Plastic Thin Small Outline Package (TSOP) Type e Dimensions................................51
10.2.
Plastic Small Outline Integrated Circuit (soic) Dimensions..........................................52
10.3.
Plastic Dual Inline Package (PDIP) Dimensions..........................................................53
10.4.
Die Bonding Physical Layout........................................................................................54
11
Ordering Information.........................................................................................................56
October 2000
Page 4
1. OVERVIEW
1.1
SPEECH/SOUND QUALITY
The ISD5116 ChipCorder product can be configured via software to operate at 4.0, 5.3, 6.4 and 8.0 kHz
sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration
decreases the sampling frequency and bandwidth, which affects sound quality. The table in the following
section compares filter pass band and product durations.
1.2
DURATION
To meet end-system requirements, the ISD5116 device is a single-chip solution, which provides from 8 to
16 minutes of voice record and playback, depending on the sample rates defined by customer software.
Input Sample
Rate (kHz)
8.0
6.4
5.3
4.0
Duration1
8 min 44 sec
10 min 55 sec
13 min 6 sec
17 min 28 sec
Typical Filter Knee
(kHz)
3.4
2.7
2.3
1.7
1. Minus any pages selected for digital storage
1.3
FLASH STORAGE
One of the benefits of ISD’s ChipCorder technology is the use of on-chip nonvolatile memory, which
provides zero-power message storage. The message is retained for up to 100 years (typically) without
power. In addition, the device can be re-recorded over 10,000 times (typically) for the digital messages
and over 100,000 times (typically) for the analog messages.
A new feature has been added that allows memory space in the ISD5116 to be allocated to either digital
or analog storage when recorded. The fact that a section has been assigned digital or analog data is
stored in the Message Address Table by the system microcontroller when the recording is made.
1.4
MICROCONTROLLER INTERFACE
2
The ISD5116 is controlled through an I C 2-wire interface. This synchronous serial port allows
commands, configurations, address data, and digital data to be loaded to the device, while allowing
status, digital data and current address information to be read back from the device. In addition to the
serial interface, two other pins can be connected to the microcontroller for enhanced interface. These are
the RAC timing pin and the INT pin for interrupts to the controller. Communications with all the internal
registers are through the serial bus, as well as digital memory Read and Write operations.
1.5
PROGRAMMING
The ISD5116 series is also ideal for playback-only applications, where single or multiple messages may
2
be played back when desired. Playback is controlled through the I C interface. Once the desired message
configuration is created, duplicates can easily be generated via a third-party programmer. For more
information on available application tools and programmers, please see the ISD web site at
www.winbond-usa.com
October 2000
Page 5
2 FUNCTIONAL DESCRIPTION
The ISD5116 is a single chip solution for voice and analog storage that also includes the capability to
store digital information in the memory array. The array may be divided between analog and digital
storage, as the user chooses, when configuring the device. The device consists of several sections that
will be described in the following paragraphs.
Looking at the block diagram below, one can see that the ISD5116 may be very easily designed into a
cellular phone. Placing the device between the microphone and the existing voice encoder chip takes
care of the transmit path. The ANA IN is connected between one of the speaker leads on the voice
decoder chip and the speaker is connected to the SPEAKER pins of the ISD5116. Two pins are needed
2
for the I C digital control and digital information for storage.
Baseband
RF
Section
ISD5116
MIC IN+
MIC IN-
BB
Codec
Speaker
MIC+
MIC-
VB
Codec
DSP
Keyboard
ANA OUT+
ANA OUT-
SP OUTSP OUT+
Microcontroller
123456789
ANA IN
SP+
SP-
Earpiece
SDA, SCL
AUX IN
AUX OUT
CAR KIT
Display
Starting at the MICROPHONE inputs, the signal from the microphone can be routed directly through the
chip to the ANA OUT pins through a 6 dB amplifier stage. Or, the signal can be passed through the AGC
amplifier and directed to the ANA OUT pins, directed to the storage array, or mixed with voice from the
receive path coming from ANA IN and be directed to the same places.
In addition, if the phone is inserted into a "hands-free" car kit, then the signal from the pickup microphone
in the car can be passed through to the same places from the AUX IN pin and the phone's microphone is
switched off. Under this situation, the other party's voice from the phone is played into ANA IN and
passed through to the AUX OUT pin that drives the car kit's loudspeaker.
Depending upon whether one desires recording one side (simplex) or both sides (duplex) of a
conversation, the various paths will also be switched through to the low pass filter (for anti-aliasing) and
into the storage array. Later, the cell phone owner can play back the messages from the array. When
this happens the Array Output MUX is connected to the volume control through the Output MUX to the
Speaker Amplifier.
For applications other than a cell phone, the audio paths can be switched into many different
configurations, providing great flexibility.
October 2000
Page 6
2.1
INTERNAL REGISTERS
The ISD5116 has multiple internal registers that are used to store the address information and the
configuration or set-up of the device. The two 16-bit configuration registers control the audio paths
through the device, the sample frequency, the various gains and attenuations, the sections powered up
and down, and the volume settings. These registers are discussed in detail in section 3.5 on page 13.
2.2
MEMORY ORGANIZATION
The ISD5116 memory array is arranged as 2048 rows (or pages) of 2048 bits for a total memory of
4,194,304 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the
analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus at 8 kHz
there is actually room for 8 minutes and 44 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The
contents of a page are either analog or digital. This is determined by instruction (op code) at the time the
data is written. A record of what is analog and what is digital, and where, is stored by the system
microcontroller in the message address table (MAT). The MAT is a table kept in the microcontroller
memory that defines the status of each message “block.” It can be stored back into the ISD5116 if the
power fails or the system is turned off. Using this table allows for efficient message management.
Segments of messages can be stored wherever there is available space in the memory array. [This is
explained in detail for the ISD5008 in Applications Note #9 and will be similarly described in a later Note
for the ISD5116.]
When a page is used for analog storage, the same 32 blocks are present but there are 8 EOM (End-ofMessage) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus, when
recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when the
Stop command is given, but continues until the 32 millisecond block is filled. Then a bit is placed in the
EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode.
2
Digital data is sent and received serially over the I C interface. The data is serial-to-parallel converted and
stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it
becomes the register that is parallel written into the array. The prior write register becomes the new serial
input register. A mechanism is built-in to ensure there is always a register available for storing new data.
Storing data in the memory is accomplished by accepting data one byte at a time and issuing an
acknowledge. If data is coming in faster than it can be written, the chip issues an acknowledge to the host
microcontroller, but holds SCL LOW until it is ready to accept more data.
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
2
array and serially sent to the I C interface. (See section 5 on page 27 for details).
October 2000
Page 7
2.3
PINOUT TABLE
Pin Name
Pin No.
28-pin
TSOP
3
Pin No.
28-pin
SOIC
24
4
25
XCLK
5
26
SCL
8
1
SDA
10
3
A0
11
4
Row Address Clock; an open drain output. The RAC pin goes LOW
TRACLO1 before the end of each row of memory and returns HIGH at
exactly the end of each row of memory.
Interrupt Output; an open drain output that indicates that a set EOM bit
has been found during Playback or that the chip is in an Overflow (OVF)
condition. This pin remains LOW until a Read Status command is
executed.
This pin allows the internal clock of the device to be driven externally for
enhanced timing precision. This pin is grounded for most applications.
Serial Clock Line is part of the I2C interface. It is used to clock the data
into and out of the I2C interface.
Serial Data Line is part of the I2C interface. Data is passed between
devices on the bus over this line.
Input pin that supplies the LSB for the I2C Slave Address.
A1
9
2
Input pin that supplies the LSB +1 bit for the I2C Slave Address.
MIC+
16
8
Differential Positive Input to the microphone amplifier.
MIC-
17
10
Differential Negative Input to the microphone amplifier.
ANA OUT+
18
11
Differential Positive Analog Output for ANA OUT of the device.
ANA OUT-
19
12
Differential Negative Analog Output for ANA OUT of the device.
ACAP
20
13
AGC Capacitor connection. Required for the on-chip AGC amplifier.
SP+
SP-
23
21
16
14
ANA IN
25
18
AUX IN
26
19
AUX OUT
27
20
VCCD
6,7
27,28
VSSD
VSSA
VCCA
12,13
2,15,22
24
5,6
9,15,23
17
NC
1,14,28
7,21,22
Differential Positive Speaker Driver Output.
Differential Negative Speaker Driver Output. When the speaker outputs
are in use, the AUX OUT output is disabled.
Analog Input. This is one of the gain adjustable analog inputs of the
device.
Auxiliary Input. This is one of the gain adjustable analog inputs of the
device.
Auxiliary Output. This is one the analog outputs of the device. When this
output is in use, the SP+ and SP- outputs are disabled.
Positive Digital Supply pins. These pins carry noise generated by
internal clocks in the chip. They must be carefully bypassed to Digital
Ground to insure correct device operation.
Digital Ground pins.
Analog Ground pins.
Positive Analog Supply pin. This pin supplies the low level audio
sections of the device. It should be carefully bypassed to Analog Ground
to insure correct device operation.
No Connect.
RAC
INT
1
Functionality
See the Parameters section of on page 38.
October 2000
Page 8
3 OPERATIONAL MODES DESCRIPTION
3.1
I2C INTERFACE
Important note: The rest of this data sheet will assume that the reader is familiar with the I2C
serial interface. Additional information on I2C may be found in section 9.0 on page 47 of this
document. If you are not familiar with this serial protocol, please read this section to familiarize
yourself with it. A large amount of additional information on I2C can also be found on the Philips
web page at http://www.philips.com/.
3.1.1
I2C Slave Address
The ISD5116 has a 7-bit slave address of <100 00xy> where x and y are equal to the state, respectively,
of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the
address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data.
Therefore, there are 8 possible slave addresses for the ISD5116. These are:
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Slave Address
<100 0000>
<100 0001>
<100 0010>
<100 0011>
<100 0000>
<100 0001>
<100 0010>
<100 0011>
R/W Bit
0
0
0
0
1
1
1
1
HEX Value
80
82
84
86
81
83
85
87
2
To use more than four ISD5116 devices in an application requires some external switching of the I C
interface.
Conventions used in I2C Data
Transfer Diagrams
3.1.2
ISD5116 I2c Operation Definitions
S
= START Condition
There are many control functions used to operate the ISD5116.
Among them are:
P
= STOP Condition
1. READ STATUS COMMAND: The Read Status command is a
read request from the Host processor to the ISD5116 without
delivering a Command Byte. The Host supplies all the clocks
(SCL). In each case, the entity sending the data drives the data
line (SDA). The Read Status Command is executed by the
2
following I C sequence.
DATA
R
W
A
2
1. Host executes I C START
2. Send Slave Address with R/W bit = “1” (Read) 81h
3. Slave (ISD5116) responds back to Host an Acknowledge (ACK)
followed by 8-bit Status word
4. Host sends an Acknowledge (ACK) to Slave
5. Wait for SCL to go HIGH
6. Slave responds with Upper Address byte of internal address
register
7. Host sends an ACK to Slave
8. Wait for SCL to go HIGH
= 8-bit data transfer
= “1” in the R/W bit
= “0” in the R/W bit
= ACK (Acknowledge)
= No ACK
N
= 7-bit Slave
Address
The Box color indicates the
direction of data flow
SLAVE ADDRESS
= Host to Slave (Gray)
= Slave to Host (White)
October 2000
Page 9
9. Slave responds with Lower Address byte of internal address register (A[4:0] will always return set to 0.)
2
10. Host sends a NO ACK to Slave, then executes I C STOP
2
Note that the processor could have sent an I C STOP after the Status Word data transfer and aborted the
transfer of the Address bytes.
A graphical representation of this operation is found below. See the caption box above for more
explanation.
S
SLAVE ADDRESS
R
A
DATA
A
DATA
A
DATA
High Addr.
Status
N
P
Low Addr.
2. LOAD COMMAND BYTE REGISTER (SINGLE BYTE LOAD): A single byte may be written to the
Command Byte Register in order to power up the device, start or stop Analog Record (if no address
information is needed), or do a Message Cueing function. The Command Byte Register is loaded as
follows:
S
1.
2.
3.
4.
5.
6.
7.
8.
SLAVE ADDRESS
W
A
DATA
A
P
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write) [80h]
Slave responds back with an ACK.
Wait for SCL to go HIGH
Host sends a command byte to Slave
Slave responds with an ACK
Wait for SCL to go HIGH
2
Host executes I C STOP
Command Byte
3. LOAD COMMAND BYTE REGISTER (ADDRESS LOAD): For the normal addressed mode the
Registers are loaded as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write)
Slave responds back with an ACK.
Wait for SCL to go HIGH
Host sends a byte to Slave - (Command Byte)
Slave responds with an ACK
Wait for SCL to go HIGH
Host sends a byte to Slave - (High Address Byte)
Slave responds with an ACK
Wait for SCL to go HIGH
Host sends a byte to Slave - (Low Address Byte)
Slave responds with an ACK
Wait for SCL to go HIGH
2
Host executes I C STOP
S
SLAVE ADDRESS
W
A
Command
October 2000
DATA
A
DATA
High Addr.
A
DATA
A
P
Low Addr.
Page 10
3.1.3
I2C Control Registers
The ISD5116 is controlled by loading commands to, or, reading from, the internal command, configuration
and address registers. The Command byte sent is used to start and stop recording, write or read digital
data and perform other functions necessary for the operation of the device.
3.2
COMMAND BYTE
Control of the ISD5116 is implemented through an 8-bit command byte, sent after the 7-bit device
address and the 1-bit Read/Write selection bit. The 8 bits are:
!
Global power up bit
!
DAB bit: determines whether device is performing an analog or digital function
!
3 function bits: these determine which function the device is to perform in conjunction with the DAB
bit.
!
3 register address bits: these determine if and when data is to be loaded to a register
Power Up
Bit
C7
PU
C6
DAB
C5
C4
FN2
FN1
Function Bits
C3
FN0
C2
C1
C0
RG2
RG1
RG0
Register Bits
Function Bits
The command byte function bits are
detailed in the table to the right. C6, the
DAB bit, determines whether the device is
performing an analog or digital function.
The other bits are decoded to produce the
individual commands. Not all decode
combinations are currently used, and are
reserved for future use. Out of 16 possible
codes, the ISD5116 uses 7 for normal
operation. The other 9 are undefined.
C6
DAB
0
0
0
0
1
1
1
Command Bits
C5
C4
FN2
FN1
0
0
1
0
0
1
1
1
1
0
0
0
0
1
Function
C3
FN0
0
1
0
1
0
1
0
STOP (or do nothing)
Analog Play
Analog Record
Analog MC
Digital Read
Digital Write
Erase (row)
Register Bits
The register load may be used to modify a command
sequence (such as load an address) or used with the null
command sequence to load a configuration or test register.
Not all registers are accessible to the user. [RG2 is always 0
as the four additional combinations are undefined.]
3.3
RG2
C2
0
0
0
0
RG1
C1
0
0
1
1
RG0
C0
0
1
0
1
Function
No action
Load Address
Load CFG0
Load CFG1
OPCODE SUMMARY
OpCode Command Description
2
The following commands are used to access the chip through the I C interface.
! Play: analog play command
! Record: analog record command
! Message Cue: analog message cue command
! Read: digital read command
! Write: digital write command
October 2000
Page 11
!
!
!
!
!
!
Erase: digital page and block erase command
Power up: global power up/down bit. (C7)
Load address: load address register (is incorporated in play, record, read and write commands)
Load CFG0: load configuration register 0
Load CFG1: load configuration register 1
Read STATUS: Read the interrupt status and address register, including a hardwired device ID
OPCODE COMMAND BYTE TABLE
OPCODE
HEX
Pwr
PU
Function Bits
DA
FN
FN
FN
B
2
1
0
C6
C5
C4
C3
Register Bits
RG
RG
RG
2
1
0
C2
C1
C0
COMMAND BIT NUMBER
CMD
C7
POWER UP
80
1
0
0
0
0
0
0
0
POWER DOWN
00
0
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY
ON
80
1
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY
OFF
00
0
0
0
0
0
0
0
0
LOAD ADDRESS
81
1
0
0
0
0
0
0
1
LOAD CFG0
82
1
0
0
0
0
0
1
0
LOAD CFG1
83
1
0
0
0
0
0
1
1
RECORD ANALOG
90
1
0
0
1
0
0
0
0
RECORD ANALOG @ ADDR
91
1
0
0
1
0
0
0
1
PLAY ANALOG
A8
1
0
1
0
1
0
0
0
PLAY ANALOG @ ADDR
A9
1
0
1
0
1
0
0
1
MSG CUE ANALOG
B8
1
0
1
1
1
0
0
0
MSG CUE ANALOG @ ADDR
B9
1
0
1
1
1
0
0
1
ERASE DIGITAL PAGE
D0
1
1
0
1
0
0
0
0
ERASE DIGITAL PAGE @
ADDR
D1
1
1
0
1
0
0
0
1
WRITE DIGITAL
C8
1
1
0
0
1
0
0
0
WRITE DIGITAL @ ADDR
C9
1
1
0
0
1
0
0
1
READ DIGITAL
E0
1
1
1
0
0
0
0
0
READ DIGITAL @ ADDR
E1
1
1
1
0
0
0
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
READ STATUS
1. See section 3.1.2 on page 9 for details.
October 2000
Page 12
3.4
DATA BYTES
2
In the I C write mode, the device can accept data sent after the command byte. If a register load option is
selected, the next two bytes are loaded into the selected register. The format of the data is MSB first, the
2
I C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is
acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes. The format of
the address is as follows:
ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0>
Note: if an analog function is selected, the block address bits must be set to 0000. Digital Read
and Write are block addressable.
When the device is polled with the Read Status command, it will return three bytes of data. The first byte
is the status byte, the next the upper address byte and the last the lower address byte. The status register
is one byte long and its bit function is:
STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0>
Lower address byte will always return the block address bits as zero, either in digital or analog mode.
The functions of the bits are:
EOM
OVF
READY
PD
PRB
DEVICE_ID
Indicates whether an EOM interrupt has occurred.
Indicates whether an overflow interrupt has occurred.
Indicates the internal status of the device – if READY is LOW no new commands
should be sent to device.
Device is powered down if PD is HIGH.
Play/Record mode indicator. HIGH=Play/LOW=Record.
An internal device ID. This is 001 for the ISD5116.
It is recommended that you read the status register after a Write or Record operation to ensure that the
device is ready to accept new commands. Depending upon the design and the number of pins available
on the controller, the polling overhead can be reduced. If INT and RAC are tied to the microcontroller, it
does not have to poll as frequently to determine the status of the ISD5116.
3.5
CONFIGURATION REGISTER BYTES
The configuration register bytes are defined, in detail, in the drawings of Section 4 on page 21. The
drawings display how each bit enables or disables a function of the audio paths in the ISD5116. The
tables below give a general illustration of the bits. There are two configuration registers, CFG0 and CFG1,
so there are four 8-bit bytes to be loaded during the set-up of the device.
October 2000
Page 13
Configuration Register 0 (CFG0)
D15 D14 D13 D12 D11 D10 D9
D8
D7 D 6 D5
D4
D3
D2
D1
D0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
Volume Control Power Down
SPKR & AUX OUT Control (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Power Down
AUXOUT MUX Select (3 bits)
INPUT SOURCE MUX Select (1 bit)
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Down
ANA IN AMP Gain SET (2 bits)
Configuration Register 1 (CFG1)
D15 D14 D13 D12 D11 D10 D9
D8
D7 D 6 D5
D4
D3
D2
D1
D0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
AGC AMP Power Down
Filter Power Down
SAMPLE RATE (& Filter) Set up (2 bits)
FILTER MUX Select
SUM 2 SUMMING AMP Control (2 bits)
SUM 1 SUMMING AMP Control (2 bits)
SUM 1 MUX Select (2 bits)
VOLUME CONTROL (3 bits)
VOLUME CONT. MUX Select (2 bits)
October 2000
Page 14
3.6
POWER-UP SEQUENCE
This sequence prepares the ISD5116 for an operation to follow, waiting the Tpud time before sending the
next command sequence.
1.
2.
3.
4.
5.
6.
7.
8.
3.6.1
2
Send I C POWER UP
Send one byte 10000000 {Slave Address, R/W = 0} 80h
Slave ACK
Wait for SCL High
Send one byte 10000000 {Command Byte = Power Up} 80h
Slave ACK
Wait for SCL High
2
Send I C STOP
Playback Mode
The command sequence for an analog Playback operation can be handled several ways. One technique
would be to do a Load Address (81h), which requires sending a total of four bytes, and then sending a
Play Analog, which would be a Command Byte (A8h) proceeded by the Slave Address Byte. This is a
total of six bytes plus the times for Start, ACK, and Stop.
Another approach would be to incorporate both into a single four byte exchange, which consists of the
Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address bytes.
3.6.2
Record Mode
The command sequence for an Analog Record would be a four byte sequence consisting of the Slave
Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. See
“Load Command Byte Register (Address Load)” in section 3.1.2 on page 10.
3.7
FEED THROUGH MODE
The previous examples were dependent upon the device already being powered up and the various paths
being set through the device for the desired operation. To set up the device for the various paths requires
loading the two 16-bit Configuration Registers with the correct data. For example, in the Feed Through
Mode the device only needs to be powered up and a few paths selected.
This mode enables the ISD5116 to connect to a cellular or cordless base band phone chip set without
affecting the audio source or destination. There are two paths involved, the transmit path and the receive
path. The transmit path connects the ISD chip’s microphone source through to the microphone input on
the base band chip set. The receive path connects the base band chip set’s speaker output through to the
speaker driver on the ISD chip. This allows the ISD chip to substitute for those functions and incidentally
gain access to the audio to and from the base band chip set.
To set up the environment described above, a series of commands need to be sent to the ISD5116. First,
the chip needs to be powered up as described in this section. Then the Configuration Registers must be
filled with the specific data to connect the paths desired. In the case of the Feed Through Mode, most of
the chip can remain powered down. The following figure illustrates the affected paths.
October 2000
Page 15
The figure above shows the part of the ISD5116 block diagram that is used in Feed Through Mode. The
rest of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note
that the Microphone to ANA OUT +/– path is differential.
To select this mode, the following control bits must be configured in the ISD5116 configuration registers.
To set up the transmit path:
1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the
state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration
Register 0 (CFG0) and they should all be ZERO to select the FTHRU path.
2. Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT. This is bit
D5 of CFG0 and it should be a ZERO to power up the amplifier.
To set up the receive path:
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings of
this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin determines the setting of this gain stage. The ANA IN Amplifier Gain Settings table on page 25 will
help determine this setting. In this example, we will assume that the peak signal never goes
above 1 volt p-p single ended. That would enable us to use the 9 dB attenuation setting, or where
D14 is ONE and D15 is ZERO.
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit D13
of CFG0 and should be a ZERO to power up the amplifier.
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of the
OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to the
state where D3 is ONE and D4 is ZERO to select the ANA IN path.
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and AUX
amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the state where
D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for its higher
gain setting for use with a piezo speaker element and also powers down the AUX output stage.
The status of the rest of the functions in the ISD5116 chip must be defined before the configuration
registers settings are updated:
October 2000
Page 16
1.
2.
3.
4.
5.
6.
Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM1
mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down
these two amplifiers.
Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage in
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0,
bit D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and
D12 respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and
FLD1 are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band
pass setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and
S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and
VOL2 are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control.
(g). Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two
registers must be loaded in this order. The internal set up for both registers will take effect synchronously
with the rising edge of SCL.
3.8
CALL RECORD
The call record mode adds the ability to record an incoming phone call. In most applications, the
ISD5116 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5116 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE FILTER
MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed Through
Mode has already powered up the ANA IN amp so we only need to power up and enable the path to the
Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the state
where both D9 and D10 are ZERO to select the ANA IN path.
October 2000
Page 17
2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1 control
the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of CFG1 and
they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only)
path.
3. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path.
4. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
5. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO.
6. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the
chip not required to add the record path remain powered down. In fact, CFG0 does not change and
remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it
would be necessary to load both registers.
3.9
MEMO RECORD
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down and
is not active in this mode. The path to be used is microphone input to AGC amplifier, then through the
INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the FILTER
MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL STORAGE
ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may be powered
down.
1. Power up the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier. This is
bit D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of the
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier.
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT
SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1
SUMMING amplifier path.
October 2000
Page 18
5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
3.10 MEMO AND CALL PLAYBACK
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From
there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo
speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered
down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the state
of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL
STORAGE ARRAY.
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They
should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING
amplifier.
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to
power-up the VOLUME CONTROL.
7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1, and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary
count of 000 through 111 controls the amount of attenuation through that state. In most cases,
the software will select an attenuation level according to the desires of the current users of the
October 2000
Page 19
product. In this example, we will assume the user wants an attenuation of –12 dB. For that
setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO.
8. Select the VOLUME CONTROL path through the OUTPUT MUX—These are bits D3 and D4,
respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to
select the VOLUME CONTROL.
9. Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and OPA1
control the state of the speaker (SP+ and SP–) and AUX OUT outputs. These are bits D1 and D2
of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the
speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0010 (hex 2422).
CFG1=0101 1001 1101 0001 (hex 59D1).
Only those portions necessary for this mode are powered up.
3.11 MESSAGE CUEING
Message cueing allows the user to skip through analog messages without knowing the actual physical
location of the message. This operation is used during playback. In this mode, the messages are skipped
512 times faster than in normal playback mode. It will stop when an EOM marker is reached. Then, the
internal address counter will be pointing to the next message.
October 2000
Page 20
4 ANALOG MODE
4.1
AUX IN AND ANA IN DESCRIPTION
The AUX IN is an additional audio input to the ISD5116, such as from the microphone circuit in a mobile
phone “car kit.” This input has a nominal 700 mV p-p level at its minimum gain setting (0 dB). See the
AUX IN Amplifier Gain Settings table on page 26. Additional gain is available in 3 dB steps (controlled
2
by the I C serial interface) up to 9 dB.
Internal to the device
Rb
CCOUP=0.1 µF
Ra
AUX IN
Input
AUX IN
Input Amplifier
NOTE: fCUTOFF=
1
2πRaCCOUP
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the serial bus) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1.11 Vp-p when at its minimum gain (6 dB) setting. See the ANA IN Amplifier Gain Settings table on
2
page 25. There is additional gain available in 3 dB steps controlled from the I C interface, if required, up
to 15 dB.
Internal to the device
Rb
CCOUP=0.1 µF
Ra
ANA IN
Input
ANA IN
Input Amplifier
NOTE: fCUTOFF=
October 2000
1
2πRaCCOUP
Page 21
4.2
ISD5116 ANALOG STRUCTURE (LEFT HALF) DESCRIPTION
INP
SUM1 SUMMING
AMP
INPUT
SOURCE
MUX
AGC AMP
Σ
SUM1
AUX IN AMP
2 (S1M1,S1M0)
(INS0) SUM1
MUX
FILTO
S1M1
0
0
1
1
ANA IN AMP
S1M0
0
1
0
1
SOURCE
BOTH
SUM1 MUX ONLY
INP Only
Power Down
ARRAY
Inso
0
1
4.3
Source
AGC AMP
AUX IN AMP
S1S1
0
0
1
1
2 (S1S1,S1S0)
15
14
13
AIG1
AIG0
AIPD
12
11
15
14
13
VLS1
VLS0
V OL2 VOL1
AXG1 AXG0
12
11
V OL0
10
AXPD
10
S1S1
9
8
INS0
AOS2
7
9
8
S1S0
S1M1
6
S1S0
0
1
0
1
5
AOS1 AOS0 AOPD
7
6
4
3
2
OPS1
OPS0
OPA1
4
3
2
1
0
FLS0
FLD1
FLD0
FLPD
AGPD
5
S1M0 S2M1 S2M0
SOURCE
ANA IN
ARRAY
FILTO
N/C
1
0
OPA0 V LPD
CFG 0
CFG 1
ISD5116 ANALOG STRUCTURE (RIGHT HALF) DESCRIPTION
FILTER
FILTER
MUX
FILTO
FILTO
SUM2 SUMMING
AMP
MUX
SUM1
Σ
LOW PASS
FILTER
ARRAY
FLS0
0
1
FLPD
0
1
SOURCE
SUM1
ARRAY
1
1
(FLS0) (FLPD)
CONDITION
Power Up
Power Down
FLD0
0
0
1
1
0
1
0
1
2 (S2M1,S2M0)
S1M1
0
0
1
1
S1M0
0
1
0
1
SOURCE
BOTH
ANA IN ONLY
FILTO ONLY
Power Down
ANA IN AMP
SAMPLE
RATE
8 KHz
6.4 KHz
5.3 KHz
4.0 KHz
MULTILEVEL
STORAGE
ARRAY
INTERNAL
CLOCK
XCLK
FLD1
SUM2
FILTER
BANDWIDTH
3.6 KHz
2.9 KHz
2.4 KHz
1.8 KHz
2
(FLD1,FLD0)
ARRAY
15
14
VLS1
VLS0
October 2000
13
VOL2
12
11
VOL1 VOL0
10
9
S1S1
S1S0
8
7
6
S1M1 S1M0 S2M1
5
4
3
2
S2M0
FLS0
FLD1
FLD0
1
0
FLPD AGPD
CFG1
Page 22
4.4
VOLUME CONTROL DESCRIPTION
VOL
MUX
ANA IN AMP
SUM2
SUM1
VOLUME
CONTROL
VOL
INP
VLS1 VLS0 SOURCE
0
0
ANA IN AMP
0
1
SUM2
1
0
SUM1
1
1
INP
4.5
AIG1
AIG0 AIP D
15
14
VLS1
VLS0
AXG1 AXG0 AX PD
13
VOL2
12
11
VOL1 VOL0
VLPD
0
1
3
1 (VLPD)
( VOL2,VOL1,VOL0)
2
(VLS1,VLS0)
INS0
AOS2
9
8
S1S0
S1M1
10
S1 S1
VOL2
0
0
0
0
1
1
1
1
VOL1
0
0
1
1
0
0
1
1
AOS1 AOS0
7
VOL0
0
1
0
1
0
1
0
1
ATTENUATION
0 dB
4 dB
8 dB
12 dB
16 dB
20 dB
24 dB
28 dB
AOPD OPS1 OPS0
6
S1 M0 S2M1
CONDITION
Power Up
Power Down
OPA1 OPA0 VLPD
5
4
3
2
1
0
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG0
CFG1
SPEAKER AND AUX OUT DESCRIPTION
Car Kit
AUX OUT (1 Vp-p Max)
OUTPUT
MUX
VOL
ANA IN AMP
Speaker
SP+
FILTO
SP–
2
( OPA1, OPA0)
SUM2
2
( OPS1,OPS0)
OPS1
0
0
1
1
15
14
AIG1
AIG0 AIP D
October 2000
13
12
11
OPS0
0
1
0
1
10
9
AXG1 AXG0 AXPD INS0
OPA1
0
0
1
1
SOURCE
VOL
ANA IN
FILTO
SUM2
8
AOS2
7
6
AOS1 AOS0
5
OPA0
0
1
0
1
4
3
AOPD OPS1 OPS0
SPKR DRIVE
Power Down
3.6 VP-P @ 150 Ω
23.5 mWatt @ 8 Ω
Power Down
2
1
AUX OUT
Power Down
Power Down
Power Down
1 VP-P Max @ 5 KΩ
0
OPA1 OPA0 VLPD
CFG0
Page 23
4.6
ANA OUT DESCRIPTION
*FTHRU
(1 Vp-p max. from AUX IN or ARRAY)
(694 mV p-p max. from mi crophone input)
*INP
*VOL
Chip Set
ANA OUT+
*FILTO
ANA OUT–
*SUM1
1
(AOPD)
*SUM2
AOPD
0
1
3 (AOS2,AOS1,AOS0)
AOS2
0
0
0
0
1
1
1
1
*DIFFERENTIAL PATH
4.7
4.7.1
15
14
13
AI G1
AI G0
AIPD
12
11
10
AXG1 AXG0 AXPD
AOS1
0
0
1
1
0
0
1
1
9
8
I NS0
AOS0
0
1
0
1
0
1
0
1
7
SOURCE
FTHRU
INP
VOL
FILTO
SUM1
SUM2
N/C
N/C
6
AOS2 AOS1
5
AOS0 AOPD
4
OPS1
3
2
OPS0 OPA1
1
CONDITION
Power Up
Power Down
0
OPA0 VLPD
CFG0
ANALOG INPUTS
Microphone Inputs
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB so
a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA
OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage
array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is typically 10kΩ.
The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC
circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because
the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount
of noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; to VCCA
gives minimum gain for the AGC amplifier but will cancel the AutoMute function.
*
FTHRU
6 dB
AGPD
0
1
MIC+
AGCIN
MIC
AGC
CONDITION
Power Up
Power Down
MIC–
1 ( AGPD)
To AutoMute
ACAP
(Pl ayback Only)
* Diffe re ntial Path
15
14
VLS1
VLS0
October 2000
13
12
11
VOL2
VOL1
VOL0
10
S1S1
9
8
S1S0
S1M1
7
6
5
S1M0 S2M1 S2M0
4
3
2
1
0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG1
Page 24
ANA IN (Analog Input)
2
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I C interface) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if required, in 3 dB
2
steps, up to 15 dB. The gain settings are controlled from the I C interface.
ANA IN Input Modes
Gain
Setting
00
01
10
11
Resistor Ratio
(Rb/Ra)
63.9 / 102
77.9 / 88.1
92.3 / 73.8
106 / 60
Gain
0.625
0.883
1.250
1.767
2
Gain
(dB)
-4.1
-1.1
1.9
4.9
ANA IN Amplifier Gain Settings
(1)
Setting
6 dB
9 dB
12 dB
15 dB
0TLP Input
(3)
VP-P
1.110
0.785
0.555
0.393
(2)
CFG0
AIG1
0
0
1
1
Gain
AIG0
0
1
0
1
Array
In/Out VP-P
Speaker
(4)
Out VP-P
0.694
0.694
0.694
0.694
2.22
2.22
2.22
2.22
0.625
0.883
1.250
1.767
1. Gain from ANA IN to SP+/2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing.
This level is typically 3 dB below clipping
4. Speaker Out gain set to 1.6 (High). (Differential)
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the ISD5116, such as from the microphone circuit in a mobile phone
“car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the following table.
2
Additional gain is available in 3 dB steps (controlled by the I C interface) up to 9 dB.
October 2000
Page 25
AUX IN Input Modes
Gain
Setting
00
01
10
11
Resistor Ratio
(Rb/Ra)
40.1 / 40.1
47.0 / 33.2
53.5 / 26.7
59.2 / 21
Gain
1.0
1.414
2.0
2.82
(2)
Gain
(dB)
0
3
6
9
AUX IN Amplifier Gain Settings
(1)
Setting
0 dB
3 dB
6 dB
9 dB
1.
2.
3.
4.
0TLP Input
(3)
VP-P
0.694
0.491
0.347
0.245
(2)
Gain
CFG0
AIG1
0
0
1
1
AIG0
0
1
0
1
1.00
1.41
2.00
2.82
Array
In/Out VP-P
0.694
0.694
0.694
0.694
Speaker
(4)
Out VP-P
0.694
0.694
0.694
0.694
Gain from AUX IN to ANA OUT
Gain from AUX IN to ARRAY IN
0TLP Input is the reference Transmission Level Point that is used for testing. This level is
typically 3 dB below clipping
Differential
October 2000
Page 26
5 DIGITAL MODE
5.1
WRITING DATA
The Digital Write function allows the user to select a portion of the array to be used as digital
memory. The partition between analog and digital memory is left up to the user. A page can
only be either Digital or Analog, not both. The minimum addressable block of memory in the
digital mode is one block or 64 bits, when reading or writing. The address sent to the device
is the 11-bit row (or page) address with the 5-bit scan (or block) address. However, one must
send a Digital Erase before attempting to change digital data on a page. This means that
even when changing only one of the 32 blocks, all 32 will need to be rewritten to the page.
After the address is entered, the data is sent in one-byte packets followed by an I2C
acknowledge generated by the chip. Data for each block is sent MSB first. The data transfer
2
is ended when the master generates an I C STOP condition. If only a partial block of data is
sent before the STOP condition, zero is “written” in the remaining bytes; that is, they are left at
the erase level. An erased page (row) will be read as all zeros. The device can buffer up to
two blocks of data. If the device is unable to accept more data due to the internal write
process, the SCL line will be held LOW indicating to the master to halt data transfer. If the
device encounters an overflow condition, it will respond by generating an interrupt condition
and an I2C Not Acknowledge signal after the last valid byte of data. Once data transfer is
terminated, the device needs up to two cycles (64 us) to complete its internal write cycle
before another command is sent. If an active command is sent before the internal cycle is
finished, the part will hold SCL LOW until the current command is finished.
5.2
READING DATA
2
The Digital Read command utilizes the combined I C command format. That is, a command is
sent to the chip using the write data direction. Then the data direction is reversed by sending
a repeated start condition, and the slave address with R/W set to 1. After this, the slave
device (ISD5116) begins to send data to the master until the master generates a Not
Acknowledge. If the part encounters an overflow condition, the INT pin is pulled LOW. No
other communication with the master is possible due to the master generating ACK signals.
As with Digital Write, Digital Read can be done a “block” at a time. Thus, only 64 bits need be
read in each Digital Read command sequence.
5.3
ERASING DATA
The Digital Erase command can only erase an entire page at a time. This means that only the
D1 command needs to include the 11-bit page address; the 5-bit for block address are left at
00000.
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if
a block has been previously written then the entire page of 2048 bits must be erased in order
to re-write (or change) a block.
A sequence might be look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page
Page 27
5.4
EXAMPLE COMMAND SEQUENCES
An explanation and graphical representation of the Write, Read and Erase operations are
found below.
1. Write digital data
For the normal digital addressed mode the Registers are loaded as follows:
SLAVE ADDRESS
W
A
C9h
A
Command Byte
DATA
A
High Addr. Byte
DATA
A
Low Addr. Byte
~
~
S
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write)
Slave responds back with an ACK.
Wait for SCL HIGH
Host sends a byte to Slave - (Command Byte = C9h)
Slave responds with an ACK
Wait for SCL HIGH
Host sends a byte to Slave - (High Address Byte)
Slave responds with an ACK
Wait for SCL HIGH
Host sends a byte to Slave - (Low Address Byte)
Slave responds with an ACK
Wait for SCL HIGH
Host sends a byte to Slave - (First 8 bits of digital information)
Slave responds with an ACK
Wait for SCL HIGH
Steps 14, 15 and 16 are repeated until last byte is sent and acknowledged
2
Host executes I C STOP
DATA
A
DATA
A
DATA
A
P
~
~
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Page 28
2. Read digital data
For a normal digital read, the Registers are loaded as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
SLAVE ADDRESS
W
A
C9h
DATA
A
High Addr. Byte
DATA
A
Low Addr. Byte
~
~
Command Byte
A
S
SLAVE ADDRESS
R
A
DATA
A
DATA
A
DATA
N
P
~
~
S
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write)
Slave responds back with an ACK
Wait for SCL HIGH
Host sends a byte to Slave - (Command Byte = E1)
Slave responds with an ACK
Wait for SCL HIGH
Host sends a byte to Slave - (High Address Byte)
Slave responds with an ACK.
Wait for SCL HIGH
Host sends a byte to Slave - (Low Address Byte)
Slave responds with an ACK
Wait for SCL HIGH
Host sends repeat START
Host sends Slave Address with R/W bit = 1 (Reverses Data Direction)
Slave responds with an ACK
Wait for SCL HIGH
Slave sends a byte to Host - (First 8 bits of digital information)
Host responds with an ACK
Wait for SCL HIGH
Steps 18, 19 and 20 are repeated until last byte is sent and a NO ACK is returned
2
Host executes I C STOP
October 2000
Page 29
3. Erase digital data
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write)
Slave responds back with an ACK
Wait for SCL to go HIGH
Host sends a byte to Slave - (Command Byte = D1)
Slave responds with an ACK
Wait for SCL to go HIGH
Host sends a byte to Slave - (High Address Byte)
Slave responds with an ACK.
Wait for SCL to go HIGH
Host sends a byte to Slave - (Low Address Byte)
Slave responds with an ACK
Wait for SCL to go HIGH
2
Host executes I C STOP
Host counts RAC cycles to track where the chip is in the erase operation.
Host determines erase of final row has begun
2
Host executes I C START
Send Slave Address with R/W bit = “0” (Write)
Slave responds back with an ACK
Wait for SCL to go HIGH
Host sends a byte to Slave - (Command Byte = 80)
Slave responds back with an ACK
Wait for SCL to go HIGH
2
Host executes I C STOP
Erase starts on falling
edge of Slave
acknowledge
S
SLAVE ADDRESS
W
A
D1h
Command Byte
"N" RAC cycles
Last erased row
Note 3.
Note 4.
A
DATA
A
High Addr. Byte
S
DATA
A
P
Note 2
Low Addr. Byte
SLAVE ADDRESS
W
A
80h
A
P
Command Byte
Notes
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low
Address Byte will be ignored.
2. I2C bus is released while erase proceeds. Other devices may use the bus until it is
time to execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end
of each erased row. The erase of the "next" row begins with the rising edge of RAC.
See the Digital Erase RAC timing diagram on page 32.
4. When the erase of the last desired row begins, the following STOP command
(Command Byte = 80 hex) must be issued. This command must be completely given,
including receiving the ACK from the Slave before the RAC pin goes HIGH .25
microseconds before the end of the row.
Page 30
6 PIN DESCRIPTIONS
6.1
DIGITAL I/O PINS
SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to
Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over the
Serial Data Line.
SDA (Serial Data Line)
2
The Serial Data Line carries the data between devices on the I C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bidirectional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency, the
duration of this period is 256 ms. There are 2048 pages of memory in the ISD5116 devices. RAC stays
HIGH for 248 ms and stays LOW for the remaining 8 ms before it reaches the end of the page.
1 R OW
RAC W aveform
During 8 KHz Operation
2 5 6 m se c
T R AC
8 m se c
T R AC LO
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing mode.
See the Timing Parameters table on page 39 for RAC timing information at other sample rates. When a
record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period, to load sample
and hold circuits internal to the device. The RAC pin can be used for message management techniques.
1 RO W
RAC W aveform
During M essage Cueing
5 0 0 use c
T R AC
October 2000
1 5 .6 us
T R A C LO
Page 31
RAC Waveform During Digital Erase
1.25 µsec
.25 µsec
Sample Rate
tRAC
tRACL0
tRACL1
4.0 kHz
2.5µs
0.5µs
2.0µs
5.3 kHz
1.87µs
0.37µs
1.50µs
6.4 kHz
1.56µs
0.31µs
1.25µs
8.0 kHz
1.25µs
0.25µs
1.00µs
INT (Interrupt)
INT is an open drain output pin. The ISD5116 interrupt pin goes LOW and stays LOW when an Overflow
(OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF
generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
The external clock input for the ISD5116 product has an internal pull-down device. Normally, the ISD5116
is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If
greater precision is required, the device can be clocked through the XCLK pin at 4.096 MHz as described
in Section 4.3 on page 22.
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for optimum
performance, maintain the external clock at 4.096 MHz AND set the Sample Rate Configuration bits to
one of the four values to properly set the filters to the correct cutoff frequency as described in Section 4.3
on page 22. The duty cycle on the input clock is not critical, as the clock is immediately divided by two
internally. If the XCLK is not used, this input should be connected to VSSD.
External Clock Input Table
Duration
(Minutes)
8.73
10.9
13.1
17.5
Sample Rate
(kHz)
8.0
6.4
5.3
4.0
Required Clock
(kHz)
4096
4096
4096
4096
FLD1
FLD0
Filter Knee (kHz)
0
0
1
1
0
1
0
1
3.4
2.7
2.3
1.7
A0, A1 (Address Pins)
2
These two pins are normally strapped for the desired address that the ISD5116 will have on the I C serial
interface. If there are four of these devices on the bus, then each must be strapped differently in order to
allow the Master device to address them individually. The possible addresses range from 80h to 87h,
depending upon whether the device is being written to, or read from, by the host. The ISD5116 has a 7bit slave address of which only A0 and A1 are pin programmable. The eighth bit (LSB) is the R/W bit.
Thus, the address will be 1000 0xy0 or 1000 0xy1. (See the table in section 3.1.1 on page 9.)
October 2000
Page 32
6.2
ANALOG I/O PINS
MIC+, MIC- (Microphone Input +/-)
The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB so
a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA
OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage
array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is typically 10 kΩ.
VCC
1.5kΩ
Internal to the device
MIC+
220 µF
+
1.5kΩ
CCOUP=0.1 µF
Electret
Microphone
WM-54B
Panasonic
0.1 µF
1.5kΩ
MIC-
6 dB
FTHRU
AGC
MIC IN
Ra=10kΩ
10kΩ
NOTE: fCUTOFF=
1
2πRaCCOUP
ANA OUT+, ANA OUT- (Analog Output +/-)
This differential output is designed to go to the microphone input of the telephone chip set. It is designed
to drive a minimum of 5 kΩ between the “+” and “–” pins to a nominal voltage level of 700 mV p-p. Both
pins have DC bias of approximately 1.2 VDC. The AC signal is superimposed upon this analog ground
voltage. These pins can be used single-ended, getting only half the voltage. Do NOT ground the unused
pin.
ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the
capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of
noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; tying it to
VCCA gives minimum gain for the AGC amplifier but cancels the AutoMute function.
SP +, SP- (Speaker +/-)
This is the speaker differential output circuit. It is designed to drive an 8Ω speaker connected across the
speaker pins up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32 and
1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2
VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused
pin.
October 2000
Page 33
AUX OUT (Auxiliary Output)
The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in a
“car kit.” It drives a minimum load of 5 kΩ and up to a maximum of 1 V p-p. The AC signal is
superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load.
Car Kit
AUX OUT (1 Vp-p Max)
OUTPUT
MUX
VOL
ANA IN AMP
Speaker
SP+
FILTO
SP–
2
(OPA1, OPA0)
SUM2
2
(OPS1,OPS0)
OPS1
0
0
1
1
OPS0
0
1
0
1
15
14
AIG1
AIG0 AIPD
13
SOURCE
VOL
ANA IN
FILTO
SUM2
12
11
10
OPS1
0
0
1
1
9
AXG1 AXG0 AXPD INS0
8
7
6
5
4
3
AOS2 AOS1 AOS 0 AOPD OPS1 OPS0
OPA0
0
1
0
1
2
1
SPKR DRIVE
Power Down
3.6 Vp.p @150Ω
23.5 mWatt @ 8Ω
Power Down
AUX OUT
Power Down
Power Down
Power Down
1 Vp.p Max @ 5KΩ
0
OPA1 OPA0 VLPD
CFG0
ANA IN (Analog Input)
2
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I C interface) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if required, in 3 dB
2
steps, up to 15 dB. The gain settings are controlled from the I C interface.
ANA IN Input Modes
Gain
Setting
00
01
10
11
October 2000
Resistor Ratio
(Rb/Ra)
63.9 / 102
77.9 / 88.1
92.3 / 73.8
106 / 60
Gain
0.625
0.88
1.25
1.77
2
Gain
(dB)
-4.1
-1.1
1.9
4.9
Page 34
ANA IN Amplifier Gain Settings
(1)
Setting
6 dB
9 dB
12 dB
15 dB
1.
2.
3.
4.
0TLP Input
(3)
VP-P
1.110
0.785
0.555
0.393
(2)
Gain
CFG0
AIG1
0
0
1
1
AIG0
0
1
0
1
0.625
0.883
1.250
1.767
Array
In/Out VP-P
0.694
0.694
0.694
0.694
Speaker
(4)
Out VP-P
2.22
2.22
2.22
2.22
Gain from ANA IN to SP+/Gain from ANA IN to ARRAY IN
0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping
Speaker Out gain set to 1.6 (High). (Differential)
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the ISD5116, such as from the microphone circuit in a mobile
phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the
AUX IN Amplifier Gain Settings table on page 26. Additional gain is available in 3 dB steps (controlled
2
by the I C interface) up to 9 dB.
AUX IN Input Modes
Gain
Setting
00
01
10
11
Resistor Ratio
(Rb/Ra)
40.1 / 40.1
47.0 / 33.2
53.5 / 26.7
59.2 / 21
Gain
1.0
1.414
2.0
2.82
(2)
Gain
(dB)
0
3
6
9
AUX IN Amplifier Gain Settings
(1)
Setting
0 dB
3 dB
6 dB
9 dB
0TLP Input
(3)
VP-P
0.694
0.491
0.347
0.245
(2)
Gain
CFG0
AIG1
0
0
1
1
AIG0
0
1
0
1
1.00
1.41
2.00
2.82
Array
In/Out VP-P
0.694
0.694
0.694
0.694
Speaker
(4)
Out VP-P
0.694
0.694
0.694
0.694
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping
4. Differential
October 2000
Page 35
6.3
POWER AND GROUND PINS
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the ISD5116 device use separate power busses.
These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible and decouple
both supplies as near to the package as possible.
VSSA, VSSD (Ground Inputs)
The ISD5116 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins
should be tied together as close to the package as possible and connected through a low-impedance
path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low
impedance path to power supply ground. These ground paths should be large enough to ensure that the
impedance between the VSSA pins and the VSSD pin is less than 3Ω. The backside of the die is connected
to VSSD through the substrate resistance. In a chip-on-board design, the die attach area must be connected to VSSD.
NC (Not Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or VCC, may result in incorrect device behavior or cause damage to the device.
6.4
SAMPLE PC LAYOUT
The SOIC package is illustrated from the top. PC board traces and the three chip capacitors are on the
bottom side of the board.
1
Note 3
Note
V
S
S
D
(Digital Ground)
1
Note 1: VSSD traces should be kept
separated back to the VSS supply feed
point..
Note 2: VCCD traces should be kept
separate back to the VCC Supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
VCCA and VCCD supplies will also need
filter capacitors per good engineering
practice (typ. 50 to 100 uF).
October 2000
Note 2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
C1
C2
C3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Analog Ground
V
C
C
D
XCLK
VSSA
C1=C2=C3=0.1 uF chip Capacitors
To
VCCA
Note 3
Page 36
7 ELECTRICAL CHARACTERISTICS AND PARAMETERS
7.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Packaged Parts)(1)
Condition
Value
0
Junction temperature
150 C
Storage temperature range
-65 C to +150 C
Voltage Applied to any pin
(VSS - 0.3V) to (VCC + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Lead temperature (soldering – 10 seconds)
300 C
VCC - VSS
-0.3V to +5.5V
0
0
0
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
Absolute Maximum Ratings (Die)(1)
Condition
Value
0
Junction temperature
150 C
Storage temperature range
-65 C to +150 C
Voltage Applied to any pad
(VSS - 0.3V) to (VCC + 0.3V)
VCC - VSS
-0.3V to +5.5V
0
0
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
Operating Conditions (Packaged Parts)
Condition
(1)
Commercial operating temperature range
-20 C to +70 C
(1)
-40 C to +85 C
Industrial operating temperature
(2)
Ground voltage (VSS)
0
0
0
0
+2.7V to +3.3V
(3)
1. Case temperature
0
0 C to +70 C
(1)
Extended operating temperature
Supply voltage (VCC)
0
Value
0V
2. VCC = VCCA = VCCD
3. VSS = VSSA = VSSD
Operating Conditions (Die)
Condition
(1)
Die operating temperature range
Supply voltage (VCC)
(2)
Ground voltage (VSS)
1. Case temperature
October 2000
Value
0
0
0 C to +50 C
+2.7V to +3.3V
(3)
0V
2. VCC = VCCA = VCCD
3. VSS = VSSA = VSSD
Page 37
7.2
PARAMETERS
General Parameters
Min(2)
Typ(1)
Max(2)
Units
VCC x 0.2
V
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
SCL, SDA Output Low Voltage
0.4
V
IOL = 3 mA
VIL2V
Input low voltage for 2V
interface
0.4
V
Apply only to SCL,
SDA
VIH2V
Input high voltage for 2V
interface
V
Apply only to SCL,
SDA
VOL1
RAC, INT Output Low Voltage
V
IOL = 1 mA
VOH
Output High Voltage
V
IOL = -10 µA
ICC
VCC Current (Operating)
VCC x 0.8
Conditions
V
1.6
0.4
VCC – 0.4
(3)
- Playback
- Record
- Feedthrough
15
30
12
25
40
15
mA
mA
mA
No Load
(3)
No Load
(3)
No Load
ISB
VCC Current (Standby)
1
10
µA
(3)
IIL
Input Leakage Current
+/-1
µA
1.
Typical values: TA = 25°C and Vcc = 3.0 V.
2.
All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are
100 percent tested.
3.
VCCA and VCCD summed together.
October 2000
Page 38
Timing Parameters
Symbol
Parameters
FS
Sampling Frequency
FCF
TREC
TPLAY
TPUD
TSTOP OR PAUSE
TRAC
TRACLO
TRACM
October 2000
Min(2)
Typ(1)
Max(2)
Units
Conditions
8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
(5)
(5)
(5)
(5)
Filter Knee
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
Knee Point
(3)(7)
Knee Point
(3)(7)
Knee Point
(3)(7)
Knee Point
Record Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8.73
10.9
13.1
17.5
min
min
min
min
(6)
(6)
(6)
(6)
Playback Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8.73
10.9
13.1
17.5
min
min
min
min
(6)
(6)
(6)
(6)
Power-Up Delay
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1
1
1
1
msec
msec
msec
msec
Stop or Pause
Record or Play
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
32
40
48
64
msec
msec
msec
msec
RAC Clock Period
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
256
320
384
512
msec
msec
msec
msec
RAC Clock Low Time
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8
10
12.1
16
msec
msec
msec
msec
RAC Clock Period in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
500
625
750
1000
µsec
µsec
µsec
µsec
(3)(7)
(9)
(9)
(9)
(9)
Page 39
TRACE
TRACML
THD
RAC Clock Period in
Erase Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1.25
1.56
1.87
2.50
msec
msec
msec
msec
RAC Clock Low Time in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
15.6
19.5
23.4
31.2
µsec
µsec
µsec
µsec
Total Harmonic Distortion
ANA IN to ARRAY,
ARRAY to SPKR
1
1
2
2
@1 KHz at 0TLP,
sample rate = 5.3 KHz
%
%
Analog Parameters
MICROPHONE INPUT(14)
Symbol
Parameters
VMIC+/-
MIC +/- Input Voltage
VMIC (0TLP)
MIC +/- input reference
transmission level point
(0TLP)
AMIC
Gain from MIC +/- input to
ANA OUT
AMIC (GT)
MIC +/- Gain Tracking
RMIC
Microphone input resistance
AAGC
Microphone AGC Amplifier
Range
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
300
mV
Peak-to-Peak
mV
Peak-to-Peak
dB
1 kHz at VMIC (0TLP)
+/-0.1
dB
1 kHz, +3 to –40 dB
0TLP Input
10
kΩ
MIC- and MIC+ pins
40
dB
Over 3-300 mV Range
Max(2)
Units
1.6
V
Peak-to-Peak (6 dB gain
setting)
1.1
V
Peak-to-Peak (6 dB gain
(10)
setting)
208
5.5
6.0
6
6.5
(4)(8)
(4)(10)
(4)
ANA IN(14)
Min(2)
Typ(1)(14)
Symbol
Parameters
VANA IN
ANA IN Input Voltage
VANA IN (0TLP)
ANA IN (0TLP) Input Voltage
AANA IN (sp)
Gain from ANA IN to SP+/-
+6 to +15
dB
4 Steps of 3 dB
AANA IN (AUX OUT)
Gain from ANA IN to AUX
OUT
-4 to +5
dB
4 Steps of 3 dB
AANA IN (GA)
ANA IN Gain Accuracy
dB
(11)
AANA IN (GT)
ANA IN Gain Tracking
+/-0.1
dB
1000 Hz, +3 to –45 dB
0TLP Input,
6 dB setting
RANA IN
ANA IN Input Resistance (6
dB to +15 dB)
10 to 100
kΩ
Depending on ANA IN
Gain
October 2000
-0.5
+0.5
Conditions
Page 40
AUX IN
(14)
Symbol
Parameters
VAUX IN
AUX IN Input Voltage
VAUX IN (0TLP)
AUX IN (0TLP) Input Voltage
AAUX IN (ANA OUT)
Gain from AUX IN to ANA
OUT
AAUX IN (GA)
AUX IN Gain Accuracy
AAUX IN (GT)
AUX IN Gain Tracking
RAUX IN
AUX IN Input Resistance
Min
(2)
Typ
(1)(14)
(2)
Max
1.0
Units
Conditions
V
Peak-to-Peak (0 dB gain
setting)
694.2
mV
Peak-to-Peak (0 dB gain
setting)
0 to +9
dB
4 Steps of 3 dB
dB
(11)
+/-0.1
dB
1000 Hz, +3 to –45 dB
0TLP Input, 0 dB setting
10 to 100
kΩ
Depending on AUX IN
Gain
-0.5
+0.5
(14)
SPEAKER OUTPUTS
Parameters
VSPHG
SP+/- Output Voltage (High
Gain Setting)
RSPLG
SP+/- Output Load Imp. (Low
Gain)
8
RSPHG
SP+/- Output Load Imp. (High
Gain)
70
CSP
SP+/- Output Load Cap.
VSPAG
SP+/- Output Bias Voltage
(Analog Ground)
VSPDCO
Speaker Output DC Offset
ICNANA IN/(SP+/-)
CRT(SP+/-)/ANA
OUT
Min
(2)
Symbol
Typ
(1)(14)
(2)
Max
3.6
150
100
1.2
Units
Conditions
V
Peak-to-Peak, differential
load = 150Ω, OPA1,
OPA0 = 01
Ω
OPA1, OPA0 = 10
Ω
OPA1, OPA0 = 01
pF
VDC
+/-100
mV
DC
With ANA IN to Speaker,
ANA IN AC coupled to
VSSA
ANA IN to SP+/- Idle Channel
Noise
-65
dB
Speaker Load =
(12)(13)
150Ω
SP+/- to ANA OUT Cross
Talk
-65
dB
1 kHz 0TLP input to ANA
IN, with MIC+/- and AUX
IN AC coupled to VSS,
and measured at ANA
OUT feed through mode
(12)
PSRR
Power Supply Rejection Ratio
-55
dB
Measured with a 1 kHz,
100 mV p-p sine wave
input at VCC and VCC pins
FR
Frequency Response (3003400 Hz)
+0.5
dB
With 0TLP input to ANA
(12)
IN, 6 dB setting
Guaranteed by design
POUTLG
Power Output (Low Gain
Setting)
23.5
mW
RMS
Differential load at 8Ω
SINAD
SINAD ANA IN to SP+/-
62.5
dB
0TLP ANA In input
minimum gain, 150Ω
(12)(13)
load
Page 41
ANA OUT
(14)
Symbol
Parameters
Min
SINAD
SINAD, MIC IN to ANA OUT
SINAD
SINAD, AUX IN to ANA OUT
(0 to 9 dB)
ICONIC/ANA OUT
Idle Channel Noise –
Microphone
ICN AUX IN/ANA
OUT
Idle Channel Noise – AUX IN
(0 to 9 dB)
PSRR (ANA OUT)
Power Supply Rejection Ratio
VBIAS
ANA OUT+ and ANA OUT-
VOFFSET
ANA OUT+ to ANA OUT-
RL
Minimum Load Impedance
FR
Frequency Response (3003400 Hz)
CRTANA OUT/(SP+/-)
ANA OUT to SP+/- Cross
Talk
CRTANA OUT/AUX
ANA OUT to AUX OUT Cross
Talk
OUT
AUX OUT
Conditions
62.5
dB
Load = 5kΩ
(12)(13)
62.5
dB
Load = 5kΩ
(12)(13)
-65
dB
Load = 5kΩ
(12)(13)
-65
dB
Load = 5kΩ
(12)(13)
-55
dB
Measured with a 1 kHz,
100 mV P-P sine wave to
VCCA, VCCD pins
1.2
VDC
Inputs AC coupled to
VSSA
mV
DC
Inputs AC coupled to
VSSA
kΩ
Differential Load
dB
0TLP input to MIC+/- in
feedthrough mode.
0TLP input to AUX IN in
(12)
feedthrough mode
-65
dB
1 kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
(12)
measured at SP+/-
-65
dB
1 kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
measured at AUX
(12)
OUT
(1)(14)
Max
+/- 100
5
+0.5
(14)
Symbol
Parameters
VAUX OUT
AUX OUT – Maximum Output
Swing
RL
Minimum Load Impedance
CL
Maximum Load Capacitance
VBIAS
AUX OUT
SINAD
SINAD – ANA IN to AUX OUT
ICN(AUX OUT)
Idle Channel Noise – ANA IN
to AUX OUT
CRTAUX OUT/ANA
AUX OUT to ANA OUT Cross
Talk
OUT
Type
(2)
Units
(2)
Min
(2)
Typ
(1(14))
(2)
Max
1.0
5
Units
V
Conditions
5kΩ Load
KΩ
100
1.2
pF
VDC
62.5
dB
0TLP ANA IN input,
minimum gain, 5k
(12)(13)
load
-65
dB
Load=5kΩ
-65
dB
1 kHz 0TLP input to ANA
IN, with MIC +/- and AUX
IN AC coupled to VSSA,
measured at SP+/-, load
= 5kΩ. Referenced to
nominal 0TLP @ output
(12)(13)
Page 42
VOLUME CONTROL(14)
Symbol
Parameters
AOUT
Output Gain
Absolute Gain
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Min(2)
Typ(1)(14)
Max(2)
-28 to 0
-0.5
+0.5
Units
Conditions
dB
8 steps of 4 dB,
referenced to output
dB
ANA IN 1.0 kHz 0TLP, 6
dB gain setting
measured differentially at
SP+/-
Typical values: TA = 25°C and Vcc = 3.0V.
All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications
are 100 percent tested.
Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions).
Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature and
voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions).
Filter specification applies to the low pass filter.
For optimal signal quality, this maximum limit is recommended.
When a record command is sent, TRAC = TRAC + TRACLO on the first page addressed.
The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission level
point. (0TLP) This is the point where signal clipping may begin.
Measured at 0TLP point for each gain setting. See the ANA IN table and AUX IN table on pages 25 and
26 respectively.
0TLP is the reference test level through inputs and outputs. See the ANA IN table and AUX IN table on
pages 25 and 26 respectively.
Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
For die, only typical values are applicable.
October 2000
Page 43
I2C Interface Timing
STANDARD-MODE
PARAMETER
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
FAST-MODE
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
fSCL
0
100
0
400
kHz
tHD; STA
4.0
-
0.6
-
µs
tLOW
4.7
-
1.3
-
µs
-
0.6
-
µs
-
µs
tHIGH
4.0
Set-up time for a repeated START
condition
tSU; STA
4.7
-
0.6
Data set-up time
tSU; DAT
250
-
100
(1)
-
ns
(2)
0.1Cb
300
ns
(2)
300
ns
Rise time of both SDA and SCL
signals
tr
-
1000
20 +
Fall time of both SDA and SCL
signals
tf
-
300
20 + 0.1Cb
Set-up time for STOP condition
tSU; STO
4.0
-
0.6
-
µs
Bus-free time between a STOP and
START condition
tBUF
4.7
-
1.3
-
µs
Capacitive load for each bus line
Cb
-
400
-
400
pF
Noise margin at the LOW level for
each connected device (including
hysteresis)
VnL
0.1 VDD
-
0.1 VDD
-
V
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VnH
0.2 VDD
-
0.2 VDD
-
V
1.
2
2
A Fast-mode I C-interface device can be used in a Standard-mode I C-interface system, but the requirement
tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line;
2
tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I C -interface specification) before the
SCL line is released.
2.
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed.
October 2000
Page 44
8 TIMING DIAGRAMS
8.1
I2C TIMING DIAGRAM
STOP
START
t
t
SU;DAT
f
t
r
SDA
SCL
t
f
t
HIGH
t
t
LOW
SU;STO
t
8.2
SCLK
PLAYBACK AND STOP CYCLE
tS T O P
tSTART
SDA
PLAY AT ADDR
STOP
SCL
DATA CLOCK PULSES
STOP
ANA IN
ANA OUT
October 2000
Page 45
8.3
EXAMPLE OF POWER UP COMMAND (FIRST 12 BITS)
October 2000
Page 46
9 I2C SERIAL INTERFACE TECHNICAL INFORMATION
CHARACTERISTICS OF THE I2C SERIAL INTERFACE
9.1
2
The I C interface is for bi-directional, two-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive
supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not busy.
9.1.1
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as a control
signal.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
2
Bit transfer on the I C-bus
9.1.2
Start and stop conditions
Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition of
the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P).
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Definition of START and STOP conditions
October 2000
Page 47
9.1.3
System configuration
A device generating a message is a ‘transmitter’; a device receiving a message is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices that are controlled by the master are the
‘slaves’.
LCD
DRIVER
MICRO CONTROLLER
STATIC
RAM OR
EEPROM
SDA
SCL
GATE
ARRAY
ISD 5116
MBC645
2
Example of an I C-bus configuration using two microcontrollers
9.1.4
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level
signal put on the interface bus by the transmitter during which time the master generates an extra
acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. In addition, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that
the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this event, the transmitter must leave the data line HIGH to enable the master to generate a stop
condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Acknowledge on the I2C-bus
October 2000
Page 48
9.2 I2C Protocol
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that
indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being
sent from the current bus master to the device being addressed. This single bit is a 0 for a Read cycle,
which indicates that the data is being sent from the device being addressed to the current bus master. For
example, the valid Slave Addresses for the ISD5116 device, for both Write and Read cycles, are shown in
Section 3.1.1 on page 9 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
st
wishes to transfer data to or from. The Slave Address is always sent out as the 1 byte following the Start
Condition sequence. An example of a Master transmitting an address to a ISD5116 slave is shown below.
In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write cycle. All the bits
transferred are from the Master to the Slave, except for the indicated Acknowledge bits. The following
example details the transfer explained in Section 3.1.2-3 on page 10 of this datasheet.
Master Transmits to Slave Receiver (Write) Mode
acknowledgement
from slave
S
SLAVE ADDRESS
Start Bit
W A
acknowledgement
from slave
COMMAND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
P
Stop Bit
R/W
A common procedure in the ISD5116 is the reading of the Status Bytes. The Read Status condition in the
ISD5116 is triggered when the Master addresses the chip with its proper Slave Address, immediately
followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an example of the
Master sending to the Slave, immediately followed by the Slave sending data back to the Master. The “N”
not-acknowledge cycle from the Master ends the transfer of data from the Slave. The following example
details the transfer explained in Section 3.1.2-1 on page 9 of this datasheet.
Master Reads from Slave immediately after first byte (Read Mode)
a cknow le dge m e nt
from sla ve
F rom S la ve
S
SLAVE ADDRESS
R
A
STATUS W ORD
F rom S la ve
A
High ADDR. BYTE
F rom S la ve
A
Lo w ADDR BYTE
N
P
F rom M a ste r
S ta rt Bit
F rom
M a ste r
R /W
F rom
M a ste r
a cknow le dge m e nt
from M a ste r
a cknow le dge m e nt
from M a ste r
S top Bit
F rom
M a ste r
not-a cknowle dge d
from M a ste r
Another common operation in the ISD5116 is the reading of digital data from the chip’s memory array at a
2
specific address. This requires the I C interface Master to first send an address to the ISD5116 Slave
2
device, and then receive data from the Slave in a single I C operation. To accomplish this, the data
direction R/W bit must be changed in the middle of the command. The following example shows the
Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the
ISD5116, and then immediately changing the data direction and reading some number of bytes from the
chip’s digital array. An unlimited number of bytes can be read in this operation. The “N” not-acknowledge
October 2000
Page 49
cycle from the Master forces the end of the data transfer from the Slave. The following example details
the transfer explained in Section 5.4-2 on page 29 of this datasheet.
Master Reads from the Slave after setting data address in Slave (Write data address, READ Data)
acknowledgement
from slave
S
SLAVE ADDRESS
Start Bit
From
Master
W A
acknowledgement
from slave
COMM AND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
R/W
From
Master
acknowledgement
from slave
From Slave
S
SLAVE ADDRESS
R
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
N
P
From Master
Start Bit
From
Master
R/W
From
Master
acknowledgement
from Master
acknowledgement
from Master
Stop Bit
From
Master
not-acknowled
from Master
October 2000
Page 50
10 DEVICE PHYSICAL DIMENSIONS
10.1. PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
A
B
G
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
4
5
6
7
8
9
10
11
12
13
14
F
C
E
D
J
H
I
Plastic Thin Small Outline Package (T SOP) T ype E Dimensions
INCHES
MILLIMET ERS
Min
Nom
Max
Min
Nom
Max
A
0.520
0.528
0.535
13.20
13.40
13.60
B
0.461
0.465
0.469
11.70
11.80
11.90
C
0.311
0.315
0.319
7.90
8.00
8.10
D
0.002
0.006
0.05
E
0.007
0.009
0.011
0.17
0.22
0.27
F
0.0217
G
0.037
H
I
0
0.020
J
0.004
Note:
0
0.039
0
3
0.022
0.15
0.55
0.041
0
0.95
0
6
0.028
0
0.50
0.008
0.10
1.00
0
3
0.55
1.05
0
6
0.70
0.21
Lead coplanarity to be w ithin 0.004 inches.
October 2000
Page 51
10.2. PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1
2
3 4
5
6
7 8 9 10 11 12 13 14
A
G
C
B
D
E
H
F
Plastic Small Outline Integrated Circuit (SOIC) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
F
0.050
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
Note:
Lead coplanarity to be within 0.004 inches.
October 2000
Page 52
10.3
PLASTIC DUAL INLINE PACKAGE (PDIP) DIMENSIONS
Plastic Dual Inline Package (PDIP) (P) Dimensions
October 2000
Page 53
10.4 DIE BONDING PHYSICAL LAYOUT
ISD5116 DEVICE PIN/PAD LOCATIONS WITH RESPECT TO DIE CENTER IN MICRON (µM)
PIN
Pin Name
X Axis
Y Axis
VSSD
VSS Digital Ground
-1842.90
3848.65
VSSD
VSS Digital Ground
-1671.30
3848.65
AD0
Address 0
-1369.40
3848.65
SDA
Serial Data Address
-818.20
3848.65
AD1
Address 1
-560.90
3848.65
SCL
Serial Clock Line
-201.40
3848.65
VCCD
VCC Digital Supply Voltage
73.20
3848.65
VCCD
VCC Digital Supply Voltage
288.60
3848.65
XCLK
External Clock Input
475.60
3848.65
INT
Interrupt
787.40
3848.65
RAC
Row Address Clock
1536.20
3848.65
VSSA
VSS Analog Ground
1879.45
3848.65
“
-1948.00
-3841.60
MIC+
Non-inverting Microphone Input
-1742.20
-3841.60
MIC-
Inverting Microphone Input
-1509.70
-3841.60
ANA OUT+
Non-inverting Analog Output
-1248.00
-3841.60
ANA OUT-
Inverting Analog Output
-913.80
-3841.60
AGC/AutoMute Cap
-626.50
-3841.60
SP-
Speaker Negative
-130.70
-3841.60
VSSA
VSS Analog Ground
202.90
-3841.60
SP+
Speaker Positive
626.50
-3841.60
VCCA
VCC Analog Supply Voltage
960.10
-3841.60
ANA IN
Analog Input
1257.40
-3841.60
AUX IN
Auxiliary Input
1523.00
-3841.60
Auxiliary Output
1767.20
-3841.60
VSSA
ACAP
AUX OUT
October 2000
“
“
Page 54
ISD 5116 SERIES BONDING PHYSICAL LAYOUT (1) (UNPACKAGED DIE)
VSSD
V S SD
AD0
SCL
SDA ADL
VCCD VCCD
XCLK IN T
RAC
VSS A
ISD5116 Series
Die Dimensions
X: 4125 um
Y: 8030 um
ISD5116
Die Thickness(3)
292.1 um + 12.7 um
Pad Opening (min)
90 x 90 microns
3.5 x 3.5 mils
VSS A
AUXOUT
MIC+
AUX IN
MIC–
ANA IN
ANAOUT+
(2 )
V
ANAOUT– ACAP SP– V S SA(2 ) SP+ CC A
1.
The backside of die is internally connected to Vss. It MUST NOT be connected to any other
potential or damage may occur.
2.
Double bond recommended.
3.
This figure reflects the current die thickness. Please contact ISD as this thickness may change in
the future.
October 2000
Page 55
11 ORDERING INFORMATION
ISD Part Number Description
ISD5116-_ _
Product Family
ISD5116 Product
(8- to 16-minute durations)
Special Temperature Field:
Blank =
Commercial Packaged (0°C to +70°C)
or
Commercial Die (0°C to +50°C)
D
=
Extended (–20°C to +70°C)
I
=
Industrial (–40°C to +85°C)
Package Type:
E
=
28-Lead 8x13.4mm Plastic Thin Small Outline
Package (TSOP) Type 1
S
=
28-Lead 0.300-Inch Plastic Small Outline Package
(SOIC)
X
=
Die
P
=
28-Lead 0.600-Inch Plastic Dual Inline Package (PDIP)
When ordering ISD5116 series devices, please refer to the following valid part numbers.
Part Number
ISD5116E
ISD5116ED
ISD5116EI
ISD5116S
ISD5116SD
ISD5116SI
ISD5116X
ISD5116P
Chip scale package is available upon customer’s request.
For the latest product information, access our website at www.winbond-usa.com.
October 2000
Page 56