CY62138FV30 MoBL® 2-Mbit (256K x 8) Static RAM Functional Description [1] Features • • • • Very high speed: 45 ns Wide voltage range: 2.20V–3.60V Pin compatible with CY62138CV25/30/33 Ultra low standby power The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Place the device into standby mode reducing power consumption when deselected (CE1 HIGH or CE2 LOW). — Typical standby current: 1 µA — Maximum standby current: 5 µA • Ultra low active power • • • • — Typical active current: 1.6 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin SOIC, 32-pin TSOP I and 32-pin STSOP packages To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). Logic Block Diagram IO0 DATA IN DRIVERS SENSE AMPS ROW DECODER IO1 256K x 8 ARRAY IO2 IO3 IO4 IO5 IO6 COLUMN DECODER A12 OE IO7 A15 A16 A17 WE POWER DOWN A13 A14 CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-08029 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 26, 2007 [+] Feedback CY62138FV30 MoBL® Pin Configuration [2] 36-Ball VFBGA Top View A1 A0 IO 4 CE2 32-Pin SOIC/TSOP II Top View A6 A3 WE A4 NC A5 A8 IO 0 B IO 1 C VSS VCC D VCC VSS E IO 2 F A2 IO 5 IO 6 A7 A NC A17 IO 7 OE CE1 A16 A15 IO 3 G A9 A10 A11 A12 A13 A14 H A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 1 32 31 2 3 4 30 29 5 6 28 27 26 25 7 8 9 10 24 23 22 11 12 13 14 15 16 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 Product Portfolio Power Dissipation VCC Range (V) Product CY62138FV30LL Speed (ns) Min Typ [3] Max 2.2 3.0 3.6 45 Operating ICC (mA) f = 1 MHz Standby ISB2 (µA) f = fmax Typ [3] Max Typ [3] Max Typ [3] Max 1.6 2.5 13 18 1 5 Note 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 001-08029 Rev. *E Page 2 of 13 [+] Feedback CY62138FV30 MoBL® DC Input Voltage [4, 5] .......................................–0.3V to 3.9V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Storage Temperature .................................. –65°C to +150°C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied............................................... 55°C to +125°C Product Supply Voltage to Ground Potential ........................................................... –0.3V to 3.9V Range Ambient Temperature VCC [6] CY62138FV30LL Industrial –40°C to +85°C 2.2V to 3.6V DC Voltage Applied to Outputs in High-Z State [4, 5] .......................................... –0.3V to 3.9V Electrical Characteristics (Over the Operating Range) Parameter Description Output HIGH Voltage VOH Output LOW Voltage VOL Input HIGH Voltage VIH Input LOW Voltage VIL Test Conditions 45 ns Min Typ [3] Unit Max IOH = –0.1 mA 2.0 V IOH = –1.0 mA, VCC > 2.70V 2.4 V IOL = 0.1 mA 0.4 V IOL = 2.1 mA, VCC > 2.70V 0.4 V VCC = 2.2V to 2.7V 1.8 VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V For BGA package –0.3 0.6 V VCC= 2.7V to 3.6V –0.3 0.8 V VCC = 2.2V to 3.6V For other packages –0.3 0.6 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, output disabled –1 +1 µA ICC VCC Operating Supply Current f = fmax = 1/tRC 13 18 mA 1.6 2.5 1 5 µA 1 5 µA VCC = VCCmax IOUT = 0 mA CMOS levels f = 1 MHz Automatic CE Power Down Current CMOS Inputs ISB1 CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V, VIN < 0.2V), f = fmax (address and data only), f = 0 (OE, and WE), VCC = 3.60V ISB2 [7] Automatic CE Power Down Current CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V Capacitance (For all packages) [8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max Unit 10 pF 10 pF Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-08029 Rev. *E Page 3 of 13 [+] Feedback CY62138FV30 MoBL® Thermal Resistance [8] Parameter ΘJA Description Test Conditions Thermal Resistance Still air, soldered on a 3 x 4.5 (Junction to Ambient) inch, two layer printed circuit Thermal Resistance board ΘJC (Junction to Case) SOIC VFBGA TSOP II STSOP TSOP I Unit 44.53 38.49 44.16 59.72 50.19 °C/W 24.05 17.66 11.97 15.38 14.59 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE 90% 10% GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT OUTPUT Parameters 2.5V (2.2V to 2.7V) RTH V 3.0V (2.7V to 3.6V) Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Conditions VCC for Data Retention [7] Typ [3] Max Operation Recovery Time Unit V 1 VCC = 1.5V, CE1 > VCC − 0.2V or CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V Chip Deselect to Data Retention Time [9] Min 1.5 Data Retention Current tCDR [8] tR Description 4 µA 0 ns tRC ns Data Retention Waveform [10] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Notes: 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 10. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 001-08029 Rev. *E Page 4 of 13 [+] Feedback CY62138FV30 MoBL® Switching Characteristics (Over the Operating Range) [11] Parameter 45 ns Description Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns tLZOE OE LOW to Low-Z [12] tHZOE OE HIGH to High-Z tLZCE 45 45 10 10 [12, 13] tHZCE CE1 HIGH or CE2 LOW to High-Z tPU CE1 LOW and CE2 HIGH to Power Up Write Cycle ns 18 [12] ns ns 18 0 ns ns 45 CE1 HIGH or CE2 LOW to Power Down ns ns 5 [12,13] CE1 LOW and CE2 HIGH to Low Z tPD ns ns [14] tWC Write Cycle Time 45 ns tSCE CE1 LOW and CE2 HIGH to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns [12, 13] tHZWE WE LOW to High-Z tLZWE WE HIGH to Low-Z [12] 18 10 ns ns Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the ““AC Test Loads and Waveforms” on page 4” . 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write. Document #: 001-08029 Rev. *E Page 5 of 13 [+] Feedback CY62138FV30 MoBL® Switching Waveforms Read Cycle 1 (Address transition controlled) [15, 16] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE controlled) [10, 16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Write Cycle No. 1 (WE controlled) [10, 14, 18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO NOTE 20 tHD DATA VALID tHZOE Notes: 15. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 18. Data IO is high impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals. Document #: 001-08029 Rev. *E Page 6 of 13 [+] Feedback CY62138FV30 MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 3 (WE controlled, OE LOW) [10, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 20 DATA IO tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 WE OE H X X X High-Z Deselect/Power Down Standby (ISB) X L X X High-Z Deselect/Power Down Standby (ISB) L H H L Data Out Read Active (ICC) L H H H High-Z Output Disabled Active (ICC) L H L X Data in Write Active (ICC) Document #: 001-08029 Rev. *E Inputs/Outputs Mode Power Page 7 of 13 [+] Feedback CY62138FV30 MoBL® Ordering Information Speed (ns) Ordering Code Package Diagram 45 CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free) CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) CY62138FV30LL-45ZXI 51-85056 32-pin TSOP I (Pb-free) CY62138FV30LL-45SXI 51-85081 32-pin SOIC (Pb-free) Operating Range Package Type Industrial Package Diagrams Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(36X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B Document #: 001-08029 Rev. *E 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85149-*C Page 8 of 13 [+] Feedback CY62138FV30 MoBL® Package Diagrams (continued) Figure 2. 32-pin TSOP II, 51-85095 51-85095-** Document #: 001-08029 Rev. *E Page 9 of 13 [+] Feedback CY62138FV30 MoBL® Package Diagrams (continued) Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE Document #: 001-08029 Rev. *E 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*B Page 10 of 13 [+] Feedback CY62138FV30 MoBL® Package Diagrams (continued) Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056 51-85056-*D Document #: 001-08029 Rev. *E Page 11 of 13 [+] Feedback CY62138FV30 MoBL® Package Diagrams (continued) Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094 51-85094-*D MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-08029 Rev. *E Page 12 of 13 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62138FV30 MoBL® Document History Page Document Title: CY62138FV30 MoBL®, 2-Mbit (256K x 8) Static RAM Document Number: 001-08029 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 463660 See ECN NXR New data sheet *A 467351 See ECN NXR Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages Changed ball A3 from NC to CE2 in 36-ball FBGA pin out *B 566724 See ECN NXR Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed pin 24 from CE1to OE and pin 22 from CE to CE1) Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 µA to 1 µA Changed the ISB2(max) value from 2.5 µA to 5 µA Changed the ICCDR(typ) value from 0.5 µA to 1 µA and ICCDR(max) value from 2.5 µA to 4 µA *C 797956 See ECN VKN Added 32-pin SOIC package Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical characteristics table *D 809101 See ECN VKN Corrected typo in the Ordering Information table *E 940341 See ECN VKN Added footnote #7 related to ISB2 and ICCDR Document #: 001-08029 Rev. *E Page 13 of 13 [+] Feedback