TI ADS5522IPAPR 12-bit, 80 msps analog-to-digital converter Datasheet

 ADS5522
SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
12-Bit, 80 MSPS
Analog-To-Digital Converter
•
•
FEATURES
•
•
•
•
•
•
•
•
•
12-Bit Resolution
80 MSPS Sample Rate
High SNR: 69.7 dBFS at 100 MHz fIN
High SFDR: 83 dBc at 100 MHz fIN
2.3-VPP Differential Input Voltage
Internal Voltage Reference
3.3-V Single-Supply Voltage
Analog Power Dissipation: 541 mW
Serial Programming Interface
TQFP-64 PowerPAD™ Package
Recommended Op Amps:
OPA695, OPA847, THS3201, THS3202,
THS4503, THS4509, THS9001
APPLICATIONS
•
•
•
•
•
•
Wireless Communication
– Communication Receivers
– Base Station Infrastructure
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
– Radar, Infrared
Video and Imaging
Medical Equipment
DESCRIPTION
The ADS5522 is a high-performance, 12-bit, 80 MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
Designed for applications demanding the highest speed and highest dynamic performance in little space, the
ADS5522 has excellent power consumption of 541 mW at 3.3-V single-supply voltage. This allows an even
higher system integration density. The provided internal reference simplifies system design requirements.
Parallel CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5522 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range.
ADS5500 PRODUCT FAMILY
80 MSPS
105 MSPS
125 MSPS
12 Bit
ADS5522
ADS5521
ADS5520
14 Bit
ADS5542
ADS5541
ADS5500
AVDD
CLK+
CLK−
VIN+
Timing Circuitry
S&H
VIN−
CM
DRVDD
12-Bit
Pipeline
ADC
Core
Internal
Reference
Digital
Error
Correction
Output
Control
SEN
SDATA
SCLK
D0
.
.
.
D11
OVR
DFS
Control Logic
Serial Programming Register
AGND
CLKOUT
ADS5522
DRGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
ADS5522
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SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
ADS5522
HTQFP-64 (2)
PowerPAD
(1)
(2)
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PAP
–40 C to 85 C
ADS5522I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5522IPAP
Tray, 160
ADS5522IPAPR
Tape and Reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47 C/W and θJC = 2.99 C/W, when used with 2 oz. copper
trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
Analog input to AGND
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
(2) (3)
UNIT
V
0.1
V
–0.3 to minimum (AVDD + 0.3, 3.6)
V
Logic input to DRGND
–0.3 to DRVDD
V
Digital data output to DRGND
–0.3 to DRVDD
V
0 to 70
Operating temperature range
–40 to 85
Junction temperature
Storage temperature range
(1)
(2)
(3)
2
ADS5522
–0.3 to 3.7
C
105
C
–65 to 150
C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog
input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle
of the overshoot should be limited to less than 5% for inputs up to 3.9 V.
The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
AVDD
Analog supply voltage
3
3.3
3.6
V
DRVDD
Output driver supply voltage
3
3.3
3.6
V
Analog input
Differential input range
VCM
Input common-mode voltage
2.3
(1)
1.45
VPP
1.55
1.65
V
Digital Output
Maximum output load
10
pF
Clock Input
ADCLK input sample rate (sine wave) 1/tC
2
Clock amplitude, sine wave, differential (2)
1
Clock duty cycle (3)
MSPS
VPP
50%
Open free-air temperature range
(1)
(2)
(3)
80
3
–40
85
C
Input common-mode should be connected to CM.
See Figure 47 for more information.
See Figure 46 for more information.
ELECTRICAL CHARACTERISTICS
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
12
Bits
2.3
VPP
6.6
kΩ
Analog Inputs
Differential input range
Differential input impedance
See Figure 37
Differential input capacitance
See Figure 37
Analog input common-mode current (per input)
Analog input bandwidth
Source impedance = 50 Ω
4
pF
200
µA
750
Voltage overload recovery time
MHz
4
Clock cycles
1
V
2.15
V
Internal Reference Voltages
Reference bottom voltage, V(REFM)
Reference top voltage, V(REFP)
Reference error
–4%
0.6%
4%
1.55
0.05
Common-mode voltage output, V(CM)
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
Differential nonlinearity error, DNL
fIN = 10 MHz
–0.5
0.25
0.5
LSB
Integral nonlinearity error, INL
fIN = 10 MHz
–1.5
0.55
1.5
LSB
±1.5
11
Offset error
-11
Offset temperature coefficient
DC power-supply rejection ratio, DC PSRR
Gain error
∆offset error/∆AVDD from AVDD = 3 V
to AVDD = 3.6 V
(1)
-2
Gain temperature coefficient
(1)
mV
0.02
%/ C
0.25
mV/V
±0.3
–0.02
2
%FS
∆%/ C
Gain error is specified by design and characterization; it is not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
68
70.5
66.5
69.5
MAX
UNIT
Dynamic AC Characteristics
fIN = 10 MHz
25 C
Full temp range
fIN = 55 MHz
Signal-to-noise ratio. SNR
RMS idle channel noise
fIN = 70 MHz
70.3
25 C
Full temp range
68
70.2
66.5
69
fIN = 100 MHz
69.7
fIN = 150 MHz
68.6
fIN = 220 MHz
67.2
Input tied to common-mode
0.43
fIN = 10 MHz
25 C
79
87
Full temp range
76
84
fIN = 55 MHz
Spurious-free dynamic range, SFDR
fIN = 70 MHz
25 C
78
84
Full temp range
76
83
83
fIN = 150 MHz
78
fIN = 220 MHz
fIN = 70 MHz
79
87
Full temp range
76
86
25 C
78
84
Full temp range
76
83
86
fIN = 100 MHz
83
fIN = 150 MHz
78
fIN = 220 MHz
71
fIN = 10 MHz
25 C
79
91
Full temp range
76
87
25 C
78
83
Full temp range
76
83
fIN = 55 MHz
Third-harmonic, HD3
fIN = 70 MHz
fIN = 100 MHz
83
fIN = 150 MHz
86
25 C
90
fIN = 70 MHz
25 C
89
25 C
Full temp range
67.5
66
fIN = 55 MHz
Signal-to-noise + distortion, SINAD
4
fIN = 70 MHz
dBc
84
fIN = 10 MHz
fIN = 10 MHz
dBc
90
fIN = 220 MHz
Worst-harmonic/spur (other than HD2 and HD3)
dBc
71
25 C
fIN = 55 MHz
Second-harmonic, HD2
LSB
87
fIN = 100 MHz
fIN = 10 MHz
dBFS
dBc
70.4
69
70.1
25 C
Full temp range
67.5
69.9
66
68.5
fIN = 100 MHz
69.4
fIN = 150 MHz
68.1
fIN = 220 MHz
65.8
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
CONDITIONS
fIN = 10 MHz
MIN
TYP
25 C
78
85.2
Full temp range
75
Effective number of bits, ENOB
Two-tone intermodulation distortion, IMD
AC power supply rejection ratio, ACPSRR
fIN = 70 MHz
UNIT
82
fIN = 55 MHz
Total harmonic distortion, THD
MAX
83.6
25 C
77
82.1
Full temp range
75
81
fIN = 100 MHz
80.8
fIN = 150 MHz
76.6
fIN = 220 MHz
70.4
fIN = 70 MHz
11.3
f = 10.1 MHz, 15.1 MHz
(–7dBFS each tone)
88
f = 50.1 MHz, 55.1 MHz
(–7dBFS each tone)
85
f = 148.1 MHz, 153.1 MHz
(–7dBFS each tone)
93
Supply noise frequency ≤ 100 MHz
35
dBc
Bits
dBFS
dB
Power Supply
Total supply current, ICC
fIN = 70 MHz
201
230
mA
Analog supply current, I(AVDD)
fIN = 70 MHz
164
180
mA
Output buffer supply current, I(DRVDD)
fIN = 70 MHz, 10-pF load from digital
outputs to ground
37
50
mA
Analog only
541
594
Power dissipation
Output buffer power with 10-pF load on
digital output to ground
122
165
Standby power
With Clocks running
180
250
mW
mW
DIGITAL CHARACTERISTICS
Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
VIH
High-level input voltage
2.4
VIL
Low-level input voltage
0.8
V
IIH
High-level input current
10
µA
IIL
Low-level input current
–10
µA
Input current for RESET
Input capacitance
V
–20
µA
4
pF
Digital Outputs
VOL
Low-level output voltage
CLOAD = 10 pF
VOH
High-level output voltage
CLOAD = 10 pF
Output capacitance
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0.3
2.8
0.4
V
3
V
3
pF
5
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SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
Analog
Input
Signal
Sample
N
N + 1
N + 2
N + 3
N + 4
N + 14
N + 15
N + 17
N + 16
tA
Input Clock
tSTART
Output Clock
tPDI
tsu
Data Out
(D0−D11)
N − 17
N − 16
N − 15
N − 14
N − 13
N−3
N−2
N−1
N
Data Invalid
tEND
th
17.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS (1)
Typical values given at TA = 25 C, min and max specified over the full recommeded operating temperature range,
AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF,
unless otherwise noted (2)
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
tA
Input CLK falling edge to data sampling point
Aperture jitter (uncertainty)
Uncertainty in sampling instant
valid (3)
ns
fs
3.6
4.7
ns
1.8
3.1
ns
Data setup time
Data
tH
Data hold time
50% of CLKOUT rising edge to data becoming
invalid (3)
tSTART
Input clock to output data valid
start (4) (5)
Input clock rising edge to data valid start delay
tEND
Input clock to output data valid
end (4) (5)
Input clock rising edge to data valid end delay
tJIT
Output clock jitter
Uncertainty in CLKOUT rising edge, peak-to-peak
210
315
ps
tr
Output clock rise time
Rise time of CLKOUT measured from 20% to 80%
of DRVDD
2.5
2.8
ns
tf
Output clock fall time
Fall time of CLKOUT measured from 80% to 20%
of DRVDD
2.1
2.3
ns
tPDI
Input clock to output clock delay
Input clock rising edge zero crossing, to output
clock rising edge 50%
8
8.9
ns
tr
Data rise time
Data rise time measured from 20% to 80% of
DRVDD
5.6
6.1
ns
tf
Data fall time
Data fall time measured from 80% to 20% of
DRVDD
4.4
5.1
ns
Output enable(OE) to data output
delay
Time required for outputs to have stable timings
with regard to input clock (6) after OE is activated
(6)
to 50% of CLKOUT rising edge
1
300
tSU
(1)
(2)
(3)
(4)
(5)
6
Aperture delay
3.3
8.4
7.1
5.0
11.1
ns
ns
1000
Clock
cycles
Timing parameters are ensured by design and characterization, and not tested in production.
See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.
Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
See the Output Information section for details on using the input clock for data capture.
These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
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TIMING CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommeded operating temperature range,
AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF,
unless otherwise noted
PARAMETER
Wakeup time
Latency
DESCRIPTION
MIN
TYP
MAX
Time to valid data after coming out of software
power down
1000
Time to valid data after stopping and restarting the
clock
1000
Time for a sample to propagate to the ADC outputs
17.5
UNIT
Clock
cycles
Clock
cycles
RESET TIMING CHARACTERISTICS
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
t1
Power-on delay
Delay from power-on of AVDD and DRVDD to RESET pulse active
t2
Reset pulse width
t3
Register write delay
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
Power Supply
(AVDD, DRVDD)
10
ms
Pulse width of active RESET signal
2
µs
Delay from RESET disable to SEN active
2
µs
40
ms
t1 10 ms
t2 2 ms
t3 2 ms
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5522 has a three-wire serial interface. The device latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
• Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
• Minimum width of data stream for a valid loading is 16 clocks.
• Data is loaded at every 16th SCLK falling edge while SEN is low.
• In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
• Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
• The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS (continued)
A3
SDATA
A2
A1
A0
D11
D10
ADDRESS
D9
D0
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
tSLOADS
SEN
tSLOADH
tWSCLK tWSCLK
tSCLK
SCLK
tsu(D)
SDATA
th(D)
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
(1)
MIN (1)
PARAMETER
tSCLK
SCLK period
tWSCLK
SCLK duty cycle
TYP (1)
MAX (1)
50%
75%
50
UNIT
ns
25%
tSLOADS
SEN to SCLK setup time
8
ns
tSLOADH
SCLK to SEN hold time
6
ns
tDS
Data setup time
8
ns
tDH
Data hold time
6
ns
Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table (1)
A3 A2 A1 A0
D11
D10
D9
TP<1
>
TP<0
>
D8 D7 D6 D5 D4 D3 D2
D1
D0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
X
0
Normal mode of operation
1
1
1
0
0
0
1
0
0
0
0
0
0
0
X
0
All outputs forced to 0 (2)
1
1
1
0
0
1
0
0
0
0
0
0
0
0
X
0
All outputs forced to 1 (2)
1
1
1
0
0
1
1
0
0
0
0
0
0
0
X
0
Each output bit toggles between 0 and 1.
1
1
1
1
0
0
0
0
0
0
0
0
0
0
X
0
Normal mode of operation
1
1
1
1
1
0
0
0
0
0
0
0
0
0
X
0
Device is put in power-down (low-current) mode.
PDN
(1)
(2)
(3)
8
DESCRIPTION
Test Mode
(2) (3)
Power Down
The register contents default to the appropriate setting for normal operation up on RESET.
The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode
outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.
While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D11. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
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Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS)
2
V DFS t
12
AV DD
DATA FORMAT
CLOCK OUTPUT POLARITY
Straight Binary
Data valid on rising edge
4
12
5
AV DD t V DFS t
12
AV DD
Two's Complement
Data valid on rising edge
7
12
8
AV DD t V DFS t
12
AV DD
Straight Binary
Data valid on falling edge
Two's Complement
Data valid on falling edge
V DFS u
10
12
AV DD
PIN CONFIGURATION
DRVDD
DRGND
D7
D6
59
58
57
56
55
DRVDD
DRGND
60
DRGND
D8
61
D2
D9
62
D3
D10
63
D5
D11 (MSB)
64
D4
OVR
PAP PACKAGE
(TOP VIEW)
54
53
52
51
50
49
DRGND
1
48 DRGND
SCLK
2
47 D1
SDATA
3
46 D0 (LSB)
SEN
4
45 NC
AVDD
5
44 NC
AGND
6
43 CLKOUT
AVDD
7
AGND
8
AVDD
9
42 DRGND
ADS5522
PowerPAD
41 OE
40 DFS
(Connected to Analog Ground)
CLKP 10
39 AVDD
CLKM 11
38 AGND
AGND 12
37 AVDD
AGND 13
36 AGND
23
24
25
26
27
28
29
30
31
32
AGND
AVDD
REFP
REFM
IREF
AGND
22
AVDD
21
AGND
20
AGND
19
AVDD
18
AVDD
17
AGND
33 AVDD
INM
AGND 16
INP
34 AVDD
AGND
35 RESET
CM
AGND 14
AVDD 15
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PIN ASSIGNMENTS
TERMINAL
NO. OF
PINS
I/O
AVDD
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
12
I
Analog power supply
AGND
6, 8, 12–14, 16,
18, 21, 23, 25,
27, 32, 36, 38
14
I
Analog ground
DRVDD
49, 58
2
I
Output driver power supply
DRGND
1, 42, 48, 50,
57, 59
6
I
Output driver ground
NC
44, 45
2
—
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive); 1- F capacitor in series with a 1-Ω resistor to GND
REFM
30
1
O
Reference voltage (negative); 1- F capacitor in series with a 1-Ω resistor to GND
IREF
31
1
I
Current set; 56.2-kΩ resistor to GND; do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), Internal 200-kΩ resistor to AVDD (1)
OE
41
1
I
Output enable (active high) (2)
DFS
40
1
I
Data format and clock out polarity select (3) (2)
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select (2)
SDATA
3
1
I
Serial interface data (2)
SCLK
2
1
I
Serial interface clock (2)
46, 47, 51–56,
60-63
14
O
Parallel data output
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
NAME
NO.
D0 (LSB) to
D11 (MSB)
(1)
(2)
(3)
10
DESCRIPTION
Not connected
If RESET pin is unused, it must be tied to AGND and serial interface should be used to reset the device. See the serial programming
interface section for details.
Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
Table 3 defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1 LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSBs.
Integral Nonlinearity (INL)
The offset error is the difference, given in number of
LSBs, between the ADC's actual average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
DC and the first eight harmonics.
P
SNR + 10Log 10 S
PN
(1)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
PS
SINAD + 10Log 10
PN ) PD
(2)
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSBs.
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Gain Error
Effective Number of Bits (ENOB)
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Specifications section for limits on the
variation of V(REFP) and V(REFM)).
The ENOB is a measure of a converter's
performance as compared to the theoretical limit
based on quantization noise.
ENOB + SINAD * 1.76
6.02
(3)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
P
THD + 10Log 10 S
PD
(4)
THD is typically given in units of dBc (dB to carrier).
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Spurious-Free Dynamic Range (SFDR)
Reference Error
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
The reference error is the variation of the actual
reference voltage (V(REFP)– V(REFM)) from its ideal
value. The reference error is typically given as a
percentage.
Two-Tone Intermodulation Distortion (IMD3)
Voltage Overload Recovery Time
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or
2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to
the converter's full-scale range.
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
DC Power Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
12
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 4 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16 MHz Input Signal)
0
0
SFDR = 90.0 dBc
THD = 86.4 dBc
SNR = 71.2 dBFS
SINAD = 71.1 dBFS
−40
SFDR = 86.8 dBc
THD = 85.2 dBc
SNR = 70.9 dBFS
SINAD = 70.8 dBFS
−20
Amplitude− dB
Amplitude− dB
−20
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
0
40
5
10
f − Frequency − MHz
25
30
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70 MHz Input Signal)
35
40
0
SFDR = 87.0 dBc
THD = 82.2 dBc
SNR = 70.6 dBFS
SINAD = 70.4 dBFS
−40
SFDR = 85.9 dBc
THD = 83.7 dBc
SNR = 70.5 dBFS
SINAD = 70.3 dBFS
−20
Amplitude− dB
−20
Amplitude− dB
20
f − Frequency − MHz
0
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
0
5
10
f − Frequency − MHz
15
20
25
30
35
40
35
40
f − Frequency − MHz
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 100 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125 MHz Input Signal)
0
0
SFDR = 87.2 dBc
THD = 82.8 dBc
SNR = 69.8 dBFS
SINAD = 69.6 dBFS
−40
SFDR = 80.2 dBc
THD = 77.8 dBc
SNR = 69.3 dBFS
SINAD = 68.8 dBFS
−20
Amplitude− dB
−20
Amplitude− dB
15
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
f − Frequency − MHz
0
5
10
15
20
25
30
f − Frequency − MHz
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 150 MHz Input Signal)
0
0
SFDR = 81.7 dBc
THD = 79.9 dBc
SNR = 68.7 dBFS
SINAD = 68.4 dBFS
SFDR = 69.8 dBc
THD = 69.2 dBc
SNR = 67.0 dBFS
SINAD = 65.3 dBFS
−20
Amplitude− dB
−20
Amplitude− dB
SPECTRAL PERFORMANCE
(FFT for 220 MHz Input Signal)
−40
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
25
20
35
30
40
0
5
10
f − Frequency − MHz
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal)
TWO-TONE
INTERMODULATION
30
35
40
0
SFDR = 69.0 dBc
THD = 68.7 dBc
SNR = 64.8 dBFS
SINAD = 58.0 dBFS
f1 = 10 MHz, −7 dBFS
f1 = 15 MHz, −7 dBFS
2-Tone IMD = −88.0 dBFS
−20
Amplitude− dB
Amplitude− dB
25
Figure 12.
−20
−40
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
0
40
5
10
f − Frequency − MHz
15
20
25
30
35
40
f − Frequency − MHz
Figure 13.
Figure 14.
TWO-TONE
INTERMODULATION
TWO-TONE
INTERMODULATION
0
0
f1 = 50 MHz, −7 dBFS
f1 = 55 MHz, −7 dBFS
2-Tone IMD = −84.8 dBFS
f1 = 148 MHz, −7 dBFS
f1 = 153 MHz, −7 dBFS
2-Tone IMD = −92.8 dBFS
−20
Amplitude− dB
−20
Amplitude− dB
20
Figure 11.
0
−40
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
0
f − Frequency − MHz
5
10
15
20
25
f − Frequency − MHz
Figure 15.
14
15
f − Frequency − MHz
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
0.25
0.60
0.20
0.50
0.15
0.40
0.10
0.30
0.20
LSB
LSB
0.05
0
0.10
−0.05
−0.10
0
−0.15
−0.10
−0.20
−0.25
0
−0.20
fIN = 10.1 MHz, AIN = −0.5 dBFS
512
1024 1536
2048
2560 3072
−0.30
0
3584 4096
2048
2560 3072
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
3584 4096
72
Signal-to-Noise Ratio − dBFS
80
SFDR − dBc
1024 1536
Code
85
75
70
65
60
fS = 80 MSPS
AIN = −1 dBFS
55
50
71
70
69
68
67
fS = 80 MSPS
AIN = −1 dBFS
66
50
100
150
300
0
150
100
250
200
Input Frequency − MHz
Figure 19.
Figure 20.
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
300
90
fIN = 150 MHz
SFDR
80
85
SFDR
80
75
SNR − dBFS
75
70
SNR
65
60
3.00
50
Input Frequency − MHz
90
85
250
200
SFDR − dBc
0
SFDR − dBc
512
Code
90
SNR − dBFS
fIN = 10.1 MHz
AIN = −0.5 dBFS
3.15
3.30
3.45
3.60
70
SNR
65
fIN = 70 MHz
60
3.00
3.15
3.30
3.45
AVDD − Analog Supply Voltage − V
AVDD − Analog Supply Voltage − V
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
90
fIN = 150 MHz
SFDR − dBc
SFDR − dBc
90
85
80
fIN = 70 MHz
85
SFDR
80
SFDR
75
SNR − dBFS
SNR − dBFS
75
70
SNR
65
60
3.00
0.8
3.15
3.30
3.45
Figure 24.
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
0.8
IF = 150 MHz
3.60
IF = 70 MHz
0.7
Power Dissipation − W
Power Dissipation − W
0.5
0.4
0.3
0.2
0.6
0.5
0.4
0.3
0.2
0.1
20
30
40
50
60
70
0
10
80
20
30
40
50
60
Sample Rate − MSPS
Sample Rate − MSPS
Figure 25.
Figure 26.
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
70
80
90
fIN = 70.1 MHz
SNR (dBFS)
70
85
AC Performance − dB
SFDR − dBc
3.45
Figure 23.
90
SNR − dBFS
3.30
DVDD − Digital Supply Voltage − V
0.1
16
3.15
DVDD − Digital Supply Voltage − V
0.6
SFDR
80
75
SNR
70
65
−40
SNR
65
60
3.00
3.60
0.7
0
10
70
50
30
SFDR (dBc)
SNR (dBc)
10
−10
fIN = 70.1 MHz
−15
10
35
60
85
−30
−100
−90 −80 −70 −60 −50 −40 −30 −20 −10
Temperature − °C
Input Amplitude − dBFS
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
AC PERFORMANCE
vs INPUT AMPLITUDE
AC PERFORMANCE
vs INPUT AMPLITUDE
90
90
SNR (dBFS)
70
AC Performance − dB
AC Performance − dB
70
50
30
SFDR (dBc)
10
−10
SNR (dBc)
SNR (dBc)
fIN = 220.1 MHz
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
−90 −80 −70 −60 −50 −40 −30 −20 −10
Input Amplitude − dBFS
Input Amplitude − dBFS
Figure 29.
Figure 30.
OUTPUT
NOISE HISTOGRAM
AC PERFORMANCE
vs CLOCK AMPLITUDE
90
SFDR − dBc
70
60
50
40
0
fIN = 70.1 MHz
85
SFDR
80
75
SNR − dBFS
Percentage − %
10
−30
−100
80
30
20
10
0
2052
0
70
SNR
65
60
2053
2054
2055
2056
2057
2058
0
2059
0.5
1
1.5
2
2.5
Code
Differential Clock Amplitude − V
Figure 31.
Figure 32.
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
3
90
SFDR − dBc
fS = 76.8 MSPS
fIN = 170 MHz
−20
−40
SFDR
85
80
−60
75
−80
SNR − dBFS
Amplitude − dB
SFDR (dBc)
30
−10
fIN = 150.1 MHz
−30
−100
SNR (dBFS)
50
−100
−120
−140
0
5
10
15
20
25
30
35
40
SNR
70
65
fIN = 20.1 MHz
60
30
40
50
f − Frequency − MHz
Clock Duty Cycle − %
Figure 33.
Figure 34.
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70
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TYPICAL CHARACTERISTICS
Typ, min, max values at TA = 25 C, full temperature range is TMIN = –40 C to TMAX = 85 C, AVDD = DRVDD = 3.3 V,
sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp differential clock, and –1 dBFS differential input, unless otherwise
noted
SIGNAL-TO-NOISE RATIO (SNR)
100
90
71
70
69
71
69
80
70
68
67
66
60
69
71
68
70
50
69
40
64
71
67
68
70
71
69
67
68
30
65
66
65
66
63
62
64
61
20
63
70
10
20
40
67
66
69 68
60
80
65
100
120
64
140
63
160
Input Frequency − MHz
Figure 35.
18
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200
62
61
60
220
63
SNR − dBFS
Sample Rate − MSPS
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TYPICAL CHARACTERISTICS (continued)
Typ, min, max values at TA = 25 C, full temperature range is TMIN = –40 C to TMAX = 85 C, AVDD = DRVDD = 3.3 V,
sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp differential clock, and –1 dBFS differential input, unless otherwise
noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
80
100
90
86 88
90
86
88
86
82
84
88
86
84
82
78
80
76 74
86
60
78
88
86
82
86
50
40
76
74
86
88
84
72
84
30
82
88
84
80
86
82
60
72
70
80
100
66
68
66
78
80
40
68
76 74
84
86
20
70
78
86
10
66
84
88
20
72 70 68
80
SFDR − dBc
Sample Rate − MSPS
86
84
88
70 90
66
80
86
90
72 70 68
84
84
88
80
82
86
84
76 74
78
120
140
160
180
200
64
64
220
Input Frequency − MHz
Figure 36.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5522 is a low-power, 12-Bit, 80 MSPS,
CMOS, switched capacitor, pipeline ADC that
operates from a single 3.3-V supply. The conversion
process is initiated by a falling edge of the external
input clock. Once the signal is captured by the input
S&H, the input sample is sequentially converted by a
series of small resolution stages, with the outputs
combined in a digital correction logic block. Both the
rising and the falling clock edges are used to
propagate the sample through the pipeline every half
clock cycle. This process results in a data latency of
17.5 clock cycles, after which the output data is
available as a 12-bit parallel word, coded in either
straight offset binary or binary two's complement
format.
INPUT CONFIGURATION
The analog input for the ADS5522 consists of a
differential
sample-and-hold
architecture
implemented using the switched capacitor technique
shown in Figure 37.
S3a
L1
R1a
C1a
INP
S1a
CP1
CP3
S2
R3
CA
L2
R1b
INM
S1b
C1b
VINCM
1V
CP2
CP4
L1, L2: 6 nH − 10 nH effective
R1a, R1b: 5W − 8W
C1a, C1b: 2.2 pF − 2.6 pF
CP1, CP2: 2.5 pF − 3.5 pF
CP3, CP4: 1.2 pF − 1.8 pF
CA: 0.8 pF − 1.2 pF
R3: 80 W − 120 W
Swithches: S1a, S1b: On Resistance: 35 W − 50 W
S2: On Resistance: 7.5 W − 15 W
S3a, S3b: On Resistance: 40 W − 60 W
All switches OFF Resistance: 10 GW
S3b
NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 37. Analog Input Stage
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This differential input topology produces a high level
of ac-performance for high sampling rates. It also
results in a very high usable input bandwidth,
especially important for high intermediate-frequency
(IF) or undersampling applications. The ADS5522
requires each of the analog inputs (INP, INM) to be
externally biased around the common-mode level of
the internal circuitry (CM, pin 17). For a full-scale
differential input, each of the differential lines of the
input signal (pins 19 and 20) swings symmetrically
between CM + 0.575 V and CM –0.575 V. This
means that each input is driven with a signal of up to
CM 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential
input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top
reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5522 obtains optimum performance when
the analog inputs are driven differentially. The circuit
shown in Figure 38 illustrates one possible
configuration using an RF transformer.
RO
ZO
50W
50W
25W
R
50W
ADS5522
25W
10W
0.1 mF
Figure 38. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding
of an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (VCM)
from the ADS5522 is connected to the center-tap of
the secondary winding. To ensure a steady low-noise
VCM reference, best performance is attained when
the CM output (pin 17) is filtered to ground with a
0.1-µF and 0.001-µF low-inductance capacitors,
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 400 µA (200
µA per input) at 80 MSPS. Equation 5 describes the
dependency of the common-mode current and the
sampling frequency:
400 mA x fs (in MSPS)
80
(5)
Where:
fS > 2MSPS.
This equation helps to design the output capability
and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of
the ADS5522. Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, OPA847, and
OPA695) that can be selected depending on the
application. An RF gain block amplifier, such as TI'ss
THS9001, can also be used with an RF transformer
for high input frequency applications. The THS4503
is a recommended differential input/output amplifier.
Table 4 lists the recommended amplifiers.
When using single-ended operational amplifiers
(such as the THS3201, THS3202, OPA847, or
OPA695) to provide gain, a three-amplifier circuit is
recommended with one amplifier driving the primary
of an RF transformer and one amplifier in each of the
legs of the secondary driving the two differential
inputs of the ADS5522. These three amplifier circuits
minimize even-order harmonics. For high frequency
inputs, an RF gain block amplifier can be used to
drive a transformer primary; in this case, the
transformer secondary connections can drive the
input of the ADS5522 directly, as shown in
Figure 38, or with the addition of the filter circuit
shown in Figure 39.
Figure 39 illustrates how RIN and CIN can be placed
to isolate the signal source from the switching inputs
of the ADC and to implement a low-pass RC filter to
limit the input noise in the ADC. It is recommended
that these components be included in the ADS5522
circuit layout when any of the amplifier circuits
discussed previously are used. The components
allow fine-tuning of the circuit performance. Any
mismatch between the differential lines of the
ADS5522 input produces a degradation in
performance at high input frequencies, mainly
characterized by an increase in the even-order
harmonics. In this case, special care should be taken
to keep as much electrical symmetry as possible
between both inputs.
Another possible configuration for lower-frequency
signals is the use of differential input/output
amplifiers that can simplify the driver circuit for
applications requiring dc-coupling of the input.
Flexible in their configurations (see Figure 40), such
amplifiers can be used for single-ended-to-differential
conversion signal amplification.
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ADS5522
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SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
Table 4. Recommended Amplifiers to Drive the Input of the ADS5522
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
DC to 20 MHz
THS4503
Differential In/Out Amp
No
DC to 50 MHz
OPA847
Operational Amp
Yes
DC to 100 MHz
THS4509
Differential In/Out Amp
No
OPA695
Operational Amp
Yes
THS3201
Operational Amp
Yes
THS3202
Operational Amp
Yes
THS9001
RF Gain Block
Yes
10 MHz to 120 MHz
Over 100 MHz
+5V
USE WITH TRANSFORMER?
5V
RS
100W
VIN
0.1 mF
OPA695
1000 pF
R1
400W
RIN
1:1
25 W
INP
RT
100W
RIN
CIN
ADS5522
25 W
INM
CM
R2
57.5 W
AV = 8V/V
(18dB)
10 W
0.1 mF
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
22
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ADS5522
www.ti.com
SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
RS
RF
RS
+5V
RT
+3.3V
10 mF
0.1 mF
RIN
INP
VCOM
RIN
INM
1 mF
CM
THS4503
10 mF
RG
ADS5522
12-Bit / 80MSPS
5V
0.1 mF
RF
10W
0.1 mF
Figure 40. Using the THS4503 with the ADS5522
Submit Documentation Feedback
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ADS5522
www.ti.com
SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
POWER-SUPPLY SEQUENCE
The preferred power-up sequence is to ramp AVDD
first, followed by DRVDD, including a simultaneous
ramp of AVDD and DRVDD. In the event that DRVDD
ramps up first in the system, care must be taken to
ensure that AVDD ramps up within 10 ms. Optionally,
it is recommended to put a 2-kΩ resistor from REFP
(pin 29) to AVDD as shown in Figure 41. This helps
to make the device more robust to power supply
ramp-up timings.
connected from IREF (pin 31) to AGND to set
proper current for the operation of the ADC,
shown in Figure 42. No capacitor should
connected between pin 31 and ground; only
56.2-kΩ resistor should be used.
the
as
be
the
1W
29
REFP
30
REFM
31
IREF
1 mF
1W
1 mF
28
AVDD
56.2 kW
2 kW
29
REFP
1W
Figure 42. REFP, REFM, and IREF Connections
for Optimum Performance
1 mF
CLOCK INPUT
Figure 41. Power-Up Sequence
POWER-DOWN
The device enters power-down in one of two ways:
either by reducing the clock speed or by setting the
PDN bit throught the serial programming interface.
Using the reduced clock speed, power-down may be
initiated for clock frequency below 2 MSPS. The
exact frequency at which the power down occurs
varies from device to device.
Using the serial interface PDN bit to power down the
device places the outputs in a high-impedance state
and only the internal reference remains on to reduce
the power-up time. The power-down mode reduces
power dissipation to approximately 180 mW.
The ADS5522 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between
both configurations. The common-mode voltage of
the clock inputs is set internally to CM (pin 17) using
internal 5-kΩ resistors that connect CLKP (pin 10)
and CLKM (pin 11) to CM (pin 17), as shown in
Figure 43.
CM
CM
5 kW
5 kW
CLKM
CLKP
REFERENCE CIRCUIT
The ADS5522 has built-in internal reference
generation, requiring no external circuitry on the
printed circuit board (PCB). For optimum
performance, it is best to connect both REFP and
REFM to ground with a 1-µF decoupling capacitor
(the 1-Ω resistor shown in Figure 42 is optional). In
addition, an external 56.2-kΩ resistor should be
6 pF
3 pF
Figure 43. Clock Inputs
24
Submit Documentation Feedback
3 pF
ADS5522
www.ti.com
SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
Square Wave
or Sine W ave
(3 VPP)
CLKP
100
SFDR − dBc
When driven with a single-ended CMOS clock input,
it is best to connect CLKM (pin 11) to ground with a
0.01-µF capacitor, while CLKP is ac-coupled with a
0.01-µF capacitor to the clock source, as shown in
Figure 44.
fIN = 20MHz
95
SFDR
90
85
80
0.01 mF
SNR − dBFS
ADS5522
CLKM
0.01 mF
75
SNR
70
65
60
35
40
0.01 mF
CLKP
Differential Square Wave
or Sine Wave
(3 VPP)
ADS5522
0.01 mF
CLKM
Figure 45. AC-Coupled, Differential Clock Input
55
60
65
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further
improves as the amplitude is increased. In that
sense, using a differential clock allows for the use of
larger amplitudes without exceeding the supply rails
and absolute maximum ratings of the ADC clock
input. Figure 47 shows the performance variation of
the device versus input clock amplitude. For detailed
clocking schemes based on transformer or
PECL-level clocks, see the ADS5522EVM User's
Guide (SLWU010), available for download from
www.ti.com.
95
fIN = 70MHz
90
SFDR
85
80
SNR − dBFS
For high input frequency sampling, it is
recommended to use a clock source with low jitter.
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 46 shows the performance variation of the
ADC versus clock duty cycle.
50
Figure 46. AC Performance vs Clock Duty Cycle
SFDR − dBc
The ADS5522 clock input can also be driven
differentially,
reducing
susceptibility
to
common-mode noise. In this case, it is best to
connect both clock inputs to the differential input
clock signal with 0.01-µF capacitors, as shown in
Figure 45.
45
Clock Duty Cycle − %
Figure 44. AC-Coupled, Single-Ended Clock Input
75
SNR
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude − V
Figure 47. AC Performance vs Clock Amplitude
Submit Documentation Feedback
25
ADS5522
www.ti.com
SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
OUTPUT INFORMATION
The output circuitry of the ADS5522, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output
slew rate described in the timing diagram of Figure 1.
Care should be taken to ensure that all output lines
(including CLKOUT) have nearly the same load as
D2 (pin 51). This circuit also reduces the sensitivity
of the output timing versus supply voltage or
temperature. Placing external resistors in series with
the outputs is not recommended.
The ADC provides 12 data outputs (D11 to D0, with
D11 being the MSB and D0 the LSB), a data-ready
signal (CLKOUT, pin 43), and an out-of-range
indicator (OVR, pin 64) that equals 1 when the
output reaches the full-scale limits.
Two different output formats (straight offset binary or
two's complement) and two different output clock
polarities (latching output data on rising or falling
edge of the output clock) can be selected by setting
DFS (pin 40) to one of four different voltages.
Table 3 details the four modes. In addition, output
enable control (OE, pin 41, active high) is provided to
put the outputs into a high-impedance state.
The timing characteristics of the digital outputs
change for sampling rates below the 80 MSPS
maximum sampling frequency. Table 5 and Table 6
show the values of various timing parameters at
lower sampling frequencies.
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0xFFF in
straight offset binary output format and 0x7FF in
two's complement output format. For a negative input
overdrive, the output code is 0x000 in straight offset
binary output format and 0x800 in two's complement
output format. These outputs to an overdrive signal
are ensured through design and characterization.
To use the input clock as the data capture clock, it is
necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either
of the following equations to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 5. Timing Characteristics at Additional Sampling Frequencies
tsu (ns)
th (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN
TYP
MIN
TYP
TYP
MAX
MIN
TYP
TYP
MAX
TYP
MAX
65
4.7
6.0
2.1
3.1
2.4
4.2
8.3
12.0
6.6
7.2
5.5
6.4
40
8.5
11
2.8
3.5
-1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17
25.7
2.5
4.7
-9.8
2
9.5
21.6
7.5
8
7.6
8
10
27
51
4
6.5
-30
-3
11.5
31
2
284
370
8
19
185
320
515
576
50
82
75
150
MAX
MAX
MIN
MAX
MIN
MIN
Table 6. Timing Characteristics at Additional Sampling Frequencies
fS
(MSPS)
CLKOUT, Rise Time
tr (ns)
TYP
MAX
65
MIN
3.1
3.5
40
4.8
20
8.3
CLKOUT, Fall Time
tf (ns)
MIN
CLKOUT Jitter, Peak-to-Peak
tJIT (ps)
Input-to-Output Clock Delay
tPDI (ns)
MIN
TYP
MAX
TYP
MAX
MIN
TYP
MAX
2.6
2.9
260
380
7.8
8.5
9.4
5.3
4
4.4
445
650
9.5
10.4
11.4
9.5
7.6
8.2
800
1200
13
15.5
18
16
20.7
25.5
537
551
567
10
2
26
31
52
36
65
2610
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ADS5522
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SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
SERIAL PROGRAMMING INTERFACE
The ADS5522 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power-up by applying a 2 µs (minimum) high pulse
on RESET (pin 35); this also resets the entire ADC
and sets the data outputs to low. This pin has a
200-kΩ internal pullup resistor to AVDD. The
programming is done through a three-wire interface.
Table 2 shows the different modes and the bit values
to be written to the register to enable them.
Note that some of these modes may modify the
standard operation of the device and possibly vary
the performance with respect to the typical data
shown in this data sheet.
Applying a RESET signal is absolutely essential to
set the internal registers to their default states for
normal operation. If the hardware RESET function is
not used in the system, the RESET pin must be tied
to ground and it is necessary to write the default
values to the internal registers through the serial
programming interface. The registers must be written
in the following order.
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse
is not provided to the device.
PowerPAD PACKAGE
The PowerPAD package is a thermally enhanced
standard size IC package designed to eliminate the
use of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily
mounted using standard printed circuit board (PCB)
assembly techniques and can be removed and
replaced using standard repair procedures.
The PowerPAD package is designed so that the lead
frame die pad (or thermal pad) is exposed on the
bottom of the IC. This provides a low thermal
resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the
IC can then be soldered directly to the printed circuit
board (PCB), using the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern
including etch for the leads as well as the
thermal pad as illustrated in the Mechanical
Data section. The recommended thermal pad
dimension is 8 mm x 8 mm.
2. Place a 5-by-5 array of thermal vias in the
thermal pad area. These holes should be 13
mils in diameter. The small size prevents
wicking of the solder through the holes.
3. It is recommended to place a small number of
25 mil diameter holes under the package, but
outside the thermal pad area to provide an
additional heat path.
4. Connect all holes (both those inside and
outside the thermal pad area) to an internal
copper plane (such as a ground plane).
5. Do not use the typical web or spoke via
connection pattern when connecting the
thermal vias to the ground plane. The spoke
pattern increases the thermal resistance to the
ground plane.
6. The top-side solder mask should leave
exposed the terminals of the package and the
thermal pad area.
7. Cover the entire bottom side of the PowerPAD
vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal
pad area and all of the package terminals.
For more detailed information regarding the
PowerPAD package and its thermal properties, see
either the application brief SLMA004B (PowerPAD
Made Easy) or technical brief SLMA002 (PowerPAD
Thermally Enhanced Package).
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ADS5522
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SBAS320C – MAY 2004 – REVISED FEBRUARY 2007
ADS5522 Revision history
Revision
Date
Description
A
02/05
Production data sheet released
B
04/06
Added notes regarding the input voltage overstress requirements in the absolute max ratings table
Changed minimum recommended sampling rate to 2 MSPS
Clarified the Electrical Characteristics measurement conditions
Added min VOH and max VOL specifications
Added data valid with respect to the input clock, output clock jitter, wakeup time, output clock rise
and fall time and clock propagation delay timings
Clarified output capture test modes in Table 2
Updated the definitions section
Clarified measurement conditions for the specifications plots
Updated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate
Timings specified at various sampling speeds in Table 5 and Table 6
Information added in pin assignment table for pins RESET, OE, SEN, SDATA and SCLK
Removed the input voltage stress section
In serial programming section, note added about mandatory RESET
Latency spec corrected in timing diagram and timing table to 17.5 clocks
C
28
02/07
Added min/max spec for offset and gain error
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5522IPAP
ACTIVE
HTQFP
PAP
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5522IPAPG4
ACTIVE
HTQFP
PAP
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5522IPAPR
ACTIVE
HTQFP
PAP
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5522IPAPRG4
ACTIVE
HTQFP
PAP
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5522IPAPR
Package Package Pins
Type Drawing
HTQFP
PAP
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5522IPAPR
HTQFP
PAP
64
1000
346.0
346.0
41.0
Pack Materials-Page 2
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