HD74HC173 4-bit D-type Register (with 3-state outputs) REJ03D0583-0300 Rev.3.00 Jan 31, 2006 Description The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change state on the positive going edge of the clock. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC173P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC173FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) HD74HC173RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Data Enable Clear Clock G1 H L L L L L X L X X H X L L G2 X X X H L L Data D Output Q X X X X L H L Q0 Q0 Q0 L H Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant Rev.3.00, Jan 31, 2006 page 1 of 7 HD74HC173 Pin Arrangement M 1 Output Control Output 16 VCC Output Control Clear 15 Clear 1Q 3 1Q 1D 14 1D 2Q 4 2Q 2D 13 2D N 2 3Q 5 3Q 3D 12 3D 4Q 6 4Q 4D 11 4D CK Data Enable 10 G2 Clock 7 9 G1 GND 8 Data Input Data Enable Input (Top view) Logic Diagram 1D D C C 2D D C C 3D D C C 4D D C C G1 G2 Clock Clear Control M Control N Rev.3.00, Jan 31, 2006 page 2 of 7 Q R Q Q R VCC 2Q VCC Q Q R 1Q Q Q R VCC Q 3Q VCC 4Q HD74HC173 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±35 ±75 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf Unit V V °C ns 0 to 400 Note: Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH Ta = –40 to+85°C Unit Min Max IOZ 1.5 3.15 4.2 — — — 1.9 4.4 5.9 4.18 5.68 — — — — — — — — — — — — 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.5 1.5 3.15 4.2 — — — 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±5.0 Iin ICC 6.0 6.0 — — — — ±0.1 4.0 — — ±1.0 40 VOH VOL Off-state output current Input current Quiescent supply current Ta = 25°C Typ Max 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 VIL Output voltage Min Rev.3.00, Jan 31, 2006 page 3 of 7 Test Conditions V V V V Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –6 mA IOH = –7.8 mA IOL = 20 µA IOL = 6 mA IOL = 7.8 mA µA Vin = VIH or VIL, Vout = VCC or GND µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC173 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax tPLH, tPHL tPHL Enable time tZH, tZL Disable time tHZ, tLZ Setup time tsu Removal time trem Hold time th Pulse width tw Output rise/fall time Input capacitance tTLH, tTHL Cin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max — — — — — — — — — — — — — — — 100 20 17 90 18 15 5 5 5 80 16 14 — — — — — — — — 14 — — 14 — — 12 — — 12 — — 4 – — 0 — — –2 — — 4 — — 4 — 5 5 27 32 175 35 30 150 30 26 150 30 26 150 30 26 — — — — — — — — — — — — 60 12 10 10 — — — — — — — — — — — — — — — 125 25 21 115 23 20 5 5 5 100 20 17 — — — — 4 21 25 220 44 37 190 38 33 190 38 33 190 38 33 — — — — — — — — — — — — 75 15 13 10 ns Clock to Q ns Clear to Q ns ns ns ns ns ns ns pF Test Circuit Output 1KΩ S2 OPEN GND CL VCC TEST t PLH / t PHL S2 OPEN t ZH/ t HZ t ZL / t LZ GND VCC Note 1. CL includes probe and jig capacitance Rev.3.00, Jan 31, 2006 page 4 of 7 Test Conditions MHz HD74HC173 Waveforms • Waveform – 1 tr tf VCC 90% 50% 10% Clear tW tf tr 50% 10% 0V trem tW (H) tW (L) VCC 90% 90% Clock 50% 50% 50% 10% 10% 0V tsu th tsu th VCC 90% 90% Data 10% tf 50% 10% 50% tr 0V tPHL tPLH 90% Output QH tTHL 50% 10% 50% tPHL VOH 90% 50% 10% 50% tTLH VOL Note 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 2 tf tr 90 % 50 % 10 % t ZL Output Control VCC 90 % 50 % 10 % 0V t LZ VOH 50 % Waveform – A t ZH Waveform – B 10 % t HZ 50 % 90 % VOL VOH VOL Notes 1. Input pulse PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. Rev.3.00, Jan 31, 2006 page 5 of 7 HD74HC173 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jan 31, 2006 page 6 of 7 8° 0.50 1 0.70 1.15 0.90 HD74HC173 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 8 1 Z e *3 bp x A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 1.75 A M L1 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 1.27 e x 0.25 y 0.15 0.635 Z 0.40 L L Rev.3.00, Jan 31, 2006 page 7 of 7 8° 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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