NBSG111 2.5V/3.3VSiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com Description The NBSG111 is a 1−to−10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single−ended NECL or PECL inputs and the VMM pin is used for LVCMOS inputs. For single−ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. MARKING DIAGRAM* SG 111 LYW FCBGA−49 BA SUFFIX CASE 489A SG111 L Y W = Device Code = Wafer Lot = Year = Work Week *For further details, refer to Application Note AND8002/D ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Features • • • • • • • • • • Maximum Input Clock Frequency > 6 GHz Typical Maximum Input Data Rate > 6 Gb/s Typical 300 ps Typical Propagation Delay 60 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V RSECL Output Level (400 mV Peak−to−Peak Output), Differential Output 50 Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices VBB and VMM Reference Voltage Output © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 8 1 Publication Order Number: NBSG111/D NBSG111 1 2 3 4 5 6 7 A VEE Q9 Q9 Q8 Q8 Q7 VEE B Q0 VMM CLK1 CLK1 VCC NC Q7 C Q0 VEE VTCLK1 VTCLK1 VTSEL SEL Q6 D Q1 EN VTEN VCC VTSEL SEL Q6 E Q1 EN VTEN VTCLK0 VTCLK0 VEE Q5 F Q2 NC VCC CLK0 CLK0 VBB Q5 G VEE Q2 Q3 Q3 Q4 Q4 VEE Figure 1. BGA−49 Pinout (Top View) http://onsemi.com 2 NBSG111 Table 1. PIN DESCRIPTION Pin Name I/O A1,A7,G1,G7,C2,E6 VEE − Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. Description F3,D4,B5 VCC − Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. B2 VMM − LVCMOS Reference Voltage Output (VCC − VEE) / 2. F6 VBB − ECL Reference Voltage Output E4 VTCLK0 − Internal 50 Termination Pin for CLK0. See Table 4. (Note 1) F4 CLK0 ECL, CML, LVCMOS, LVDS, LVTTL Input E5 VTCLK0 − F5 CLK0 ECL, CML, LVCMOS, LVDS, LVTTL Input C4 VTCLK1 − B4 CLK1 ECL, CML, LVCMOS, LVDS, LVTTL Input C3 VTCLK1 − B3 CLK1 ECL, CML, LVCMOS, LVDS, LVTTL Input B1,D1,F1,G3,G5,F7, D7,B7,A5,A3 Q[0:9] RSECL Output Noninverted Differential Outputs [0:9]. Typically Terminated with 50 to VTT = VCC − 1.5 V C1,E1,G2,G4,G6,E7, C7,A6,A4,A2 Q[0:9] RSECL Output Inverted Differential Outputs [0:9]. Typically Terminated with 50 to VTT = VCC − 1.5 V D5 VTSEL − D6 SEL ECL, CML, LVCMOS, LVDS, LVTTL Input C5 VTSEL − C6 SEL ECL, CML, LVCMOS, LVDS, LVTTL Input D3 VTEN − D2 EN ECL, CML, LVCMOS, LVDS, LVTTL Input E3 VTEN − E2 EN ECL, CML, LVCMOS, LVDS, LVTTL Input F2,B6 NC − Noninverted Differential Input CLK0. Internal 75 k to VEE. Internal 50 Termination Pin for CLK0. See Table 4. (Note 1) Inverted Differential Input CLK0. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin 1. See Table 4. (Note 1) Noninverted Differential Input CLK1. Internal 75 k to VEE. Internal 50 Termination Pin for CLK1. See Table 4. (Note 1) Inverted Differential Input CLK1. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin for SEL. See Table 4. (Note 1) Noninverted Differential Select Logic Input. Internal 75 k to VEE. Internal 50 Termination Pin for SEL. See Table 4. (Note 1) Inverted Differential Select Logic Input. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin for EN. See Table 4. (Note 1) Noninverted Differential Output Enable Pin. Internal 75 k to VEE. Internal 50 termination Pin for EN. See Table 4. (Note 1) Inverted Differential Output Enable Pin. Internal 75 k to VEE and 36.5 k to VCC. No Connect. The NC Pins are Electrically Connected to the Die and ”MUST BE” Left Open. 1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self−oscillation. http://onsemi.com 3 NBSG111 Table 2. FUNCTION TABLE SEL EN Active Input L L H H L H L H Disabled Outputs CLK0, CLK0 Disabled Outputs CLK1, CLK1 2. SEL/EN are the inverse of SEL/EN unless specified otherwise. Q0 (B1) Q0 (C1) Q1 (D1) Q1 (E1) (C5) VTSEL (C6) SEL Q2 (F1) R1 RTIN Q2 (G2) R2 Q3 (G3) (E4) VTCLK0 (F4) CLK0 (F5) CLK0 (E5) VTCLK0 (B4) CLK1 (C4) VTCLK1 (B3) CLK1 (C3) VTCLK1 (D6) SEL (D5) VTSEL (D3) VTEN RTIN R2 RTIN RTIN R2 RTIN (D2) EN R1 0 R2 RTIN R2 Q4 (G5) R2 R2 R1 Q3 (G4) RTIN Q4 (G6) SYNC Q5 (F7) Q5 (E7) 1 (E2) EN (E3) VTEN R1 Q6 (D7) RTIN R2 Q6 (C7) (F6) VBB Q7 (B7) (A1, A7, G1, G7) VEE Q7 (A6) Q8 (A5) Q8 (A4) (B5, D4, F3) VCC Q9 (A3) (B2) VMM Q9 (A2) Figure 2. Logic Diagram Table 3. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL to VCC LVDS Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Together AC−COUPLED Bias VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS See Text on Page 1. Unused Differential Input Switching Voltage Reference Range is from VEE + 1125 mV to VCC − 75 mV http://onsemi.com 4 NBSG111 Table 4. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor, R2 (CLK0, CLK0, CLK1, CLK1, SEL, SEL, EN, EN) 75 k Internal Input Pullup Resistor, R1 (CLK0, CLK1, SEL, EN) 36.5 k ESD Protection > 2 kV > 100 V > 1 kV Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 3) Flammability Rating Level 3 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 479 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units 3.6 V 3.6 −3.6 V V −3.6 V 2.8 |VCC − VEE| V V VCC Positive Power Supply VEE = 0 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V VEE Negative Power Supply VCC = 0 V VINPP Differential Input Voltage |CLK − CLK| VCC − VEE w 2.8 V VCC − VEE t 2.8 V IOUT Output Current Continuous Surge 25 50 mA mA IIN Input Current Through RT (50 Resistor) Static Surge 45 80 mA mA IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range −40 to +70 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 LFPM 500 LFPM 49 FCBGA 49 FCBGA 67 57 °C/W °C/W JC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) 49 FCBGA 2 to 4 °C/W Tsol Wave Solder < 15 sec. 225 °C VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 5 NBSG111 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 5) −40°C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 110 70 85 110 70 85 110 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 6) 1365 1520 1615 1410 1530 1660 1435 1560 1685 mV VOUTPP Output Voltage Amplitude 305 420 545 305 420 545 305 420 545 mV VIH Input HIGH Voltage (Single−Ended) (Notes 8 and 9) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 8 and 10) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB PECL Output Voltage Reference 1025 1100 1265 1025 1100 1265 1025 1100 1265 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 2.5 1.2 2.5 1.2 2.5 V VMM LVCMOS Output Voltage Reference (@ 2.5 VCC) RTIN Internal Input Termination Resistor IIH IIL 1.2 mV 1050 1250 1450 1050 1250 1450 1050 1250 1450 45 50 55 45 50 55 45 50 55 Input HIGH Current (@ VIH) 30 100 30 100 30 100 A Input LOW Current (@ VIL) 25 100 25 100 25 100 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 6 NBSG111 Table 7. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 11) −40°C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 110 70 85 110 70 85 110 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 6) 2165 2320 2415 2210 2330 2460 2235 2360 2485 mV VOUTPP Output Voltage Amplitude 305 420 545 305 420 545 305 420 545 mV VIH Input HIGH Voltage (Single−Ended) (Notes 8 and 9) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 8 and 10) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB PECL Output Voltage Reference 1825 1900 2065 1825 1900 2065 1825 1900 2065 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 3.3 1.2 3.3 1.2 3.3 V VMM LVCMOS Output Voltage Reference (@ 3.3 VCC) RTIN Internal Input Termination Resistor IIH IIL 1.2 mV 1450 1650 1850 1450 1650 1850 1450 1650 1850 45 50 55 45 50 55 45 50 55 Input HIGH Current (@ VIH) 30 100 30 100 30 100 A Input LOW Current (@ VIL) 25 100 25 100 25 100 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. VMM varies (VCC − VEE) / 2 with VCC and VEE. 6. All outputs loaded with 50 to VCC − 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 8. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 9. VIH cannot exceed VCC. 10. VIL always w VEE. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. VMM varies (VCC − VEE) / 2 with VCC and VEE. *Typicals used for testing purposes. http://onsemi.com 7 NBSG111 Table 8. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 12) −40°C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 70 85 110 70 85 110 70 85 110 mA VOH Output HIGH Voltage (Note 13) −1135 −980 −885 −1090 −970 −840 −1065 −940 −815 mV VOUTPP Output Voltage Amplitude 305 420 545 305 420 545 305 420 545 mV VIH Input HIGH Voltage (Single−Ended) (Notes 15 and 16) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 15 and 17) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB NECL Output Voltage Reference −1475 −1400 −1235 −1475 −1400 −1235 −1475 −1400 −1235 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) VMM LVCMOS Output Voltage Reference (@ − 2.5 VEE) (@ − 3.3 VEE) RTIN Internal Input Termination Resistor IIH Input HIGH Current (@ VIH) IIL Input LOW Current (@ VIL) VEE+1.2 −1450 −1850 −1250 −1650 45 0.0 VEE+1.2 −1050 −1450 −1450 −1850 −1250 −1650 50 55 45 30 100 25 100 0.0 VEE+1.2 0.0 −1050 −1450 V mV −1050 −1450 −1450 −1850 −1250 −1650 50 55 45 50 55 30 100 30 100 A 25 100 25 100 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. 13. All outputs loaded with 50 to VCC − 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 16. VIH cannot exceed VCC. 17. VIL always w VEE. *Typicals used for testing purposes. http://onsemi.com 8 NBSG111 Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic fin < 3 GHz fin = 5.5 GHz 25°C Min Typ Max 305 180 420 250 250 430 400 300 550 450 350 700 500 2 5 15 15 20 85 70°C Min Typ Max 305 150 420 220 250 430 400 300 550 450 350 700 500 2 5 15 15 20 85 Min Typ Max 305 100 420 200 250 430 400 300 600 480 350 750 550 ps 2 5 15 15 20 85 ps Unit VOUTPP Output Voltage Amplitude (See Figure 3) (Note 18) tPLH, tPHL Propagation Delay to Output Differential Output Enable Clock Select tSKEW Duty Cycle Skew (Note 19) Within−Device Skew (Note 20) Device−to−Device Skew (Note 21) tS Setup Time to CLK (EN to Selected CLK0:1) 110 70 110 70 115 80 ps tH Hold Time (EN to Selected CLK0:1) 110 70 110 70 115 80 ps tJITTER RMS Random Clock Jitter(Figure 3) (Note 23) fin = 5 GHz Peak−to−Peak Data Dependent Jitter (Note 24) fin = 5 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 22) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz Q, Q 0.5 2.0 0.5 2.0 0.5 mV 2.0 ps 14 75 40 2600 75 80 40 60 60 2600 75 80 40 2600 60 80 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 18. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC − 1.5 V. Input edge rates 40 ps (20% − 80%). 19. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform (Figure 4). 20. Within−Device skew is measured between outputs under identical transitions and conditions on any one device. 21. Device−to−Device skew for identical transitions at identical VCC levels. 22. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC −VEE t 2600 mV). 23. Additive RMS jitter with 50% duty cycle clock signal at 5 GHz. 24. Additive Peak−to−Peak jitter with input NRZ data at PRBS 231−1 at 5 Gb/s. http://onsemi.com 9 NBSG111 10.0 9.0 8.0 Q AMP (mV) 450 7.0 6.0 3.3 V 350 5.0 4.0 2.5 V RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) 550 3.0 250 2.0 RMS JITTER (ps) 150 1 2 1.0 3 4 5 6 0.0 INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 4. AC Reference Measurement Q Zo = 50 D Receiver Device Driver Device Q D Zo = 50 50 50 VTT VTT = VCC − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping † NBSG111BA FCBGA−49 100 Units / Tray NBSG111BAR2 FCBGA−49 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NBSG111 PACKAGE DIMENSIONS FCBGA−49 BA SUFFIX PLASTIC 8x8 mm (1.0 mm pitch) BGA FLIP CHIP PACKAGE CASE 489A−02 ISSUE A A B NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M−1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE C. 4. DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 6. 489A−01 OBSOLETE, NEW STANDARD 489A−02. A D A2 ÉÉ ÉÉ TERMINAL A1 CORNER Z E 4X DIM A A1 A2 b D D1 E E1 e Z DETAIL A 0.15 C D1 e FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA NOTE 5 A B e E1 49 X 0.20 C b NOTE 3 C 0.15 M C A B D 0.08 M C E NOTE 4 0.12 C G 6 5 4 3 2 C SEATING PLANE F 7 MILLIMETERS MIN MAX −−− 1.40 0.3 0.5 0.91 REF 0.40 0.60 8.00 BSC 6.00 BSC 8.00 BSC 6.00 BSC 1.00 BSC 49 X 1 VIEW Z−Z A1 DETAIL A (ROTATED 90 _ C.W.) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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