LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 LMH6580/LMH6581 8x4 500 MHz Analog Crosspoint Switch, Gain of 1, Gain of 2 Check for Samples: LMH6580, LMH6581 FEATURES DESCRIPTION • • • The LMH™ family of products is joined by the LMH6580 and the LMH6581, high speed, nonblocking, analog, crosspoint switches. The LMH6580/LMH6581 are designed for high speed, DC coupled, analog signals such as high resolution video (UXGA and higher). The LMH6580/LMH6581 each has eight inputs and four outputs. The non-blocking architecture allows any output to be connected to any input, including an input that is already selected. With fully buffered inputs the LMH6580/LMH6581 can be impedance matched to nearly any source impedance. The buffered outputs of the LMH6580/LMH6581 can drive up to two back terminated video loads (75Ω load). The outputs and inputs also feature high impedance inactive states allowing high performance input and output expansion for array sizes such as 8 x 8 or 16 x 4 by combining two devices. The LMH6580/LMH6581 are controlled with a 4 pin serial interface that can be configured as a 3 wire interface. Both serial mode and addressed modes are available. 1 23 • • • • • • • • • 8 Inputs and 4 Outputs 48-pin TQFP Package −3 dB Bandwidth (VOUT = 2 VPP, RL = 1 kΩ) 500 MHz −3 dB Bandwidth (VOUT = 2 VPP, RL = 150Ω) 450 MHz Fast Slew Rate 2100 V/μs Channel to Channel Crosstalk (10/100 MHz) −70/ −52 dBc All Hostile Crosstalk (10/100 MHz) −55/−45 dBc Easy to Use Serial Programming 4 Wire Bus Two Programming Modes Serial & Addressed Modes Symmetrical Pinout Facilitates Expansion. Output Current ±70 mA Two Gain Options AV = 1 or AV = 2 APPLICATIONS • • • • • • • • Studio Monitoring/Production Video Systems Conference Room Multimedia Video Systems KVM (Keyboard Video Mouse) Systems Security/Surveillance Systems Multi-Antenna Diversity Radio Video Test Equipment Medical Imaging Wide-Band Routers & Switches The LMH6580/LMH6581 come in 48-pin TQFP packages. They also have diagonally symmetrical pin assignments to facilitate double sided board layouts and easy pin connections for expansion. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMH is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com GND IN0 VEE VEE IN1 VCC VCC IN2 VEE GND GND IN3 Connection Diagram VEE GND OUT3 IN4 GND GND VEE VCC IN5 VCC VCC GND VCC OUT2 VEE IN6 BCST VEE CFG IN7 CLK DIN DOUT CS RST VEE OUT1 GND VCC VCC GND VEE OUT0 GND MODE VEE SWITCH MATRIX 4 OUTPUTS 8 INPUTS Block Diagram 36 CONFIGURATION REGISTER CFG BCST 16 DATA IN CS CLK LOAD REGISTER RST DATA OUT MODE These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) ESD Tolerance (3) Human Body Model 2000V Machine Model 200V VS ±6V IIN (Input Pins) ±20 mA IOUT See (4) Input Voltage Range − V to V+ Maximum Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical Characteristics and ±5V Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum output current (IOUT) is determined by device power dissipation limitations. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. OPERATING RATINGS (1) Temperature Range (2) −40°C to +85°C Supply Voltage Range ±3V to ±5.5V Thermal Resistance 48-Pin TQFP (1) (2) θJA 44°C/W θJC 12°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see ±3.3V Electrical Characteristics and ±5V Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. ±3.3V ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Performance SSBW −3 dB Bandwidth LSBW GF 0.1 dB Gain Flatness VOUT = 0.5 VPP 425 LMH6580 VOUT = 1 VPP, LMH6581 V OUT = 2 VPP, RL = 1 kΩ 500 LMH6580 VOUT = 1 VPP, LMH6581 VOUT = 2 VPP, RL = 150Ω 450 LMH6580 VOUT = 1 VPP, LMH6581 V OUT = 2 VPP, RL = 150Ω 70 MHz MHz Time Domain Response tr Rise Time LMH6580 1V Step, LMH6581 2V Step, 10% to 90% 3.1 ns tf Fall Time LMH6580 1V Step, LMH6581 2V Step, 10% to 90% 1.4 ns (1) (2) (3) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensured parametric performance is indicated in the electrical tables under conditions different than those tested. Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 3 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com ±3.3V ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±3.3V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol OS Parameter Overshoot SR ts Min (2) Conditions 2V Step (4) Slew Rate LMH6580, 2 VPP, 40% to 60% Slew Rate LMH6581, 2 VPP, 40% to 60% (4) Settling Time 2V Step, VOUT within 0.5% Typ (3) Max (2) Units <1 % 900 V/µs 1700 V/µs 7 ns dBc Distortion And Noise Response HD2 2nd Harmonic Distortion 2 VPP, 10 MHz −76 HD3 3rd Harmonic Distortion 2 VPP, 10 MHz −76 dBc en Input Referred Voltage Noise >1 MHz 12 nV/ √Hz in Input Referred Noise Current >1 MHz 2 pA/ √Hz XTLK Crosstalk All Hostile, f = 100 MHz −45 dBc ISOL Off Isolation f = 100 MHz −60 dBc Static, DC Performance AV Gain VOS LMH6581 1.986 2.00 2.014 LMH6580 0.994 1.00 1.005 ±3 ±17 Input Offset Voltage (5) TCVOS Input Offset Voltage Average Drift See IB Input Bias Current Non-Inverting (6) −5 µA TCIB Input Bias Current Average Drift Non-Inverting (5) −12 nA/°C VO Output Voltage Range LMH6581, RL = 100Ω ±1.8 ±2.1 LMH6580, RL = 100Ω ±1.24 ±1.3 LMH6581, RL = ∞Ω, (7) ±2.08 ±2.2 LMH6580 RL = ∞Ω, ±1.25 ±1.3 VO Output Voltage Range 38 mV µV/°C V V −45 PSRR Power Supply Rejection Ratio ICC Positive Supply Current RL = ∞ 50 60 dBc mA IEE Negative Supply Current RL = ∞ 50 56 mA Tri State Supply Current RST Pin > 2.0V 10 13 mA 100 Miscellaneous Performance RIN Input Resistance Non-Inverting CIN Input Capacitance Non-Inverting 1 pF RO Output Resistance Enabled Closed Loop, Enabled 300 mΩ RO Output Resistance Disabled LMH6580 50 LMH6581 CMVR Input Common Mode Voltage Range IO Output Current 1100 Sourcing, VO = 0 V 1350 kΩ 1500 kΩ ±1.3 V ±50 mA Digital Control VIH Input Voltage High VIL Input Voltage Low VOH Output Voltage High >2.0 VOL Output Voltage Low <0.4 V Switching Time 15 ns TS Setup Time 7 ns TH Hold Time 7 ns (4) (5) (6) (7) 4 2.0 V 0.8 V V Slew Rate is the average of the rising and falling edges. Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Negative input current implies current flowing out of the device. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 ±5V ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Min (2) Conditions Typ (3) Max (2) Units Frequency Domain Performance SSBW −3 dB Bandwidth LSBW VOUT = 0.5 VPP (4) 450 LMH6580 VOUT = 1 VPP, LMH6581 VOUT = 2 VPP, RL = 1 kΩ 500 LMH6580 VOUT = 1 VPP, LMH6581 VOUT = 2 VPP, RL = 150Ω 450 MHz GF 0.1 dB Gain Flatness LMH6580, VOUT = 1 VPP, LMH6581, VOUT = 2 VPP, RL = 150Ω 100 MHz DG Differential Gain RL = 150Ω, 3.58 MHz/4.43 MHz .05 % DP Differential Phase RL = 150Ω, 3.58 MHz/4.43 MHz .05 deg LMH6580 2V, Step, 10% to 90% 2.8 LMH6581 2V, Step, 10% to 90% 1.2 Time Domain Response tr Rise Time ns tf Fall Time 2V Step, 10% to 90% 1.6 ns OS Overshoot 2V Step <1 % (5) 1200 V/µs 2100 V/µs 6 ns dBc SR Slew Rate LMH6580, 2 VPP, 40% to 60% SR Slew Rate LMH6581, 6 VPP, 40% to 60% (5) ts Settling Time 2V Step, VOUT Within 0.5% Distortion And Noise Response HD2 2nd Harmonic Distortion 2 VPP, 5 MHz −80 HD3 3rd Harmonic Distortion 2 VPP, 5 MHz −70 dBc en Input Referred Voltage Noise >1 MHz 12 nV/ √Hz in Input Referred Noise Current >1 MHz 2 pA/ √Hz XTLK Cross Talk All Hostile, f = 100 MHz −45 dBc Channel to Channel, f = 100 MHz −52 dBc f = 100 MHz −65 dBc ISOL Off Isolation Static, DC Performance AV Gain LMH6581 1.986 2.00 2.014 Vos Input Offset Voltage LMH6580 0.995 1.00 1.005 ±2 TCVos Input Offset Voltage Average Drift See (6) ±17 IB Input Bias Current Non-Inverting (7) 38 −5 (6) −12 TCIB Input Bias Current Average Drift Non-Inverting VO Output Voltage Range LMH681, RL = 100Ω ±3.4 ±3.6 LMH6580, RL = 100Ω ±2.9 ±3.0 LMH6581, RL = ∞Ω ±3.7 ±3.9 LMH6580, RL = ∞Ω ±2.9 ±3.0 DC −42 −45 VO Output Voltage Range PSRR (1) (2) (3) (4) (5) (6) (7) Power Supply Rejection Ratio mV µV/°C ±12 µA nA/°C V V dBc Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensured parametric performance is indicated in the electrical tables under conditions different than those tested. Room Temperature limits are 100% production tested at 25°C. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. This parameter is specified by design and/or characterization and is not tested in production. Slew Rate is the average of the rising and falling edges. Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Negative input current implies current flowing out of the device. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 5 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com ±5V ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 100Ω; Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units XTLK DC Crosstalk Rejection DC, Channel to Channel −62 −90 OISO DC Off Isloation DC −60 −90 ICC Positive Supply Current RL = ∞ 54 66 mA IEE Negative Supply Current RL = ∞ 50 62 mA Tri State Supply Current RST Pin > 2.0V 14 17 mA dBc dBc Miscellaneous Performance RIN Input Resistance Non-Inverting 100 kΩ CIN Input Capacitance Non-Inverting 1 pF RO Output Resistance Enabled Closed Loop, Enabled 300 mΩ RO Output Resistance Disabled LMH6580, Resistance to Ground 50 LMH6581, Resistance to Ground CMVR Input Common Mode Voltage Range IO Output Current 1100 Sourcing, VO = 0 V ±60 1300 1500 kΩ ±3.0 V ±70 mA Digital Control VIH Input Voltage High VIL Input Voltage Low 2.0 V VOH Output Voltage High >2.4 VOL Output Voltage Low 0.8 V V <0.4 V Switching Time 15 ns TS Setup Time 5 ns TH Hold Time 5 ns 6 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 1 VPP Frequency Response 1 VPP Frequency Response 1 1 -1 -2 0 PHASE -45 -3 -4 -90 + GAIN (dB) -1 -2 0 PHASE -45 -3 -4 V = +5V -90 + PHASE (°) GAIN 0 PHASE (°) GAIN (dB) GAIN 0 V = +3.3V -5 V- = -5V -6 VOUT = 1 VPP RL = 150: -7 1 10 -135 -5 V- = -3.3V -135 -180 -6 VOUT = 1 VPP RL = 150: -7 1 10 -180 -225 1000 100 -225 1000 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 1. Figure 2. 1 VPP Frequency Response Broadcast 1 VPP Frequency Response Broadcast 2 1 1 0 GAIN GAIN 0 PHASE -2 -45 -3 -90 + -2 -3 -45 -4 V = +5V -90 + V = +3.3V - V = -5V -5 VOUT = 1 VPP RL = 150: -6 0.1 1 10 -135 -5 -180 -6 VOUT = 1 VPP RL = 150: -7 0.1 1 -225 1000 100 -135 - V = -3.3V FREQUENCY (MHz) Frequency Response 1 kΩ Load -225 1000 Frequency Response 1kΩ Load 1 GAIN GAIN 0 -1 -1 -2 0 PHASE -3 -45 -90 + GAIN (dB) 0 PHASE (°) GAIN (dB) 100 Figure 4. 1 -2 0 PHASE -3 -45 + -4 V = +3.3V -5 V = -3.3V V = +5V -5 10 FREQUENCY (MHz) Figure 3. -4 -180 -90 PHASE (°) -4 0 PHASE PHASE (°) -1 GAIN (dB) -1 PHASE (°) GAIN (dB) 0 - -135 - V = -5V -6 VOUT = 1 VPP RL = 1 k: -7 0.1 1 -135 VOUT = 1 VPP -180 10 -225 1000 100 -6 -180 RL = 1 k: -7 0.1 1 10 100 -225 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Figure 6. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 7 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued) Frequency Response with Input Expansion Frequency Response with Input Expansion 2 1 1 0 GAIN GAIN -2 -45 + -3 V = +5V -90 - -2 0 PHASE -3 -45 + -4 V = +3.3V -90 - -4 V = -5V VOUT = 1 VPP -5 R = 150: -135 -180 L -6 0.1 GAIN (dB) 0 PHASE PHASE (°) GAIN (dB) -1 1 10 -225 1000 100 -5 V = -3.3V VOUT = 1 VPP -6 R = 150: -135 -180 L -7 0.1 1 10 Figure 7. 2 VPP Pulse Response 1.5 1 1 0.5 0.5 VOUT (V) VOUT (V) 2 VPP Pulse Response 0 + V = +5V 0 + -0.5 V = +3.3V -1 V = -3.3V RL = 100: - - V = -5V RL = 100: SINGLE CHANNEL -1.5 0 5 SINGLE CHANNEL -1.5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 10. 2 VPP Pulse Response, Broadcast Mode 2 VPP Pulse Response, Broadcast Mode 1.5 1.5 1 1 0.5 0.5 0 VOUT (V) VOUT (V) Figure 9. + V = +5V - V = -5V RL = 100: -0.5 -1.5 0 5 0 + V = +3.3V - V = -3.3V RL = 100: -0.5 BROADCAST -1 8 -225 1000 Figure 8. 1.5 -1 100 FREQUENCY (MHz) FREQUENCY (MHz) -0.5 PHASE (°) -1 0 BROADCAST -1 10 15 20 25 30 35 40 45 50 -1.5 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued) 1 VPP Pulse Response 0.75 0.5 0.5 0.25 0.25 VOUT (V) VOUT (V) 1 VPP Pulse Response 0.75 0 + -0.25 V = +5V 0 + -0.25 V = +3.3V -0.5 V = -3.3V RL = 100: - - V = -5V RL = 100: -0.5 SINGLE CHANNEL SINGLE CHANNEL -0.75 0 5 -0.75 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 13. Figure 14. All Hostile Crosstalk -30 -50 -40 CROSSTALK (dBc) CROSSTALK (dBc) Channel to Channel Crosstalk -40 -60 -70 -80 INPUTS ONLY -50 OUTPUTS ONLY -60 -70 -80 INPUTS & OUTPUTS -90 -90 -100 0.1 1 10 100 -100 0.1 1000 1 FREQUENCY (MHz) 100 1000 Figure 15. Figure 16. Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency -50 -50 + V = +5V - V = -5V RL = 100: -60 VOUT = 3V -70 VOUT = 1V -80 VOUT = 0.5V DISTORTION (dBc) -60 + V = +5V - V = -5V DISTORTION (dBc) 10 FREQUENCY (MHz) RL = 100: -70 VOUT = 1V VOUT = 3V -80 -90 -90 -100 -100 VOUT = 0.5V 1 10 100 1 FREQUENCY (MHz) 10 100 FREQUENCY (MHz) Figure 17. Figure 18. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 9 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued) Second Order Distortion (HD2) vs. Frequency -50 Third Order Distortion (HD3) vs. Frequency -50 + + V = +3.3V V = +3.3V - - V = -3.3V -60 RL = 100: DISTORTION (dBc) DISTORTION (dBc) -60 VOUT = 2V V = -3.3V -70 VOUT = 2V VOUT = 1V -80 RL = 100: -70 VOUT = 1V -80 VOUT = 0.5V -90 -90 VOUT = 0.5V -100 10 1 -100 100 10 1 FREQUENCY (MHz) Figure 19. Figure 20. Positive Voltage Swing over Temperature Negative Voltage Swing over Temperature 3.5 -2.5 + + V = +5V V = +5V 100°C 3.25 V = -5V 100: LOAD - OUTPUT VOLTAGE (V) - OUTPUT VOLTAGE (V) 100 FREQUENCY (MHz) 25°C 3 -40°C 2.75 V = -5V 100: LOAD -2.75 -40°C -3 25°C -3.25 100°C 2.5 2.5 2.75 3 3.25 -3.5 -3.5 3.5 -3.25 INPUT VOLTAGE (V) Figure 21. + 100°C - 25°C 1.25 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) V = -3.3V 100: LOAD -40°C 1 1 + V = +3.3V - 0.75 0.75 1.25 1.5 1.75 -1 V = -3.3V 100: LOAD -40°C -1.25 -1.5 25°C 100°C -1.75 -1.75 -1.5 Figure 23. Submit Documentation Feedback -1.25 -1 -0.75 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 10 -2.5 Negative Voltage Swing over Temperature -0.75 V = +3.3V 1.5 -2.75 Figure 22. Positive Voltage Swing over Temperature 1.75 -3 INPUT VOLTAGE (V) Figure 24. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS LMH6580 (continued) Enabled Output Impedance 100 Enabled Output Impedance 100 + + V = +5V V = +3.3V - - V = -5V V = -3.3V 10 |Z| (:) |Z| (:) 10 1 0.1 0.1 1 1 10 100 0.1 0.1 1000 1 10 FREQUENCY (MHz) Figure 25. Figure 26. Disabled Output Impedance 100 + V = +3.3V - - V = -3.3V V = -5V 10 10 |Z| (k:) |Z| (k:) 1000 Disabled Output Impedance 100 + V = +5V 1 0.1 0.01 0.1 100 FREQUENCY (MHz) 1 0.1 1 10 100 0.01 0.1 1000 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 27. Figure 28. 1000 Switching Time 1 4 0.5 3 OUTPUT (V) 2.5 2 0 1.5 1 -0.5 CFG 0.5 0 -1 DISABLE TO ENABLE -0.5 CONFIGURE PIN VOLTAGE (V) 3.5 ENABLE TO DISABLE -1.5 -50 -40 -30 -20 -10 0 -1 10 20 30 40 50 TIME (ns) Figure 29. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 11 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 2 VPP Frequency Response 2 VPP Frequency Response 1 GAIN GAIN -1 0 -2 PHASE -3 -45 -4 -90 -5 VS = ±5V -135 -6 VOUT = 2 VPP -180 NORMALIZED GAIN (dB) 0 PHASE (°) 1 10 100 0 -2 PHASE -3 -45 -4 -90 -5 1 10 FREQUENCY (MHz) Figure 30. Figure 31. Large Signal Bandwidth 0 PHASE -3 -45 -4 -90 -5 VS = ±5V -135 VOUT = 2 VPP -180 -7 1 10 100 FREQUENCY (MHz) -225 1000 -1 -2 0 PHASE -3 -45 -4 -90 -5 V = ±3.3V S -135 -6 VOUT = 2 VPP RL = 1 k: -7 1 10 -180 Figure 33. Small Signal Bandwidth Small Signal Bandwidth 1 135 1 GAIN 0 PHASE -3 -45 -4 -90 -5 VS = ±5V -135 -6 VOUT = 0.5 VPP -180 RL = 150: -7 1 10 100 -225 1000 PHASE (°) -1 NORMALIZED GAIN (dB) GAIN -2 -225 1000 FREQUENCY (MHz) Figure 32. NORMALIZED GAIN (dB) 100 PHASE (°) -2 NORMALIZED GAIN (dB) 0 PHASE (°) NORMALIZED GAIN (dB) GAIN GAIN -1 0 -225 1000 1 RL = 1 k: 12 100 FREQUENCY (MHz) Large Signal Bandwidth -6 -180 RL = 150: -7 -225 1000 1 0 -135 VS = ±3.3V -6 VOUT = 2 VPP RL = 150: -7 -1 0 90 -1 45 0 -2 PHASE -45 -3 -4 -90 + V = +3.3V -5 V- = -3.3V -135 -6 VOUT = 0.5 VPP RL = 150: -7 1 10 -180 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Figure 35. Submit Documentation Feedback PHASE (°) NORMALIZED GAIN (dB) 0 PHASE (°) 1 -225 1000 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued) Frequency Response 1 kΩ Load Group Delay 1 2.00 VS = ±5V GAIN 1.50 VOUT = 1V -1 VS = ±3.3V -2 -3 0 PHASE -45 -90 -4 VS = ±3.3V -5 -6 VOUT = 2 VPP RL = 1 k: -7 10 -135 100 GROUP DELAY (ns) VS = ±5V PHASE (°) NORMALIZED GAIN (dB) 0 1.00 0.50 0.00 -0.50 -1.00 -180 -1.50 -225 1000 -2.00 0 100 FREQUENCY (MHz) 200 Figure 36. 2 VPP Pulse Response 500 2 VPP Pulse Response 1.5 1 1.0 0.5 0.5 VOUT (V) VOUT (V) 400 Figure 37. 1.5 0 -0.5 300 FREQUENCY (MHz) VS = ±3.3V SINGLE CHANNEL 0.0 -0.5 + V = +5V - V = -5V -1 -1.5 -1.0 RL = 100: SINGLE CHANNEL 0 5 -1.5 10 15 20 25 30 35 40 45 50 1.5 1.5 1.0 1 0.5 0.5 VOUT (V) VOUT (V) 2 0.0 -0.5 -1 -1.5 VS = ±5V SINGLE CHANNEL 20 25 35 40 VS = ±5V BROADCAST 0 -1.5 15 30 -0.5 -1.0 10 25 4 VPP Pulse Response Broadcast 2.0 5 20 Figure 39. 2.5 0 15 Figure 38. 4 VPP Pulse Response -2.5 10 TIME (ns) 2.5 -2.0 5 0 TIME (ns) -2 -2.5 30 35 40 0 5 10 15 TIME (ns) TIME (ns) Figure 40. Figure 41. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 20 25 30 Submit Documentation Feedback 13 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued) 4 VPP Pulse Response 6 VPP Pulse Response 2.5 4 2.0 3 1.5 2 0.5 VOUT (V) VOUT (V) 1.0 0.0 -0.5 1 0 -1 -1.0 -2 -1.5 -3 VS = ±3.3V SINGLE CHANNEL -2.0 -2.5 VS = ±5V SINGLE CHANNEL -4 0 5 10 15 20 25 30 35 40 5 0 10 15 TIME (ns) 20 25 30 35 40 TIME (ns) Figure 42. Figure 43. Off Isolation All Hostile Crosstalk -30 -40 OUTPUTS ONLY -40 CROSSTALK (dBc) OFF ISOLATION (dBc) -50 -60 -70 -80 -50 INPUTS ONLY -60 -70 -80 INPUTS & OUTPUTS -90 -90 -100 0.1 1 10 100 -100 0.1 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 44. Figure 45. Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency -60 -55 + V = +5V -60 VOUT = 2V RL = 100: -70 VOUT = 4V -85 VOUT = 2V -80 -85 DISTORTION (dBc) DISTORTION (dBc) -65 V- = -5V -65 VOUT = 0.5V -70 -75 VOUT = 4V -80 + V = +5V -90 - -85 V = -5V VOUT = 0.5V -95 -90 1 14 RL = 100: 10 100 10 1 FREQUENCY (MHz) FREQUENCY (MHz) Figure 46. Figure 47. Submit Documentation Feedback 100 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued) Second Order Distortion vs. Frequency Third Order Distortion vs. Frequency -55 -55 + V = +3.3V -60 V- = -3.3V -60 -65 DISTORTION (dBc) DISTORTION (dBc) VOUT = 2V VOUT = 0.5V -70 -75 VOUT = 4V -80 + RL = 100: -65 VOUT = 3V -70 -75 VOUT = 2V -80 VOUT = 0.5V V = +5V - -85 -85 V = -5V RL = 100: -90 10 1 -90 100 10 1 FREQUENCY (MHz) Figure 48. Figure 49. No Load Output Swing Positive Swing over Temperature 3.75 4 100°C OUTPUT VOTLAGE (V) VS = ±5V 3 NO LOAD OUTPUT VOLTAGE (V) 100 FREQUENCY (MHz) 2 1 0 -1 -2 3.5 25°C -40°C 3.25 3 + V = +5V - -3 -4 -3 -2 -1 0 1 2 V = -5V 100: LOAD 2.75 1.5 3 INPUT VOLTAGE (V) 1.75 Figure 50. No Load Output Swing + 2.5 - 2 V = -5V 100: LOAD OUTPUT VOLTAGE (V) OUTPUT VOTLAGE (V) V = +5V -3 -3.25 -40°C 2.25 Figure 51. Negative Swing Over Temperature -2.25 2 INPUT VOLTAGE (V) 25°C -3.5 VS = ±3.3V NO LOAD 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -3.75 -2.25 100°C -2 -1.75 -1.5 -2.5 -2 -1 0 1 2 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 52. Figure 53. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 15 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LMH6581 (continued) Positive Swing over Temperature Negative Swing over Temperature 2.25 -1.25 + V = +3.3V - OUTPUT VOTLAGE (V) OUTPUT VOTLAGE (V) 100°C 2 -40°C 25°C 1.75 1.5 + V = -3.3V 100: LOAD -1.5 -1.75 25°C -40°C -2 V = +3.3V - V = -3.3V 100: LOAD 1.25 0.75 1 1.25 100°C -2.25 -1.5 1.5 -1.25 INPUT VOLTAGE (V) Figure 54. Enabled Output Impedance Disabled Output Impedance 10000 10 1000 |z| (:) |z| (:) -0.75 Figure 55. 100 1 0.1 0.01 0.1 -1 INPUT VOLTAGE (V) 100 10 1 10 100 1 0.1 1000 1 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) Figure 56. Figure 57. Switching Time 4 1 3 0.5 OUTPUT (V) 2.5 2 0 1.5 1 -0.5 CFG 0.5 0 -1 DISABLE TO ENABLE -0.5 ENABLE TO DISABLE -1 -1.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 CONFIGURE PIN VOLTAGE (V) 3.5 TIME (ns) Figure 58. 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 APPLICATION INFORMATION INTRODUCTION The LMH6580/LMH6581 are high speed, fully buffered, non- blocking, analog crosspoint switches. Having fully buffered inputs allows the LMH6580/LMH6581 to accept signals from low or high impedance sources without the worry of loading the signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission lines with no external components other than the termination resistor. When disabled, the outputs are in a high impedance state. The LMH6580/LMH6581 can have any input connected to any (or all) output(s). Conversely, a given output can have only one associated input. INPUT AND OUTPUT EXPANSION The LMH6580/LMH6581 have high impedance inactive states for both inputs and outputs allowing maximum flexibility for crosspoint expansion. In addition the LMH6580/LMH6581 employ diagonal symmetry in pin assignments. The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board. As an example two LMH6580/LMH6581 chips can be combined on one board to form either an 8 x 8 crosspoint or a 16 x 4 crosspoint. To make an 8 x 8 crosspoint all 8 input pins would be tied together (Input 0 on side 1 to input 7 on side 2 and so on) while the 4 output pins on each chip would be left separate. To make the 16 x 4 crosspoint, the 4 outputs would be tied together while all 16 inputs would remain independent. In the 16 x 4 configuration it is important not to have 2 connected outputs active at the same time. With the 8 x 8 configuration, on the other hand, having two connected inputs active is a valid state. Crosspoint expansion as detailed above has the advantage that the signal will go through only one crosspoint. Expansion methods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion. Output expansion as shown in Figure 59 is very straight forward. Connecting the inputs of two crosspoint switches has a very minor impact on performance. Input expansion requires more planning. Input expansion, as show in Figure 60 and Figure 61 gives the option of two ways to connect the outputs of the crosspoint switches. In Figure 60 the crosspoint switch outputs are connected directly together and share one termination resistor. This is the easiest configurarion to implement and has only one drawback. Because the disabled output of the unused crosspoint (only one output can be active at a time) has a small amount of capacitance, the frequency response of the active crosspoint will show peaking. This is illustrated in Figure 62 and Figure 63. In most cases this small amount of peaking is not a problem. As illustrated in Figure 61 each crosspoint output can be given its own termination resistor. This results in a frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2 crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint output will cause a gain error. In order to counter act this the termination resistors of both crosspoints should be adjusted to approximately 80Ω. This will provide very good matching, but the gain accuracy of the system will now be dependent on the process variations of the crosspoint resistors which have a variability of approximately ±20%. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 17 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com 1 1 1 2 2 IN 3 4x4 OUT 3 4 4 1 5 2 3 4 2 3 6 IN 4x4 OUT 7 8 4 Figure 59. Output Expansion 1 1 1 2 2 IN 4x4 OUT 3 3 2 4 4 3 5 1 6 2 IN 4x4 4 OUT 7 3 8 4 Figure 60. Input Expansion with Shared Termination Resistors 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 1 1 1 2 2 IN 4x4 OUT 3 3 2 4 4 3 5 1 6 2 IN 4x4 4 OUT 7 3 8 4 Figure 61. Input Expansion with Separate Termination Resistors 2 OUTPUT CONNECTED DIRECTLY 1 NORMALIZED GAIN (dB) 0 -1 NO EXPANSION -2 -3 -4 -5 VS = ±3.3V -6 VOUT = 2 VPP -7 -8 RL = 150: 1 10 100 1000 FREQUENCY (MHz) Figure 62. Input Expansion Frequency Response Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 19 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com 2 OUTPUTS CONNECTED DIRECTLY NORMALIZED GAIN (dB) 1 0 -1 -2 CONNECTED THROUGH 71: RESISTORS -3 -4 + V = +5V - -5 V = -5V VOUT = 2 VPP -6 RL = 150: -7 1 10 100 1000 FREQUENCY (MHz) Figure 63. Input Expansion Frequency Response DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Since most capacitive loading is due to undesired parasitic capacitances the values of the capacitive loading will not usually be known exactly. It is best to start with a conservative value of ROUT and decrease the value until the bandwidth shows slight peaking. At this point the value of the isloation resistor will be determined by whether flat frequency response or maximum bandwidth is the desired goal. Smaller values of ROUT will produce some peaking, but maximum bandwidth. Larger resistor values will decrease bandwidth and suppress peaking. As starting values, a capacitive load of 5 pF should have around 75 Ω of isolation resistance. A value of 120 pF would require around 12Ω. When driving transmission lines, the output termination resistor is normally sufficient. USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE REBIABILITY The LMH6580/LMH6581 crosspoint switch can offer enhanced bandwidth and reliability with the use of external buffers on the outputs. The bandwidth is increased by unloading the outputs and driving the high impedance of an external buffer. See the Frequency Response 1 kΩ Load curve in Typical Performance section for an example of bandwidth achieved with less loading on the outputs. For this technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used. As shown in Figure 64 the resistor RL is placed between the crosspoint output and the buffer amplifier. This resistor will provide a load for the crosspoint output buffer and reduce peaking caused by the buffer input capacitance. A recommended value for RL is 500Ω to 1000Ω. Higher values of RL will give higher bandwidth, but also higher peaking. The optimum value of RL will depend greatly on board layout and the input capacitance of the buffer amplifier. Besides offering enhanced bandwidth performance using an external buffer provides greater system reliability. The first advantage is to reduce thermal loading on the crosspoint switch. This reduced die temperature will increase the life of the crosspoint. The second advantage is enhanced ESD reliability. It is very difficult to build high speed devices that can withstand all possible ESD events. With external buffers the crosspoint switch is isolated from ESD events on the external system connectors. LMH6703 LMH6583 OUTPUT BUFFER RL + - VOUT 560: 1 k: 560: Figure 64. Buffered Output 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 CROSSTALK When designing a large system such as a video router crosstalk can be a very serious problem. Extensive testing in our lab has shown that most crosstalk is related to board layout rather than occurring in the crosspoint switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as possible between input and output signal traces. Care must be taken, though, not to influence the signal trace impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated with higher frequencies crosstalk increases at higher frequencies. SWITCH MATRIX 4 OUTPUTS 8 INPUTS DIGITAL CONTROL 36 CONFIGURATION REGISTER CFG BCST 16 DATA IN LOAD REGISTER CS CLK RST DATA OUT MODE Figure 65. Block Diagram Table 1. Logic Pins Pin Name Level Sensitive CLK Yes Edge Triggered Triggered by CS Yes CLK rising edge DATA IN Yes CLK falling edge DATA OUT Yes CLK rising edge CFG Yes MODE Yes RST Yes BCST Yes There are two modes for programing the LMH6580/LMH6581, Serial Mode and Addressed Mode. The LMH6580/LMH6581 have internal control registers that store the programming states of the crosspoint switch. The logic is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied directly to the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off state and the address of which input to connect to. These registers are not directly accessible to the user. The second level of logic is another bank of registers identical to the first, but set up as shift registers. These registers are accessed by the user via the serial input bus. The LMH6580/LMH6581 is programmed via a serial input bus with the support of four other digital control pins. The Serial bus consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The serial bus is gated by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all data on the serial input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is set to begin receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 21 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com brought low at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next negative transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal. Once the last valid data has been clocked in, either the chip select pin must go high or, the clock signal must stop. Otherwise invalid data will be clocked into the chip. The data clocked into the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of the state of the MODE pin. The CFG pin is not dependent on the state of the Chip select pin. If no new data is clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation. The programming format of the incoming serial data is selected by the MODE pin. When the MODE pin is HIGH the crosspoint can be programmed one output at a time by entering a string of data that contains the address of the output that is going to be changed (Addressed Mode). When the mode pin is LOW the crosspoint is in Serial Mode. In this mode the crosspoint accepts a 16 bit array of data that programs all of the outputs. In both modes the data fed into the chip does not change the chip operation until the Configure pin is pulsed high. The configure and mode pins are independent of the chip select pin. THREE WIRE VS. FOUR WIRE CONTROL There are two ways to connect the serial data pins. The first way is to control all four pins separately, and the second option is to connect the CFG and the CS pins together for a 3 wire interface. The benefit of the 4-wire interface is that the chip can be configured independently using the CS pin. This would be an advantage in a system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured simultaneously. The 4-wire solution is also helpful in a system that has a free running clock on the CLK pin. In this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being clocked into the chip. The 3-wire option provides the advantage of one less pin to control at the expense of having less flexibility with the configure pin. One way around this loss of flexibility would be if the clock signal is generated by an FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip select function is provided by the presence or absence of the clock signal. SERIAL PROGRAMMING MODE Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 16-bits programs all four outputs of the crosspoint. The data is fed to the chip as shown in Table 2 and Table 3 (two tables are required to show the entire data frame). The table is arranged such that the first bit clocked into the crosspoint register is labeled bit number 0. The register labeled Load Register in Figure 65 is a shift register. If the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then additional data will be shifted into the register, and the desired data will be shifted out. Also illustrated is the timing relationships for the digital pins in Figure 66. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid data from being clocked into the chip. Another way to accomplish the same thing is to strobe the clock pin with only the desired number of pulses starting and ending with clock in the low condition. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 T-1 1 CLK 0 T1 T0 T12 T13 T15 T14 T16 TS TS 1 CS_N 0 1 CFG 0 TH TS 1 DIN 0 I0 I1 I... I13 I12 I14 I15 I16 1 MODE 0 TD 1 I0 DOUT 0 I1 Figure 66. Timing Diagram for Serial Mode Table 2. Serial Mode Data Frame (First Two Words) (1) Output 0 Output 1 Input Address LSB 0 (1) 1 On = 0 Input Address MSB Off = 1 LSB LSB 2 3 4 5 On = 0 Off = 1 6 7 Off = TRI-STATE, Bit 0 is first bit clocked into device. Table 3. Serial Mode Data Frame (Continued) Output 2 Output 3 Input Address LSB 8 9 On = 0 Input Address MSB Off = 1 LSB 10 11 12 13 On = 0 MSB Off = 1 14 15 ADDRESSED PROGRAMMING MODE Addressed programming mode makes it possible to change only one output register at a time. To utilize this mode the mode pin must be High. All other pins function the same as in serial programming mode except that the word clocked in is 5 bits and is directed only at the output specified. In addressed mode the data format is shown below in Table 4. Also illustrated is the timing relationships for the digital pins in Figure 67. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. The chip select pin must then transition high after the final data bit has been clocked in and before another clock signal positive edge occurs to prevent invalid data from being clocked into the chip. Also, in addressed mode is it necessary for the clock signal to make a low to high transition after the chip select pin has been brought high. If there is not a low to high transition of the clock after the chip select pin goes high subsequent data wil not be loaded into the chip properly. The configure (CFG) pin timing is not critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 23 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 T1 1 CLK 0 www.ti.com T2 T3 T4 T5 T6 TS T7 T8 T9 T10 TS 1 CS_N 0 1 CFG 0 TH TS 1 DIN 0 A0 A1 I2 I1 I0 T 1 MODE 0 1 DOUT 0 HIGH IMPEDANCE Figure 67. Timing Diagram for Addressed Mode Table 4. Addressed Mode Word Format (1) Output Address Input Address LSB MSB LSB 0 1 2 (1) 3 TRI-STATE MSB 1 = TRI-STATE 0 = On 4 5 Bit 0 is first bit clocked into device. DAISY CHAIN OPTION IN SERIAL MODE The LMH6580/LMH6581 supports daisy chaining of the serial data stream between multiple chips. This feature is available only in the Serial Programming Mode. To use this feature serial data is clocked into the first chip DIN pin, and the next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select pin goes low on both chips a double length word is clocked into the first chip. As the first word is clocking into the first chip the second chip is receiving the data that was originally in the shift register of the first chip (invalid data). When a full 16 bits have been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip. With a full 32 clock cycles both chips have valid data and the chip select pin of both chips should be brought high to prevent the data from overshooting. A configure pulse will activate the new configuration on both chips simultaneously, or each chip can be configured separately. The mode, chip select, configure and clock pins of both chips can be tied together and driven from the same sources. SPECIAL CONTROL PINS The LMH6580/LMH6581 have two special control pins that function independent of the serial control bus. One of these pins is the reset (RST) pin. The RST pin is active high meaning that at logic 1 level the chip is configured with all outputs disabled and in a high impedance state. The RST pin programs all the registers with input address 0 and all the outputs are turned off. In this configuration the device draws only 11mA. The RST pin can be used as a shutdown function to reduce power consumption. The other special control pin is the broadcast (BCST) pin. The BCST pin is also active high and sets all the outputs to the on state connected to input 0. This is sometimes referred to as broadcast mode, where input 0 is broadcast to all eight outputs. 24 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 LMH6580, LMH6581 www.ti.com SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 THERMAL MANAGEMENT The LMH6580/LMH6581 are high performance devices that produce a significant amount of heat. With ±5V supplies, the LMH6580/LMH6581 will dissipate approximately 0.5 W of idling power with all outputs enabled. Idling power is calculated based on the typical supply current of 50 mA and a 10V supply voltage. This power dissipation will vary within the range of 0.4 W to 0.6 W due to process variations. In addition, each equivalent video load (150Ω) connected to the outputs should be budgeted 30 mW of power. For a typical application with one video load for each output this would be a total power of 0.62 W. With a θJA of 44 °C/W this will result in the silicon being 27°C over the ambient temperature. A more aggressive application would be two video loads per output which would result in 0.74 W of power dissipation. This would result in a 33°C temperature rise. For heavier loading, the TQFP package thermal performance can be significantly enhanced with an external heat sink and by providing for moving air ventilation. Also, be sure to calculate the increase in ambient temperature from all devices operating in the system case. Because of the high power output of this device, thermal management should be considered very early in the design process. Generous passive venting and vertical board orientation may avoid the need for fan cooling or heat sinks. Also, the LMH6580/LMH6581 can be operated with a ±3.3V power supply. This will cut power dissipation substantially while only reducing bandwidth by about 10% (2 VPP output). The LMH6580/LMH6581 are fully characterized and factory tested at the ±3.3V power supply condition for applications where reduced power is desired. PRINTED CIRCUIT LAYOUT Generally, a good high frequency layout will keep power supply and ground traces away from the input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross analog signal lines (particularly inputs) it is best if they cross perpendicularly. Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device Package Evaluation Board Part Number LMH6580 48–Pin LMH730164EF Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 Submit Documentation Feedback 25 LMH6580, LMH6581 SNOSAY4C – AUGUST 2007 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 26 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 25 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMH6580 LMH6581 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 PACKAGING INFORMATION Orderable Device Status (1) LMH6580VS/NOPB ACTIVE Package Type Package Pins Package Drawing Qty TQFP PFB 48 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU SN Level-3-260C-168 HR (4) -40 to 85 LMH6580 VS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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