ON MC10E411FNR2G 5v ecl 1:9 differential pecl/necl rambus clock buffer Datasheet

MC10E411
5VECL 1:9 Differential
PECL/NECL RAMBus Clock
Buffer
Description
The MC10E411 is a low skew 1-to-9 differential driver, designed
with clock distribution in mind. The MC10E411’s function and
performance are similar to the popular MC10E111, with the added
feature of 1.2 V output swings.
The output voltage swing of the E411 is larger than a standard ECL
swing. The 1.2 V output swings provide a signal which can be AC
coupled into RAMBus compatible input loads. The larger output
swings are produced by lowering the VOL of the device. With the
exception of the lower VOL, the E411 is identical to the MC10E111.
Note that the larger output swings eliminate the possibility of
temperature compensated outputs, thus the E411 is only available in
the 10E style of ECL. In addition, because the VOL is lower than
standard ECL, the outputs cannot be terminated to −2.0 V. This data
sheet provides a few termination alternatives.
The device TPD is affected by the quantity of output pairs
terminated with minimum occurring with only one output pair and
increasing about 10 − 20 ps for all output pairs. Relative skew
distribution is not affected as more pairs are terminated, but the
increased TPD does shift the entire distribution. Unused output pairs
should be left unterminated (open) to reduce power and switching
noise.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MC10E411FNG
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Features
•
•
•
•
•
•
•
•
• ESD Protection: Human Body Model; > 2 kV,
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
Differential Design
VBB Output
Voltage Compensated Outputs
PECL Mode Operating Range:
VCC = 4.5 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −4.5 V to −5.5 V
Internal Input 50 kW Pulldown Resistors
•
•
•
•
•
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 180 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC10E411/D
MC10E411
Q0
Q0
Q1 VCCO Q1
Q2
Q2
Q0
25
24
23
20
19
Q0
22
21
VEE
26
18
Q3
Q1
EN
27
17
Q3
Q2
IN
28
16
Q4
15
VCCO
Pinout: 28-Lead PLCC
(Top View)
VCC
1
IN
2
14
Q4
VBB
3
13
Q5
NC
4
12
Q5
5
6
7
8
9
Q8
Q8
Q7 VCCO Q7
10
11
Q6
Q6
Q1
Q2
Q3
Q3
IN
Q4
IN
Q4
Q5
Q5
EN
Q6
Q6
Q7
Q7
All VCC and VCCO pins are tied together on the die
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Q8
Q8
VBB
Figure 1. 28−Lead Pinout Assignment
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN
FUNCTION
IN, IN
EN
Q0, Q0−Q8, Q8
VBB
VCC, VCCO
VEE
NC
ECL Differential Input Pair
ECL Enable
ECL Differential Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
VCC
VCC
RS = ZO
ZO
ZO
RAMBus Load
300 W
VOH and VOL levels will vary
slightly from specification table
RL = ZO
VCC −2.4 V
VEE
Figure 3. Termination Alternatives
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2
MC10E411
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
Tsol
Wave Solder
Pb
Pb−Free
Condition 2
VI VCC
VI VEE
Rating
Unit
8
V
6
−6
V
V
50
100
mA
mA
± 0.5
mA
0 to +85
°C
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E411
Table 3. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
65
Min
85°C
Typ
Max
55
65
Min
Typ
Max
Unit
55
65
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
2580
2750
2920
2620
2785
2950
2690
2865
3040
mV
VIH
Input HIGH Voltage (Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.73
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
3.4
4.6
3.4
4.6
3.4
4.6
V
IIH
Input HIGH Current
150
mA
150
150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.5 V / −0.5 V.
2. Outputs are terminated through a 300 W resistor to VEE.
3. VIHCMR min and max vary 1:1 with VCC.
Table 4. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C
Typ
Max
Typ
Max
Typ
Max
Unit
Power Supply Current
130
156
130
156
130
156
mA
IEE
Power Supply Current
55
65
55
65
55
65
mA
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 5)
−2420
−2250
−2080
−2380
−2215
−2050
−2310
−2135
−1960
mV
VIH
Input HIGH Voltage (Single−Ended)
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage (Single−Ended)
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.35
−1.25
−1.31
−1.19
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
−1.6
−2.4
−1.6
−0.4
−1.6
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
Characteristic
Min
85°C
IEE
Symbol
Min
25°C
150
0.5
0.3
Min
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.5 V / −0.5 V.
5. Outputs are terminated through a 300 W resistor to VEE.
6. VIHCMR min and max vary 1:1 with VCC.
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MC10E411
Table 5. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 7)
0°C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
700
Typ
85°C
Max
Min
700
Typ
Max
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
IN (Differential) (Note 8)
IN (Single−Ended) (Note 9)
EN to Q
400
350
450
ts
Setup Time (Note 10)
EN to IN
200
0
200
0
200
0
ps
tH
Hold Time (Note 11)
IN to EN
0
−200
0
−200
0
−200
ps
tR
Release Time (Note 12)
EN to IN
300
100
300
100
300
100
ps
tskew
Within-Device Skew (Note 13)
Part-to-Part Skew (Diff)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing
(Differential Configuration)
250
1000
250
1000
250
1000
mV
tr/tf
Output Rise/Fall Time
(20%−80%)
275
600
275
600
275
600
ps
600
650
850
430
380
450
700
Unit
fMAX
630
680
850
50
200
500
450
450
700
750
850
50
200
<1
MHz
50
200
<1
<1
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary +0.5 V / −0.5 V.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
11. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
12. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times.
13. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
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5
MC10E411
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.4 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E411FN
PLCC−28
37 Units / Rail
MC10E411FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E411FNR2
PLCC−28
500 / Tape & Reel
MC10E411FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC10E411
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E411
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC10E411/D
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