LTC2337-18 18-Bit, 500ksps, ±10.24V True Bipolar, Fully Differential Input ADC with 100dB SNR Description Features n n n n n n n n n n n n n n n n n 500ksps Throughput Rate ±4LSB INL (Max) Guaranteed 18-Bit No Missing Codes Fully Differential Inputs True Bipolar Input Ranges ±6.25V, ±10.24V, ±12.5V 100dB SNR (Typ) at fIN = 2kHz –115dB THD (Typ) at fIN = 2kHz Guaranteed Operation to 125°C Single 5V Supply Low Drift (20ppm/°C Max) 2.048V Internal Reference Onboard Single-Shot Capable Reference Buffer No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock Power Dissipation 35mW (Typ) 16-Lead MSOP Package The LTC®2337-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with fully differential inputs. Operating from a single 5V supply, the LTC2337-18 has a ±10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2337-18 achieves ±4LSB INL maximum, no missing codes at 18-bits with 100dB SNR. The LTC2337-18 has an onboard single-shot capable reference buffer and low drift (20ppm/°C max) 2.048V temperature compensated reference. The LTC2337-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 500ksps throughput with no cycle latency makes the LTC2337-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2337-18 dissipates only 35mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2337-18 to 300μW for further power savings during inactive periods. Applications n n n n n Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765 and 7961132 Typical Application 5V 10µF 32k Point FFT fS = 500ksps, fIN = 2kHz 1.8V TO 5V 2.2µF 0 SNR = 100.4dB THD = –116dB SINAD = 100.3dB SFDR = –118dB –20 0.1µF –10.24V +10.24V –10.24V + VDD VDDLBYP OVDD IN+ LTC2337-18 – IN– REF REFBUF 47µF REFIN 100nF GND CHAIN RDL/SDI SDO SCK BUSY CNV SAMPLE CLOCK 233718 TA01 AMPLITUDE (dBFS) –40 +10.24V –60 –80 –100 –120 –140 –160 –180 0 50 100 150 FREQUENCY (kHz) 200 250 233718 TA01b 233718f For more information www.linear.com/LTC2337-18 1 LTC2337-18 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) TOP VIEW Supply Voltage (VDD)...................................................6V Supply Voltage (OVDD).................................................6V Supply Bypass Voltage (VDDLBYP)............................3.2V Analog Input Voltage IN+, IN–...............................................–16.5V to 16.5V REFBUF....................................................................6V REFIN ...................................................................2.8V Digital Input Voltage (Note 3)............................ (GND –0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)............................ (GND –0.3V) to (OVDD + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2337C................................................. 0°C to 70°C LTC2337I..............................................–40°C to 85°C LTC2337H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C VDDLBYP VDD GND IN+ IN– GND REFBUF REFIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY CHAIN CNV MS PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 110°C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2337CMS-18#PBF LTC2337CMS-18#TRPBF 233718 16-Lead Plastic MSOP 0°C to 70°C LTC2337IMS-18#PBF LTC2337IMS-18#TRPBF 233718 16-Lead Plastic MSOP –40°C to 85°C LTC2337HMS-18#PBF LTC2337HMS-18#TRPBF 233718 16-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) (Note 5) l –2.5 • VREFBUF – 0.25 MIN TYP 2.5 • VREFBUF + 0.25 MAX V VIN – Absolute Input Range (IN–) (Note 5) l –2.5 • VREFBUF – 0.25 2.5 • VREFBUF + 0.25 V VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– l –5 • VREFBUF 5 • VREFBUF V VCM Common Mode Input Range (Note 11) l –0.5 IIN Analog Input Current l –7.8 CIN Analog Input Capacitance 5 pF RIN Analog Input Resistance 2.083 kΩ CMRR Input Common Mode Rejection Ratio 67 dB 0 fIN = 250kHz UNITS 0.5 V 4.8 mA Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN Resolution l 18 No Missing Codes l 18 TYP Integral Linearity Error Bits DNL Differential Linearity Error BZE Bipolar Zero-Scale Error FSE Bipolar Full-Scale Error 0.8 (Note 6) UNITS Bits Transition Noise INL MAX LSBRMS l –4 ±1 4 l –1 ±0.1 1 LSB (Note 7) l –15 0 15 LSB VREFBUF = 4.096V (REFBUF Overdriven) (Notes 7, 9) l –100 100 LSB REFIN = 2.048V (Note 7) l –150 150 LSB Bipolar Zero-Scale Error Drift LSB 0.01 Bipolar Full-Scale Error Drift LSB/°C ±0.5 ppm/°C Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 93 97 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 95 100 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l 96 101 dB ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 93.5 97 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 96 100 dB 98 SNR THD SFDR Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range MAX UNITS ±12.5V Range, fIN = 2kHz, REFBUF = 5V l ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l –111 –102 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l –115 –102 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l –112 –100 dB ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l 102 113 dB ±10.24V Range, fIN = 2kHz, REFIN = 2.048V l 102 117 dB ±12.5V Range, fIN = 2kHz, REFBUF = 5V l 100 114 –3dB Input Linear Bandwidth 102 7 dB dB MHz Aperture Delay 500 ps Aperture Jitter 4 ps Transient Response Full-Scale Step 0.5 µs 233718f For more information www.linear.com/LTC2337-18 3 LTC2337-18 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREFIN Internal Reference Output Voltage VREFIN Temperature Coefficient (Note 14) MIN TYP MAX 2.043 2.048 2.053 2 20 l REFIN Output Impedance UNITS V ppm/°C 15 VREFIN Line Regulation VDD = 4.75V to 5.25V REFIN Input Voltage Range (REFIN Overdriven) (Note 5) kΩ 0.08 mV/V 1.25 2.4 V Reference Buffer Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VREFBUF Reference Buffer Output Voltage VREFIN = 2.048V l 4.091 4.096 4.101 V REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 5, 9) l 2.5 5 V REFBUF Output Impedance VREFIN = 0V REFBUF Load Current VREFBUF = 5V (REFBUF Overdriven) (Notes 9, 10) VREFBUF = 5V, Nap Mode (REFBUF Overdriven) (Note 9) IREFBUF 13 kΩ 0.72 0.39 l 0.8 mA mA Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIH High Level Input Voltage VIL Low Level Input Voltage IIN Digital Input Current CIN Digital Input Capacitance CONDITIONS MIN l TYP MAX V l VIN = 0V to OVDD UNITS 0.8 • OVDD –10 l 0.2 • OVDD V 10 μA 5 VOH High Level Output Voltage IO = –500µA l VOL Low Level Output Voltage IO = 500µA l l pF OVDD – 0.2 V 0.2 –10 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD ISOURCE Output Source Current VOUT = 0V –10 10 mA µA ISINK Output Sink Current VOUT = OVDD 10 mA Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VDD Supply Voltage OVDD Supply Voltage CONDITIONS 500ksps Sample Rate (IN+ = IN– = 0V) IVDD IOVDD INAP ISLEEP Supply Current Supply Current Nap Mode Current Sleep Mode Current 500ksps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD) Sleep Mode (IVDD + IOVDD) PD Power Dissipation Nap Mode Sleep Mode 500ksps Sample Rate (IN+ = IN– = 0V) Conversion Done (IVDD + IOVDD) Sleep Mode (IVDD + IOVDD) 4 MIN TYP MAX UNITS l 4.75 5 5.25 V l 1.71 5.25 V 8.5 l l 7 0.1 3.9 60 4.6 225 mA mA mA μA l l l 35 19.5 0.3 42.5 23 1.1 mW mW mW l 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fSMPL Maximum Sampling Frequency l tCONV Conversion Time l 1 tACQ Acquisition Time l 1.460 tHOLD Maximum Time between Acquisitions l tCYC Time Between Conversions l 2 µs tCNVH CNV High Time l 20 ns tACQ = tCYC – tHOLD (Note 11) TYP MAX UNITS 500 ksps 1.5 µs 540 ns µs tBUSYLH CNV↑ to BUSY Delay CL = 20pF l tCNVL Minimum Low Time for CNV (Note 12) l 20 ns tQUIET SCK Quiet Time from CNV↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 10 ns 13 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 12) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 12) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO l 13.5 tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V CL = 20pF, OVDD = 2.5V CL = 20pF, OVDD = 1.71V l l l tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 11) l tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 11) tEN ns 7.5 8 9.5 ns ns ns l 5 ns 1 ns Bus Enable Time After RDL↓ (Note 12) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 12) l 13 ns tWAKE REFBUF Wakeup Time CREFBUF = 47μF, CREFIN = 100nF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V, fSMPL = 500kHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB 200 ms when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±20.48V input with REFIN = 2.048V. Note 9: When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0V. Note 10: fSMPL = 500kHz, IREFBUF varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 13: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD tDELAY tDELAY 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD 50% 50% 233718 F01 Figure 1. Voltage Levels for Timing Specifications 233718f For more information www.linear.com/LTC2337-18 5 LTC2337-18 Typical Performance Characteristics fSMPL = 500ksps, unless otherwise noted. Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 5000 2.5 0.4 4500 0.3 4000 0.2 3500 0.1 3000 DNL ERROR (LSB) 1.0 0.5 0 –0.5 –1.0 COUNTS 0.5 1.5 INL ERROR (LSB) DC Histogram 3.0 2.0 0.0 –0.1 1500 1000 –2.5 –0.4 500 –3.0 –0.5 0 65536 131072 196608 OUTPUT CODE 262144 0 65536 131072 196608 OUTPUT CODE 233718 G01 THD, Harmonics vs Input Frequency SNR, SINAD vs Input Frequency 110 SNR = 100.4dB THD = –116dB SINAD = 100.3dB SFDR = –118dB –70 –60 –80 –100 –120 –140 SINAD 90 80 70 0 50 100 150 FREQUENCY (kHz) 200 60 250 0 25 50 –110 –120 –130 SNR, SINAD vs Input Level, fIN = 2kHz 102.0 SNR, SINAD vs Temperature, fIN = 2kHz SNR, SINAD (dBFS) 101.0 SNR SINAD 100.5 –105 100.5 100.0 SNR SINAD 99.5 99.0 –30 –20 –10 INPUT LEVEL (dB) 0 233718 G07 50 75 100 125 150 175 200 FREQUENCY (kHz) 98.0 –55 –35 –15 THD, Harmonics vs Temperature, fIN = 2kHz –110 –115 –120 –125 THD 3RD 2ND –130 98.5 100.0 –40 25 233718 G06 THD, HARMONICS (dBFS) 101.5 101.0 0 233718 G05 101.5 6 –100 –150 75 100 125 150 175 200 FREQUENCY (kHz) 233718 G04 102.0 –90 –140 –160 –180 THD 2ND 3RD –80 SNR 100 SNR, SINAD (dBFS) –40 233718 G03 233718 G02 32k Point FFT fS = 500ksps, fIN = 2kHz –20 0 131067 131069 131071 131073 131075 CODE 262144 THD, HARMONICS (dBFS) 0 MAGNITUDE (dBFS) 2000 –0.3 –2.0 σ = 0.8 2500 –0.2 –1.5 AMPLITUDE (dBFS) TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V, 5 25 45 65 85 105 125 TEMPERATURE (°C) 233718 G08 –135 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 233718 G09 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 500ksps, unless otherwise noted. Full-Scale Error vs Temperature Offset Error vs Temperature 20 5 1.5 15 4 MAX INL 0.5 MAX DNL 0 MIN DNL –0.5 –1.0 MIN INL 3 10 OFFSET ERROR (LSB) 1.0 FULL-SCALE ERROR (LSB) INL, DNL ERROR (LSB) INL/DNL vs Temperature 2.0 5 0 –5 –10 –15 –2.0 –55 –35 –15 –20 –55 –35 –15 INTERNAL REFERENCE OUTPUT (V) VDD 2.0484 100 CURRENT (µA) CURRENT (mA) 80 60 40 2 20 1 OVDD 0 –55 –35 –15 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 233718 G13 2.0482 2.0481 2.0480 2.0479 2.0478 2.0477 2.0476 –55 –35 –15 30 75 25 Supply Current vs Sampling Rate 8 7 SUPPLY CURRENT (mA) 80 CMRR (dB) 70 20 15 65 60 10 55 5 6 8 10 233718 G16 5 25 45 65 85 105 125 TEMPERATURE (°C) 233718 G15 CMRR vs Input Frequency 35 –10 –8 –6 –4 –2 0 2 4 DRIFT (ppm/°C) 2.0483 233718 G14 Internal Reference Output Temperature Coefficient Distribution NUMBER OF PARTS 233718 G12 120 3 5 25 45 65 85 105 125 TEMPERATURE (°C) Internal Reference Output vs Temperature 6 0 –5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Sleep Current vs Temperature 8 4 –2 233718 G11 Supply Current vs Temperature 5 0 –1 –4 233718 G10 7 1 –3 –1.5 5 25 45 65 85 105 125 TEMPERATURE (°C) 2 50 VDD 6 5 4 3 2 1 0 50 100 150 FREQUENCY (kHz) 200 250 233718 G17 0 OVDD 0 100 300 200 400 SAMPLING FREQUENCY (kHz) 500 233718 G18 233718f For more information www.linear.com/LTC2337-18 7 LTC2337-18 Pin Functions VDDLBYP (Pin 1): 2.5V Supply Bypass Pin. The voltage on this pin is generated via an onboard regulator off of VDD. This pin must be bypassed with a 2.2μF ceramic capacitor to GND. VDD (Pin 2): 5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 10µF ceramic capacitor. GND (Pins 3, 6 and 16): Ground. IN+, IN– (Pins 4, 5): Positive and Negative Differential Analog Inputs. Typical input range ±10.24V. REFBUF (Pin 7): Reference Buffer Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 47μF ceramic capacitor. The internal buffer driving this pin may be disabled by grounding its input at REFIN. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V. A resistive load greater than 500kΩ can be placed on the reference buffer output. REFIN (Pin 8): Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs 2.048V at this pin. Bypass this pin with a 100nF ceramic capacitor to GND to limit the reference output noise. If more accuracy is desired, this pin may be overdriven by an external reference in the range of 1.25V to 2.4V. CNV (Pin 9): Convert Input. A rising edge on this input powers up the part and initiates a new conversion. Logic levels are determined by OVDD. 8 CHAIN (Pin 10): Chain Mode Selector Pin. When low, the LTC2337-18 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2337-18 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. BUSY (Pin 11): BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by OVDD. RDL/SDI (Pin 12): When CHAIN is low, the part is in normal mode and the pin is treated as a bus enabling input. When CHAIN is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another ADC in the daisy chain is input. Logic levels are determined by OVDD. SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, the conversion result or daisy-chain data from another ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by OVDD. SDO (Pin 14): Serial Data Output. The conversion result or daisy-chain data is output on this pin on each rising edge of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by OVDD. OVDD (Pin 15): I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1μF capacitor. 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Functional Block Diagram VDD = 5V VDDLBYP = 2.5V REFIN = 1.25V TO 2.4V OVDD = 1.8V TO 5V REFBUF = 2.5V TO 5V LDO 15k 2.048V REFERENCE 2× REFERENCE BUFFER IN+ IN– 4R 4R R 0.63× BUFFER + R 18-BIT SAMPLING ADC – CHAIN SDO RDL/SDI SCK SPI PORT CNV BUSY CONTROL LOGIC GND 233718 BD01 Timing Diagram Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV BUSY CONVERT HOLD NAP ACQUIRE SCK SDO D17 D16 D15 D2 D1 D0 233718 TD01 233718f For more information www.linear.com/LTC2337-18 9 LTC2337-18 Applications Information The LTC2337-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with fully differential inputs. Operating from a single 5V supply, the LTC2337-18 has a ±10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2337-18 achieves ±4LSB INL maximum, no missing codes at 18-bits and 100dB SNR. The LTC2337-18 has an onboard single-shot capable reference buffer and low drift (20ppm/°C max) 2.048V temperaturecompensated reference. The LTC2337-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 500ksps throughput with no cycle latency makes the LTC2337-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2337-18 dissipates only 35mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2337-18 to 300μW for further power savings during inactive periods. Converter Operation The LTC2337-18 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A converter (CDAC) is connected to the outputs of the resistor divider networks that pins IN+ and IN– drive to sample an attenuated and level-shifted version of the differential analog input voltage as shown in Figure 3. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4 … VREFBUF/262144) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 18-bit digital output code for serial transfer. with REFBUF = 4.096V. The ideal transfer function is shown in Figure 2. The output data is in 2’s complement format. Analog Input The analog inputs of the LTC2337-18 are fully differential to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit shown in Figure 3. The back-to-back diodes at the inputs form clamps that provide ESD protection. Each input drives a resistor divider network that has a total impedance of 2kΩ. The resistor divider network attenuates and level shifts the ±2.5 • REFBUF true bipolar signal swing of each input to the 0-REFBUF input signal swing of the ADC core. In the acquisition phase, 45pF (CIN) from the sampling CDAC in series with approximately 50Ω (RON) from the on-resistance of the sampling switch is connected to 011...111 OUTPUT CODE (TWO’S COMPLEMENT) Overview BIPOLAR ZERO 011...110 000...001 000...000 111...111 111...110 100...001 FSR = +FS – –FS 1LSB = FSR/262144 100...000 –FSR/2 233718 F02 Figure 2. LTC2337-18 Transfer Function 0.63 • VREFBUF IN+ 1.6k 400Ω RON 50Ω CIN 45pF 0.63 • VREFBUF IN– 1.6k Transfer Function 400Ω RON 50Ω CIN 45pF BIAS VOLTAGE 233718 F03 The LTC2337-18 digitizes the full-scale voltage of ±5 • REFBUF into 218 levels, resulting in an LSB size of 156µV 10 –1 0V 1 FSR/2 – 1LSB LSB LSB INPUT VOLTAGE (V) Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2337-18 For more information www.linear.com/LTC2337-18 233718f LTC2337-18 Applications Information the output of the resistor divider network. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC core and resistor divider network. The inputs of the ADC core draw a current spike while charging the CIN capacitors during acquisition. Input Drive Circuits A low impedance source can directly drive the high impedance inputs of the LTC2337-18 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike when entering acquisition. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2337-18. The amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC inputs which draw a small current spike during acquisition. High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Single-Ended-to-Differential Conversion For single-ended input signals, a single-ended-to-differential conversion circuit must be used to produce a differential signal at the inputs of the LTC2337-18. The LT1469 high speed dual operational amplifier is recommended for performing single-ended-to-differential conversions as shown in Figure 5a. In this case, the first amplifier is configured as a unity gain buffer and the single-ended input signal directly drives the high impedance input of this amplifier. Figure 5b shows the resulting FFT when the LT1469 is used to drive the LTC2337-18 in this configuration. LT1469 Input Filtering The input resistor divider network, sampling switch onresistance (RON) and the sample capacitor (CIN) form a second lowpass filter that limits the input bandwidth to the ADC core to 7MHz. A buffer amplifier with a low noise density must be selected to minimize the degradation of the SNR over this bandwidth. SINGLE-ENDED INPUT SIGNAL IN+ 500Ω IN– BW = 48kHz SINGLE-ENDEDTO-DIFFERENTIAL DRIVER Figure 4. Input Signal Chain 6 4.99k + – OUT2 7 ±10.24V 4.99k 233718 F05a Figure 5a. LT1469 Converting a ±10.24V Single-Ended Signal to a ±20.48V Differential Input Signal 0 SNR = 100dB THD = –115dB SINAD = 99.9dB SFDR = –119dB –20 –40 –60 –80 –100 –120 –140 LTC2337-18 6600pF ±10.24V 5 AMPLITUDE (dBFS) The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. The simple 1-pole RC lowpass filter shown in Figure 4 is sufficient for many applications. 2 ±10.24V OUT1 1 + – 3 –160 –180 233718 F04 0 50 100 150 FREQUENCY (kHz) 200 250 233718 F05b Figure 5b. 128k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 5a 233718f For more information www.linear.com/LTC2337-18 11 LTC2337-18 Applications Information Fully Differential Inputs Internal Reference with Internal Buffer To achieve the full distortion performance of the LTC2337‑18, a low distortion fully differential signal source driven through the LT1469 configured as two unity gain buffers as shown in Figure 6 can be used to get the full data sheet THD specification of –115dB. The LTC2337-18 has an on-chip, low noise, low drift (20ppm/°C max), temperature compensated bandgap reference that is factory trimmed to 2.048V. It is internally connected to a reference buffer as shown in Figure 7a and is available at REFIN (Pin 8). REFIN should be bypassed to GND with a 100nF ceramic capacitor to minimize noise. The reference buffer gains the REFIN voltage by 2 to 4.096V at REFBUF (Pin 7). So the input range is ±10.24V, as shown in Table 1. Bypass REFBUF to GND with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size) to compensate the reference buffer and minimize noise. LT1469 ±10.24V 3 2 5 ±10.24V 6 + – 1 + – 7 ±10.24V ±10.24V 233718 F06 BANDGAP REFERENCE 100nF ADC Reference REFBUF There are three ways of providing the ADC reference. The first is to use both the internal reference and reference buffer. The second is to externally overdrive the internal reference and use the internal reference buffer. The third is to disable the internal reference buffer and overdrive the REFBUF pin from an external source. The following tables give examples of these cases and the resulting bipolar input ranges. Table 1. Internal Reference with Internal Buffer REFIN REFBUF BIPOLAR INPUT RANGE 2.048V 4.096V ±10.24V Table 2. External Reference with Internal Buffer REFIN (OVERDRIVE) REFBUF BIPOLAR INPUT RANGE 1.25V (Min) 2.5V ±6.25V 2.048V 4.096V ±10.24V 2.4V (Max) 4.8V ±12V Table 3. External Reference Unbuffered REFIN REFBUF (OVERDRIVE) BIPOLAR INPUT RANGE 0V 2.5V (Min) ±6.25V 0V 5V (Max) ±12.5V 12 15k REFIN Figure 6. LT1469 Buffering a Fully Differential Signal Source REFERENCE BUFFER 6.5k 47µF 6.5k GND LTC2337-18 233718 F07a Figure 7a.LTC2337-18 Internal Reference Circuit External Reference with Internal Buffer If more accuracy and/or lower drift is desired, REFIN can be easily overdriven by an external reference since a 15k resistor is in series with the reference as shown in Figure 7b. REFIN can be overdriven in the range from 1.25V to 2.4V. The resulting voltage at REFBUF will be 2 • REFIN. So the input range is ±5 • REFIN, as shown in Table 2. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the LTC2337-18 when overdriving the internal reference. The LTC6655-2.048 offers 0.025% (max) initial accuracy and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range and complements the extended temperature range of the LTC2337-18 up to 125°C. Bypassing the LTC6655-2.048 with a 2.7μF to 100μF ceramic capacitor close to the REFIN pin is recommended. 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Applications Information 15k REFIN 15k REFIN BANDGAP REFERENCE BANDGAP REFERENCE 2.7µF REFBUF REFBUF REFERENCE BUFFER REFERENCE BUFFER 47µF LTC6655-2.048 6.5k 6.5k LTC6655-5 47µF 6.5k GND 6.5k LTC2337-18 LTC2337-18 GND 233718 F07b Figure7b. Using the LTC6655-2.048 as an External Reference External Reference Unbuffered The internal reference buffer can also be overdriven from 2.5V to 5V with an external reference at REFBUF as shown in Figure 7c. So the input ranges are ±6.25V to ±12.5V, respectively, as shown in Table 3. To do so, REFIN must be grounded to disable the reference buffer. A 13k resistor loads the REFBUF pin when the reference buffer is disabled. To maximize the input signal swing and corresponding SNR, the LTC6655-5 is recommended when overdriving REFBUF. The LTC6655-5 offers the same small size, accuracy, drift and extended temperature range as the LTC6655-2.048. By using a 5V reference, an SNR of 102dB can be achieved. Bypassing the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size) close to the REFBUF pin is recommended. The REFBUF pin of the LTC2337-18 draws a charge (QCONV) from the external bypass capacitor during each conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge with a DC current equivalent to IREFBUF = QCONV/tCYC. Thus, the DC current draw of REFBUF depends on the sampling rate and output code. In applications where a burst of samples is taken after idling for long periods, as shown in Figure 8, IREFBUF quickly goes from approximately 390µA to a maximum of 0.8mA for REFBUF = 5V at 500ksps. This step in DC current draw triggers a transient response in the external 233718 F07c Figure 7c. Overdriving REFBUF Using the LTC6655-5 reference that must be considered since any deviation in the voltage at REFBUF will affect the accuracy of the output code. If an external reference is used to overdrive REFBUF, the fast settling LTC6655-5 reference is recommended. Internal Reference Buffer Transient Response For optimum transient performance, the internal reference buffer should be used. The internal reference buffer uses a proprietary design that results in an output voltage change at REFBUF of less than 1LSB when responding to a sudden burst of conversions. This makes the internal reference buffer of the LTC2337-18 truly single-shot capable since the first sample taken after idling will yield the same result as a sample taken after the transient response of the internal reference buffer has settled. Figure 9 shows the transient responses of the LTC2337-18 with the internal reference buffer and with the internal reference buffer overdriven by the LTC6655-5, both with a bypass capacitance of 47μF. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the CNV IDLE PERIOD IDLE PERIOD 233718 F08 Figure 8. CNV Waveform Showing Burst Sampling 233718f For more information www.linear.com/LTC2337-18 13 LTC2337-18 Applications Information DEVIATION FROM FINAL VALUE (LSB) 2 that the LTC2337-18 achieves a typical SNR of 100dB at a 500kHz sampling rate with a 2kHz input. INTERNAL REFERENCE BUFFER 0 Total Harmonic Distortion (THD) –2 EXTERNAL SOURCE ON REFBUF –4 –6 –8 0 100 200 300 400 500 600 700 800 900 1000 TIME (µs) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: 233718 F09 Figure 9. Transient Response of the LTC2337-18 fundamental. The LTC2337-18 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 10 shows that the LTC2337-18 achieves a typical SINAD of 100dB at a 500kHz sampling rate with a 2kHz input. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 10 shows 0 SNR = 100.4dB THD = –116dB SINAD = 100.3dB SFDR = –118dB –20 AMPLITUDE (dBFS) –40 –60 –80 –100 V22 + V32 + V42 +…+ VN V1 2 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Power Considerations The LTC2337-18 provides two power supply pins: the 5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2337-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2337-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2337‑18 has a power-on reset (POR) circuit that will reset the LTC2337-18 at initial power-up or whenever the power supply voltage drops below 2V. Once the supply voltage reenters the nominal supply voltage range, the POR will re-initialize the ADC. No conversions should be initiated until 200μs after a POR event to ensure the re-initialization period has ended. Any conversions initiated before this time will produce invalid results. –120 –140 Timing and Control –160 –180 0 50 100 150 FREQUENCY (kHz) 200 250 233718 F10 Figure 10. 32k Point FFT of the LTC2337-18 14 THD= 20log CNV Timing The LTC2337-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Applications Information 8 7 SUPPLY CURRENT (mA) the LTC2337-18. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2337-18 powers down. VDD 6 5 4 3 2 1 0 OVDD 0 100 300 200 400 SAMPLING FREQUENCY (kHz) 500 233718 G18 Acquisition A proprietary sampling architecture allows the LTC2337-18 to begin acquiring the input signal for the next conversion 527ns after the start of the current conversion. This extends the acquisition time to 1.460µs, easing settling requirements and allowing the use of extremely low power ADC drivers. (Refer to the Timing Diagram.) Internal Conversion Clock The LTC2337-18 has an internal clock that is trimmed to achieve a maximum conversion time of 1.5µs. Auto Nap Mode The LTC2337-18 automatically enters nap mode after a conversion has been completed and completely powers up once a new conversion is initiated on the rising edge of CNV. During nap mode, only the ADC core powers down and all other circuits remain active. During nap, data from the last conversion can be clocked out. The auto nap mode feature will reduce the power dissipation of the LTC2337-18 as the sampling frequency is reduced. Since full power is consumed only during a conversion, the ADC core of the LTC2337-18 remains powered down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 11. Sleep Mode The auto nap mode feature provides limited power savings since only the ADC core powers down. To obtain greater power savings, the LTC2337-18 provides a sleep mode. During sleep mode, the entire part is powered down except for a small Figure 11. Power Supply Current of the LTC2337-18 Versus Sampling Rate. standby current resulting in a power dissipation of 300μW. To enter sleep mode, toggle CNV twice with no intervening rising edge on SCK. The part will enter sleep mode on the falling edge of BUSY from the last conversion initiated. Once in sleep mode, a rising edge on SCK will wake the part up. Upon emerging from sleep mode, wait tWAKE seconds before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at REFIN and REFBUF. (Refer to the Timing Diagrams section for more detailed timing information about sleep mode.) Digital Interface The LTC2337-18 has a serial digital interface. The flexible OVDD supply allows the LTC2337-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 40MHz, a 500ksps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D17 remains valid till the first rising edge of SCK. The serial interface on the LTC2337-18 is simple and straightforward to use. The following sections describe the operation of the LTC2337-18. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained. 233718f For more information www.linear.com/LTC2337-18 15 LTC2337-18 Timing Diagrams Normal Mode, Single Device shows a single LTC2337-18 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/SDI grounded, SDO is enabled and the MSB(D17) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2337-18. When CHAIN = 0, the LTC2337-18 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance. If RDL/SDI is low, SDO is driven. Figure 12 CONVERT DIGITAL HOST CNV CHAIN LTC2337-18 RDL/SDI BUSY IRQ SDO DATA IN SCK CLK 233718 F12a NAP ACQUIRE CONVERT NAP CONVERT ACQUIRE CHAIN = 0 RDL/SDI = 0 tCYC tCNVH tCNVL CNV tHOLD tACQ tACQ = tCYC – tHOLD tCONV BUSY tSCK tBUSYLH tSCKH 1 SCK 2 3 tHSDO tDSDOBUSYL SDO tQUIET 16 17 18 tSCKL tDSDO D17 D16 D15 D1 D0 233718 F12 Figure 12. Using a Single LTC2337-18 in Normal Mode 16 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Timing Diagrams Normal Mode, Multiple Devices be used to allow only one LTC2337-18 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 13, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. Figure 13 shows multiple LTC2337-18 devices operating in normal mode (CHAIN = 0) sharing CNV, SCK and SDO. By sharing CNV, SCK and SDO, the number of required signals to operate multiple ADCs in parallel is reduced. Since SDO is shared, the RDL/SDI input of each ADC must RDLB RDLA CONVERT CNV CHAIN CNV CHAIN LTC2337-18 SDO B BUSY LTC2337-18 IRQ DIGITAL HOST SDO A RDL/SDI RDL/SDI SCK SCK DATA IN CLK 233718 F13a NAP CONVERT NAP ACQUIRE CONVERT ACQUIRE CHAIN = 0 tCNVL CNV tHOLD BUSY tCONV tBUSYLH RDL/SDIA RDL/SDIB tSCK SCK 1 2 tSCKH 3 16 17 18 tHSDO SDO Hi-Z D17A D16A D15A 19 20 21 34 35 36 tSCKL tDSDO tEN tQUIET tDIS D1A D0A Hi-Z D17B D16B D15B D1B D0B Hi-Z 233718 F13 Figure 13. Normal Mode with Multiple Devices Sharing CNV, SCK, and SDO 233718f For more information www.linear.com/LTC2337-18 17 LTC2337-18 Timing Diagrams Chain Mode, Multiple Devices may limit the number of lines needed to interface to a large number of converters. Figure 14 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 18 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2337-18 operates in chain mode. In chain mode, SDO is always enabled and RDL/SDI serves as the serial data input pin (SDI) where daisy-chain data output from another ADC can be input. This is useful for applications where hardware constraints CONVERT OVDD OVDD CNV CHAIN RDL/SDI CNV CHAIN LTC2337-18 DIGITAL HOST LTC2337-18 RDL/SDI SDO A IRQ BUSY B DATA IN SDO SCK SCK CLK 233718 F14a NAP ACQUIRE CONVERT NAP ACQUIRE CONVERT CHAIN = OVDD RDL/SDIA = 0 tCYC tCNVL CNV tHOLD BUSY tCONV tBUSYLH tSCKCH SCK 1 2 3 16 17 tSSDISCK 18 19 20 34 35 36 tSCKL tHSDO tHSDISCK SDOA = RDL/SDIB tQUIET tSCKH tDSDO D17A D16A D15A D1A D0A D17B D16B D15B D1B D0B tDSDOBUSYL SDOB D17A D16A D1A D0A 233718 F14 Figure 14. Chain Mode Timing Diagram 18 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Timing Diagrams Sleep Mode To enter sleep mode, toggle CNV twice with no intervening rising edge on SCK as shown in Figure 15. The part will enter sleep mode on the falling edge of BUSY from the CHAIN = DON’T CARE RDL/SDI = DON’T CARE NAP CONVERT last conversion initiated. Once in sleep mode, a rising edge on SCK will wake the part up. Upon emerging from sleep mode, wait tWAKE seconds before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at REFIN and REFBUF. CONVERT SLEEP NAP AND ACQUIRE CONVERT ACQUIRE tCNVH tWAKE tACQ CNV tHOLD tCONV tCONV BUSY tBUSYLH SCK CHAIN = DON’T CARE RDL/SDI = DON’T CARE CONVERT SLEEP NAP AND ACQUIRE CONVERT tWAKE tCNVH CNV tCONV BUSY tBUSYLH SCK 233718 F15 Figure 15. Sleep Mode Timing Diagram 233718f For more information www.linear.com/LTC2337-18 19 LTC2337-18 Board Layout To obtain the best performance from the LTC2337-18 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1908, the evaluation kit for the LTC2337-18. Partial Top Silkscreen Partial Layer 1 Component Side 20 233718f For more information www.linear.com/LTC2337-18 LTC2337-18 Board Layout Partial Layer 2 Ground Plane Partial Layer 3 Power Plane Partial Layer 4 Bottom Layer 233718f For more information www.linear.com/LTC2337-18 21 R5 49.9 1206 BNC R14 0 OHM BNC J6 BNC C47 OPT 0603 C59 1.0uF 50V R39 0 OHM OPT C61 C44 1.0uF 25V C57 0.1uF 25V V+ 2 C60 0.1uF 25V R6 1K U8 4 5 6 R41 4.99K 2 3 - + U10A C42 OPT 0603 V+ 1 R3 OPT C58 7 C49 100pF R40 4.99K U10B LT1469CS8 V- 4 C2 0.1uF OPT R31 CLK R32 0 OHM OPT R38 R35 0 OHM 0 OHM R9 33 OHM U2 NC7SVU04P5X LT1469CS8 R33 0 OHM 2 5 3 C1 0.1uF NC7SZ04P5X R36 0 OHM R34 OPT C18 OPT 0603 C5 0.1uF BYPASS CAPS FOR U10 C55 1.0uF 50V J4 C43 0.1uF 25V AIN+ / - 10.24V V- AIN+ + / - 10.24V CLK IN 100MHz MAX 3.3VPP J1 R2 1K 8 5 3 +3.3V OPT R16 C19 OPT 0805 OPT R15 C40 OPT 1206 C39 OPT 1206 SDO SDO 5 4 * +5V 4 3 2 1 TP1 IN- IN+ OUTS OUTF GND C10 0.1uF C7 0.1uF E3 VREF 4 6 5 8 10 12 14 7 9 11 13 DC590 2 3 J3 C17 0.1uF RDL/SDI BUSY SDO SCK CNV 12 11 14 13 9 R1 CNV CNV TP3 SCK SCK TP2 B BUSY RDL RDL TP5 BUSY SDO SCK 2 3 A U7 R4 2K R17 1K R13 A2 A1 A0 SCL SDA WP 4 3 2 1 6 5 7 +3.3V 2 33 31 DB2 DB3 DB15 DB14 DB13 DB12 2 PROG WP R10 4.99K 4 2 1 6 5 3 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 R12 4.99K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 JP1 EEPROM R11 4.99K CLKOUT 0.1uF DB11 C16 DB10 DB9 DB8 DB7 DB6 DB5 29 35 DB1 DB4 37 39 DB0 DB17 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 TP7 DB16 CNVST_33 TP6 C4 0.1uF DB16 P1 CON-EDGE40-100 DB17 NC7SVU04P5X U4 C3 0.1uF 33 OHM DC590_DETECT 2 0.1uF NC7SZ04P5X U9 4 5 3 7 8 +3.3V +3.3V C15 Q PR Q C14 0.1uF 4 1 D 2 VCC R8 33 OHM CLR GND CP 1 24LC024-I /ST 6 4 U3 NL17SZ74 OE GND VCC 5 C13 +3.3V 0.1uF EXT JP2 REF INT +3.3V U6 NC7SZ66P5X CNV C56 0.1uF 2 C46 2.2uF 10V 33 OHM C48 TP4 10uF 6.3V C12 0.1uF 10V 1210 C20 47uF R37 OPT 9V-10V (NC) 1 R7 1K 5 6 7 8 VREF GND GND LTC6655BHMS8-5 GND VIN SHDN U1 LTC233X- CMS C9 10uF 6.3V C6 10uF 6.3V +3.3V C11 10uF +8.6V U15 2 VDD 1 3 +3.3V 1 15 OVDD GND GND GND 3 6 16 7 8 VDDLBYP REFBUF REFIN CHAIN 10 5 3 8 VCC VSS 4 5 3 1 For more information www.linear.com/LTC2337-18 3 4 + 22 - +3.3V LTC2337-18 Board Layout Partial Schematic of Demoboard 233718f LTC2337-18 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.50 (.0197) BSC 0.305 ±0.038 (.0120 ±.0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.280 ±0.076 (.011 ±.003) REF 16151413121110 9 GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS16) 0213 REV A 233718f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2337-18 23 LTC2337-18 Typical Application LT1469 Configured to Convert a ±10.24V Single-Ended Signal to a ±20.48V Differential Signal 15V 8 10.24V 0V –10.24V 2 3 4.99k 6 5 – + 1 5V IN+ 7 4 VDD LTC2337-18 LT1469 – + 4.99k 10.24V 0V –10.24V 10.24V 0V –10.24V IN– REFBUF REFIN 47µF –15V 100nF 233718 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS ADCs LTC2379-18/LTC2378-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps LTC2377-18/LTC2376-18 Serial, Low Power ADC 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps LTC2377-16/LTC2376-16 Serial, Low Power ADC 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2369-18/LTC2368-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps LTC2367-18/LTC2364-18 Serial, Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps LTC2367-16/LTC2364-16 Serial, Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages LTC1609 16-Bit, 200ksps Serial ADC ±10V, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and SO-20 Packages LTC1606/LTC1605 16-Bit, 250ksps/100ksps Parallel ADCs ±10V, 75mW/55mW 5V Pin Compatible ADCs LTC1859/LTC1858/ LTC1857 16-/14-/12-Bit, 8-Channel 100ksps Serial ADCs ±10V, SoftSpan™, Single-Ended or Differential Inputs, Single 5V Supply, SSOP-28 Package LTC2756/LTC2757 18-Bit, Single Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-48 Package LTC2641 16-Bit/14-Bit/12-Bit Single Serial VOUT DAC ±1LSB INL /DNL, MSOP-8 Package, 0V to 5V Output LTC2630 12-Bit/10-Bit/8-Bit Single VOUT DACs Internal Reference, ±1LSB INL (12 Bits), SC70 6-Pin Package LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package DACs References Amplifiers LT1468/LT1469 Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Low Input Offset: 75μV/125µV Op Amp 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2337-18 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2337-18 233718f LT 0913 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013