MOTOROLA MAC7131VVF Mac7100 microcontroller family hardware specification Datasheet

Freescale Semiconductor, Inc.
Advance Information
MAC7100EC/D
Rev. 0.1, 10/2003
Freescale Semiconductor, Inc...
MAC7100 Microcontroller
Family Hardware
Specifications
32-bit Embedded
Controller Division
This document provides electrical specifications, pin assignments, and package diagrams for
MAC7100 family of microcontroller devices. For functional characteristics of the family,
refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D).
This document contains the following topics:
Topic
Page
Section 1, “Overview”
1
Section 2, “Ordering Information”
2
Section 3, “Electrical Characteristics”
3
Section 4, “Device Pin Assignments”
36
Section 5, “Mechanical Information”
41
1
Overview
The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family
of 32-bit Flash-memory-based devices developed specifically for embedded automotive
applications. The pin-compatible family concept enables users to select between different
memory and peripheral options for scalable designs. All MAC7100 Family members are
composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded
Flash EEPROM for program storage, up to 32Kbytes of embedded Flash for data and/or
program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced
DMA (eDMA) controller to improve performance for transfers between memory and many of
the on-chip peripherals. The peripheral set includes asynchronous serial communications
interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I2C) bus
controllers, FlexCAN interfaces, an enhanced modular I/O subsystem (eMIOS), 10-bit
analog-to-digital converter (ATD) channels, general-purpose timers (PIT) and two
special-purpose timers (RTI and SWT). The peripherals share a large number of general
purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt
capability to trigger wake-up from low-power chip modes.
The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. The operating frequency of devices in the family is up to a
maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and
peripherals are all 32 bits wide, further improving performance for 32-bit applications. The
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Ordering Information
MAC7111 and MAC7131 also offer a 16-bit wide external data bus with 22 address lines. The family of
devices is capable of operating over a junction temperature range of -40° C to 150° C.
Table 1 provides a comparison of members of the MAC7100 Family and the availability of peripheral
modules on the various devices.
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Table 1. MAC7100 Family Device Derivatives
Module Options
MAC7101
MAC7111
MAC7121
MAC7131
MAC7141
Program Flash
512Kbytes
512Kbytes
512Kbytes
512Kbytes
512Kbytes
Data Flash
32Kbytes
32Kbytes
32Kbytes
32Kbytes
32Kbytes
SRAM
32Kbytes
32Kbytes
32Kbytes
32Kbytes
32Kbytes
External Bus
No
Yes
No
Yes
No
ATD Modules
2
1
1
2
1
CAN Modules
4
4
4
4
2
eSCI Modules
4
4
4
4
2
DSPI Modules
2
2
2
2
2
I2C Modules
1
1
1
1
1
eMIOS Module
16 channels,
16-bit
16 channels,
16-bit
16 channels,
16-bit
16 channels,
16-bit
16 channels,
16-bit
Timer Module
10 channels,
24-bit
10 channels,
24-bit
10 channels,
24-bit
10 channels,
24-bit
10 channels,
24-bit
GPIO Pins (max.)
111
111
84
127
71
Package
144 LQFP
144 LQFP
112 LQFP
208 MAP BGA
100 LQFP
2
Ordering Information
M AC 7 1 0 1 C PV 50 xx
Temperature Option
C = –40° C to 85° C
V = –40° C to 105° C
M = –40° C to 125° C
MC Status
Core Code
Core Number
Generation / Family
Package Option
Device Number
Temperature Range
Package Identifier
Speed (MHz)
Optional Package Identifiers
Package Option
FU = 100 QFP
PV = 112 / 144 LQFP
VF = 208 MAP BGA
Figure 1. Order Part Number Example
2
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Electrical Characteristics
3
Electrical Characteristics
This section contains electrical information for MAC7100 Family microcontrollers. The information is
preliminary and subject to change without notice.
MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any
voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done
to verify operation at intermediate supply voltage levels.
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3.1
Parameter Classification
The electrical parameters shown in this appendix are derived by various methods. To provide a better
understanding to the designer, the following classification is used. Parameters are tagged accordingly in in
the column labeled “C” of the parametric tables, as appropriate.
Table 2. Parametric Value Classification
3.2
P
Parameters guaranteed during production testing on each individual device.
C
Parameters derived by the design characterization and by measuring a statistically relevant
sample size across process variations.
T
Parameters derived by design characterization on a small sample size from typical devices
under typical conditions (unless otherwise noted). All values shown in the typical column
are within this classification, even if not so tagged.
D
Parameters derived mainly from simulations.
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not
guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device.
MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (for example, either VSS5 or VDD5).
Table 3. Absolute Maximum Ratings
Num
Rating
A1
I/O, Regulator and Analog Supply Voltage
A2
Digital Logic Supply Voltage 1
Voltage 1
Symbol
Min
Max
Unit
VDD5
–0.3
+6.0
V
VDD2.5
–0.3
+3.0
V
VDDPLL
–0.3
+3.0
V
VDDA
–0.3
+6.5
V
VRH, VRL
–0.3
+6.0
V
Voltage difference VDDX to VDDA
∆VDDX
–0.3
+0.3
V
Voltage difference VSSX to VSSA
∆VSSX
–0.3
+0.3
V
VRH – VRL
–0.3
+6.5
V
VDDA – VRH
–6.5
+6.5
V
VIN
–0.3
+6.0
V
A3
PLL Supply
A4
ATD Supply Voltage
A5
Analog Reference
A6
A7
A8
Voltage difference VRH – VRL
A9
Voltage difference VDDA – VRH
A10
Digital I/O Input Voltage
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Electrical Characteristics
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Table 3. Absolute Maximum Ratings (continued)
Num
Rating
A11
XFC, EXTAL, XTAL inputs
A12
TEST input
A14
A15
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1
2
3
4
5
Single pin limit for XFC, EXTAL, XTAL 3
Single pin limit for all digital I/O
pins 4
Single pin limit for all analog input pins
4
5
A16
Single pin limit for TEST
A17
Storage Temperature Range
Min
Max
Unit
VILV
–0.3
+3.0
V
VTEST
–0.3
+10.0
V
IDL
–25
+25
mA
ID
–25
+25
mA
IDA
–25
+25
mA
IDT
–0.25
0
mA
–65
+155
°C
2
Instantaneous Maximum Current
A13
Symbol
T
stg
The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The
absolute maximum ratings apply when the device is powered from an external source.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using VPOSCLAMP = VDDA + 0.3 V and VNEGCLAMP = –0.3 V, then use the larger of the
calculated values.
These pins are internally clamped to VSSPLL and VDDPLL.
All I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications.
3.3
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise.
Table 4. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
4
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulses per pin
positive
negative
—
—
3
3
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
—
—
3
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
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Electrical Characteristics
Table 5. ESD and Latch-Up Protection Characteristics
Num
Rating
Symbol
Min
Max
Unit
B1
C Human Body Model (HBM)
VHBM
2000
—
V
B2
C Machine Model (MM)
VMM
200
—
V
B3
C Charge Device Model (CDM)
VCDM
500
—
V
B4
C Latch-up Current at TA = 125°C
positive
negative
ILAT
+100
–100
—
C Latch-up Current at TA = 27°C
positive
negative
ILAT
B5
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C
3.4
mA
—
mA
+200
–200
Operating Conditions
Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature
rating of the device (C, V, M) with respect to ambient temperature (TA) and junction temperature (TJ). For
power dissipation calculations refer to Section 3.5, “Power Dissipation and Thermal Characteristics.”
Table 6. MAC7100 Family Device Operating Conditions
Num
C1
Rating
I/O, Regulator and Analog Supply Voltage
Voltage 1
Symbol
Min
Typ
Max
Unit
VDD5
4.5
5
5.5
V
VDD2.5
2.35
2.5
2.75
V
C3
PLL Supply
Voltage 1
VDDPLL
2.35
2.5
2.75
V
C4
Voltage Difference VDDX to VDDA
∆VDDX
–0.1
0
0.1
V
C5
Voltage Difference VSSX to VSSA
∆VSSX
–0.1
0
0.1
V
C6
Oscillator Frequency
fosc
0.5
—
16
MHz
C7
Bus Frequency
fbus
0.5
—
50
MHz
TJ
–40
—
110
°C
T
–40
25
85
°C
C2
Digital Logic Supply
C8a
MAC7100C Operating Junction Temperature Range
C8b
Operating Ambient Temperature Range 2
C9a
MAC7100V Operating Junction Temperature Range
TJ
–40
—
130
°C
C9b
Operating Ambient Temperature Range 2
TA
–40
25
105
°C
C10a MAC7100M Operating Junction Temperature Range
TJ
–40
—
150
°C
Operating Ambient Temperature Range 2
TA
–40
25
125
°C
2
2
2
C10b
A
1
The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source.
2
Please refer to Section 3.5, “Power Dissipation and Thermal Characteristics,” for more details about the relation
between ambient temperature TA and device junction temperature TJ.
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Electrical Characteristics
3.4.1
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5 V I/O Pins
The I/O pins operate at a nominal level of 5 V. This class of pins is comprised of the clocks, control and general
purpose/peripheral pins. The internal structure of these pins is identical; however, some functionality may be
disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled).
3.4.2
Oscillator Pins
The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5 V.
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3.5
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded.
Note that the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-toambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA
(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for
junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic
name, θJA, will continue to be commonly used.
The average chip-junction temperature (TJ) in °C is obtained from:
T J = T A + ( Θ JA )
T J = Junction Temperature ( ° C)
T A = Ambient Temperature ( ° C)
P D = Total Chip Power Dissipation (W)
Θ JA = Package Thermal Resistance ( ° C/W)
The total power dissipation is calculated from:
P D = P INT + P IO
P INT = Chip Internal Power Dissipation (W)
P INT = ( I DD × V DD ) + ( I DD PLL × V DD PLL ) + ( I DD A × V DD A )
Two cases for PIO, with the internal voltage regulator enabled and disabled, must be considered:
1. Internal Voltage Regulator disabled:
P IO =
∑ RDSON ⋅ ( IIO ) 2
i
i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
V OL
R DSON = ---------- (for outputs driven low)
I OL
or
V DD 5 – V OH
R DSON = ------------------------------- (for outputs driven high)
I OL
2. Internal voltage regulator enabled:
P INT = ( I DD R × V DD R ) + ( I DD A × V DD A )
IDDR is the current shown in Table 12 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
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Electrical Characteristics
3.5.1
Power Dissipation Simulation Details
Table 7. Thermal Resistance for 100 lead 14x14 mm LQFP, 0.5 mm Pitch 1
Rating
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
1
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Value
44
34
37
29
18
7
2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Comments
1, 2
1, 3
1, 3
1, 3
4
5
6
100 LQFP, Case Outline: 983–02
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Table 8. Thermal Resistance for 112 lead 20x20 mm LQFP, 0.65 mm Pitch 1
Rating
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
1
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Value
42
34
35
30
22
7
2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Comments
1, 2
1, 3
1, 3
1, 3
4
5
6
112 LQFP, Case Outline: 987–01
Table 9. Thermal Resistance for 144 lead 20x20 mm LQFP, 0.5 mm Pitch 1
Rating
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
1
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Value
42
34
35
30
22
7
2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Comments
1, 2
1, 3
1, 3
1, 3
4
5
6
144 LQFP, Case Outline: 918–03
Table 10. Thermal Resistance for 208 lead 17x17 mm MAP, 1.0 mm Pitch 1
Rating
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
1
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Value
46
29
38
26
19
7
2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Comments
1, 2
1, 3
1, 3
1, 3
4
5
6
208 MAP BGA, Case Outline: 1159A-01
Comments:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board at the center lead. For fused lead packages, the adjacent lead is used.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC
JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
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Electrical Characteristics
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Table 11. Power Dissipation 1/8 Simulation Model Packaging Parameters
Component
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3.6
Conductivity
Mold Compound
0.9 W/m K
Leadframe (Copper)
263 W/m K
Die Attach
1.7 W/m K
Power Supply
The MAC7100 Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports
and ATD. In the context of this section, VDD5 is used for VDDA, VDDR or VDDX; VSS5 is used for VSSA,
VSSR or VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX,
and VDDR. VDD is used for VDD2.5, and VDDPLL, VSS is used for VSS2.5 and VSSPLL. IDD is used for the
sum of the currents flowing into VDD2.5 and VDDPLL.
3.6.1
Current Injection
The power supply must maintain regulation within the VDD5 or VDD2.5 operating range during
instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is
greater than IDD5, the injection current may flow out of VDD5 and could result in the external power supply
going out of regulation. It is important to ensure that the external VDD5 load will shunt current greater than
the maximum injection current. The greatest risk will be when the MCU is consuming very little power (for
example, if no system clock is present, or if the clock rate is very low).
3.6.2
Power Supply Pins
The VDDR – VSSR pair supplies the internal voltage regulator. The VDDA – VSSA pair supplies the A/D
converter and the reference circuit of the internal voltage regulator. The VDDX – VSSX pair supplies the I/O
pins. VDDPLL – VSSPLL pair supplies the oscillator and PLL.
All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. All
VSS2.5 pins are internally connected by metal. VDDA, VDDX and VDDR as well as VSSA, VSSX and VSSR
are connected by anti-parallel diodes for ESD protection.
3.6.3
Supply Currents
All current measurements are without output loads. Unless otherwise noted the currents are measured in
single chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator
in low power mode. Production testing is performed using a square wave signal at the EXTAL input.
In expanded modes, the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A good estimate is to take the single chip currents and add the currents due to the external loads.
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Electrical Characteristics
Table 12. Supply Current Characteristics
C
D1c
C
D2
D3a
C Doze Supply Current
C Psuedo Stop Current
PLL on
D3b
C
D3c
C
D4a
C Stop Current
TJ = TA assumed
D4b
C
D4c
C
Core
Regulator
(if enabled)
D1b
2
Pins
Regulator
Core
Pins
Regulator
Core
Pins
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Num C
Rating
D1a C Run Supply Current
Single Chip
–40° C
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
–40° C 2
25° C 2
85° C 2
105° C 2
125° C 2
Symbol
IDDRcore
Typ
—1
—1
—1
—1
—1
IDDRreg
—1
—1
—1
—1
—1
IDDRpins
—1
—1
—1
—1
—1
Run ≥ Doze ≥ Pseudo Stop
IDDPScore
—1
—1
—1
—1
—1
IDDPSreg
—1
278 / 327 3
—1
—1
—1
IDDPSpins
—1
4/53
—1
—1
—1
IDDScore
—1
—1
—1
—1
—1
IDDSreg
—1
68
—1
—1
—1
IDDSpins
—1
4
—1
—1
—1
Max
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
—1
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
1
At the time of publication, this value is yet to be determined, and will be supplied when device characterization is complete.
85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
3 RTI disabled / enabled.
2
MOTOROLA
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9
Electrical Characteristics
3.6.4
Freescale Semiconductor, Inc.
Voltage Regulator Characteristics
Table 13. VREG Operating Conditions
Num
Characteristic
Symbol
Min
Typical
Max
Unit
VVDDRA
2.97
—
5.5
V
—
—
TBD
TBD
50
40
µA
µA
2.45
1.60
—
2.5
2.5
—1
2.75
2.75
—
V
V
V
2.35
2.00
1.60
—
2.5
2.5
2.5
—1
2.75
2.75
2.75
—
V
V
V
V
E1
P Input Voltages
E2
P Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
P Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode
VDD
P Output Voltage PLL
Full Performance Mode
Reduced Power Mode 2
Reduced Power Mode 3
Shutdown Mode
VDDPLL
E3
E4
Freescale Semiconductor, Inc...
C
E5
E6
E7
1
2
3
4
5
6
10
P Low Voltage Interrupt 4
Assert Level
Deassert Level
VLVIA
VLVID
4.10
4.25
4.37
4.52
4.66
4.77
V
V
P Low Voltage Reset 5
Assert Level
VLVRA
2.25
2.35
—
V
VPORA
VPORD
0.97
—
—
—
—
2.05
V
V
6
P Power On Reset
Assert Level
Deassert Level
High Impedance Output.
Current IDDPLL = 1mA (Low Power Oscillator).
Current IDDPLL = 3mA (Standard Oscillator).
Monitors VDDA, active only in full performance mode. Indicated I/O and ATD performance degradation due to low supply
voltage.
Monitors VDD2.5, active only in full performance mode. Only POR is active in reduced performance mode.
Monitors VDD2.5, active in all modes.
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Electrical Characteristics
3.6.5
Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Refer to Figure 2.
Voltage
VDDA
VLVID
VLVIA
VDD2.5
Freescale Semiconductor, Inc...
VLVRD
VLVRA
VPORD
LVI Enabled
LVI
LVI Disabled
due to LVR
Time
POR
LVR
Note: Not to scale.
Figure 2. VREG Chip Power-up and Voltage Drops
3.6.6
Output Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC
load is allowed. Capacitive loads are specified in Table 14. Capacitors with X7R dielectricum are required.
Table 14. VREG Recommended Load Capacitances
Rating
Load Capacitance on each VDD2.5 pin
Load Capacitance on VDDPLL pin
MOTOROLA
Symbol
Min
Typ
Max
Unit
CLVDD
200
440
12000
nF
CLVDDfcPLL
90
220
5000
nF
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Electrical Characteristics
3.7
Freescale Semiconductor, Inc.
I/O Characteristics
This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All
parameters are not always applicable; for example, not all pins feature pull up/down resistances.
Table 15. 5 V I/O Characteristics
Conditions shown in Table 6 unless otherwise noted
Freescale Semiconductor, Inc...
Num C
Rating
Symbol
Min
Typ
Max
Unit
0.65 ×
VDD5
—
—
V
F1a
P Input High Voltage
V
F1b
T Input High Voltage
VIH
—
—
VDD5 +
0.3
V
F2a
P Input Low Voltage
VIL
—
—
0.35 ×
VDD5
V
F2b
T Input Low Voltage
VIL
VSS5 –
0.3
—
—
V
F3
C Input Hysteresis
VHYS
—
250
—
mV
TBD
—
TBD
µA
VDD5 –
0.8
—
—
V
F4
P
Input Leakage Current (pins in high impedance input mode) 1
I
Vin = VDD5 or VSS5
IH
in
F5
P Output High Voltage (pins in output mode)
Partial Drive IOH = –2mA
Full Drive IOH = –10mA
VOH
F6
P Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
Full Drive IOL = +10mA
V
—
—
0.8
V
F7
P Internal Pull Up Device Current,
tested at VIL Max.
IPUL
—
—
–130
µA
F8
P Internal Pull Up Device Current,
tested at VIH Min.
IPUH
–10
—
—
µA
F9
P Internal Pull Down Device Current,
tested at VIH Min.
IPDH
—
—
130
µA
F10
P Internal Pull Down Device Current,
tested at VIL Max.
IPDL
10
—
—
µA
F11
D Input Capacitance
Cin
—
6
—
pF
F12
current 2
IICS
IICP
–2.5
–25
T Injection
Single Pin limit
Total Device Limit. Sum of all injected currents
OL
µA
—
2.5
25
F13
P Port Interrupt Input Pulse filtered 3
tPULSE
—
—
3
µs
F14
P Port Interrupt Input Pulse passed 3
tPULSE
10
—
—
µs
1
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
2
Refer to Section 3.6.1, “Current Injection,” for more details
3 Parameter only applies in STOP or Pseudo STOP mode.
12
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Table 16. 3.3 V I/O Characteristics
Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.
Num C
Symbol
Min
Typ
Max
Unit
G1a P Input High Voltage
VIH
0.65 ×
VDD5
—
—
V
G1b T Input High Voltage
VIH
—
—
VDD5 +
0.3
V
G2a P Input Low Voltage
VIL
—
—
0.35 ×
VDD5
V
G2b T Input Low Voltage
VIL
VSS5 –
0.3
—
—
V
VHYS
—
250
—
mV
Iin
TBD
—
TBD
µA
VDD5 –
0.4
—
—
V
Freescale Semiconductor, Inc...
G3
Rating
C Input Hysteresis
1
G4
P Input Leakage Current (pins in high impedance input mode)
V = V 5 or V 5
G5
P Output High Voltage (pins in output mode)
Partial Drive IOH = –0.75mA
Full Drive IOH = –4.5mA
V
G6
P Output Low Voltage (pins in output mode)
Partial Drive IOL = +0.9mA
Full Drive IOL = +5.5mA
VOL
—
—
0.4
V
G7
P Internal Pull Up Device Current,
tested at VIL Max.
IPUL
—
—
–60
µA
G8
P Internal Pull Up Device Current,
tested at VIH Min.
IPUH
–6
—
—
µA
G9
P Internal Pull Down Device Current,
tested at VIH Min.
IPDH
—
—
60
µA
G10 P Internal Pull Down Device Current,
tested at VIL Max.
IPDL
6
—
—
µA
G11 D Input Capacitance
Cin
—
6
—
pF
IICS
IICP
–2.5
–25
G13 P Port Interrupt Input Pulse filtered 3
tPULSE
—
—
3
µs
G14 P Port Interrupt Input Pulse passed 3
tPULSE
10
—
—
µs
in
DD
SS
OH
current 2
G12 T Injection
Single Pin limit
Total Device Limit. Sum of all injected currents
µA
—
2.5
25
1
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
2 Refer to Section 3.6.1, “Current Injection,” for more details
3 Parameter only applies in STOP or Pseudo STOP mode.
MOTOROLA
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13
Electrical Characteristics
3.8
Freescale Semiconductor, Inc.
Clock and Reset Generator Electrical
Characteristics
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and
reset generator.
Freescale Semiconductor, Inc...
3.8.1
Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET signal.
Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the
oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the
maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is
not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also
features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal
is below the Clock Monitor Assert Frequency fCMFA.
Table 17. Oscillator Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
H1a C Crystal oscillator range (loop controlled Pierce)
fOSC
4.0
—
16
MHz
H1b C Crystal oscillator range (full swing Pierce) 1, 2
fOSC
0.5
—
40
MHz
H2
IOSC
100
—
—
µA
50 4
ms
P Startup Current
H3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
—
TBD 3
H4
D Clock Quality check time-out
tCQOUT
0.45
—
2.5
s
H5
P Clock Monitor Failure Assert Frequency
fCMFA
50
100
200
KHz
H6
P External square wave input frequency
2
fEXT
0.5
—
40
MHz
H7
D External square wave pulse width low
tEXTL
9.5
—
—
ns
H8
D External square wave pulse width high
tEXTH
9.5
—
—
ns
H9
D External square wave rise time
tEXTR
—
—
1
ns
tEXTF
—
—
1
ns
CIN
—
7
—
pF
VDCBIAS
—
TBD
—
V
H10 D External square wave fall time
H11 D Input Capacitance (EXTAL, XTAL pins)
H12 C EXTAL pin DC Operating Bias in loop controlled
mode
1
Depending on the crystal; a damping series resistor might be necessary
XCLKS negated during reset
3
fosc = 4 MHz, C = 22 pF.
4
Maximum value is for extreme cases using high Q, low frequency crystals
2
14
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MOTOROLA
Electrical Characteristics
3.8.2
Freescale Semiconductor, Inc.
PLL Filter Characteristics
The oscillator provides the reference clock for the PLL. The voltage controlled oscillator (VCO) of the PLL
is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select
proper values for external loop filter components.
VDDPLL
Phase
Detector
Freescale Semiconductor, Inc...
fOSC
1
REFDV+1
fREF
∆
CS
CP
VCO
R
Kφ
fCMP
KV
fVCO
Loop Divider
1
1
SYNR+1
2
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table 18. First, the VCO Gain at the desired VCO output frequency is
approximated by:
KV = K1 ⋅ e
( f 1 – f VCO )
-------------------------K 1 ⋅ 1V
The phase detector relationship is given by:
K Φ = – i ch ⋅ K V
ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner’s stability
criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f ref
f ref
1
- ;( ζ = 0.9 )
f C < ----------------------------------------  ------ → f C < ------------

50
4
⋅ 50
2
π ⋅ (ζ + 1 + ζ )
And finally the frequency relationship is defined as
f VCO
n = ----------- = 2 ⋅ ( synr + 1 )
f ref
With the above inputs the resistance can be calculated as:
2⋅π⋅n⋅f
R = ---------------------------CKΦ
The capacitance CS can now be calculated as:
2
2⋅ζ
0.516- ;( ζ = 0.9 )
C S = --------------------- ≈ ------------π ⋅ fC ⋅ R fC ⋅ R
The capacitance CP should be chosen in the range of:
C S ÷ 20 ≤ C P ≤ C S ÷ 10
The stabilization delays shown in Table 18 are dependant on PLL operational settings and external
component selection (for example, crystal, XFC filter).
15
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Electrical Characteristics
3.8.2.1
Freescale Semiconductor, Inc.
Jitter Information
The basic functionality of the PLL is shown in Figure 3. With each transition of the clock fcmp, the deviation
from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly. The adjustment
is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and
other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real
minimum and maximum clock periods as illustrated in Figure 4. It is important to note that the pre-scaler used
by timers and serial modules will eliminate the effect of PLL jitter to a large extent.
0
1
2
3
N–1
N
tMIN1
Freescale Semiconductor, Inc...
tNOM
tMAX1
tMIN(N)
tMAX(N)
Figure 4. Jitter Definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N). Thus, jitter is defined as:
t MAX ( N )
t MIN ( N ) 
J ( N ) = max  1 – -------------------- , 1 – --------------------
N⋅t
N⋅t
NOM
NOM
For N < 100, the following equation is a good fit for the maximum jitter:
j1
- + j2
J ( N ) = ------N
J(N)
0 1
5
10
15
20
N
Figure 5. Maximum Bus Clock Jitter Approximation
16
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MOTOROLA
Electrical Characteristics
3.8.3
Freescale Semiconductor, Inc.
PLL Characteristics
Table 18. PLL Characteristics
Num C
Freescale Semiconductor, Inc...
J1
Rating
PLL reference frequency, crystal oscillator range
1
Symbol
Min
Typ
Max
Unit
fREF
0.5
—
16
MHz
J2
P Self Clock Mode frequency
fSCM
1
—
5.5
MHz
J3
D VCO locking range
fVCO
8
—
40
MHz
J4
D Lock Detector transition from Acquisition to Tracking mode
|∆trk|
3
—
4
%2
J5
D Lock Detection
|∆Lock|
0
—
1.5
%2
J6
D Un-Lock Detection
|∆unl|
0.5
—
2.5
%2
J7
D Lock Detector transition from Tracking to Acquisition mode
|∆unt|
6
—
8
%2
J8
C PLLON Total Stabilization delay (Auto Mode) 3
tstab
—
0.5 4
35
ms
—
0.3
5
1
4
ms
5
2
4
ms
J9
D PLLON Acquisition mode stabilization delay
3
tacq
3
J10
D PLLON Tracking mode stabilization delay
tal
—
0.2
J11
D Charge pump current acquisition mode
| ich |
—
38.5
—
µA
J12
D Charge pump current tracking mode
| ich |
—
3.5
—
µA
J13
D Jitter fit VCO loop gain parameter
K1
—
–100
—
MHz/V
J14
D Jitter fit VCO loop frequency parameter
f1
—
60
—
MHz
J15
C Jitter fit parameter 1
j1
—
—
TBD
%4
J16
C Jitter fit parameter 2
j2
—
—
TBD
%4
1
VDDPLL at 2.5 V.
Percentage deviation from target frequency
3
PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
4 f
REF = 4 MHz, fSYS = 25 MHz (REFDV = 0x03, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS = 10 KΩ.
5 f
REF = 4 MHz, fSYS = 8 MHz (REFDV = 0x00, SYNR = 0x01), CS = 33 nF, CP = 3.3 nF, RS = 2.7 KΩ.
2
3.8.4
Crystal Monitor Time-out
The time-out Table 19 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
Table 19. Crystal Monitor Time-Outs
3.8.5
Min
Typ
Max
Unit
6
10
18.5
µs
Clock Quality Checker
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 18. These numbers define the upper time limit for the individual check windows to complete.
Table 20. CRG Maximum Clock Quality Check Timings
17
Clock Check Windows
Value
Unit
Check Window
9.1 to 20.0
ms
Timeout Window
0.46 to 1.0
s
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Electrical Characteristics
3.8.6
Freescale Semiconductor, Inc.
Startup
Table 21 summarizes several startup characteristics explained in this section. Refer to the MAC7100
Microcontroller Family Reference Manual (MAC7100RM/D) for a detailed description of the startup
behavior.
Table 21. CRG Startup Characteristics
Freescale Semiconductor, Inc...
Num C
Rating
Symbol
Min
Typ
Max
Unit
K1
T POR release level
VPORR
—
—
2.07
V
K2
T POR assert level
VPORA
0.97
—
—
V
K3
D Reset input pulse width, minimum input time
PWRSTL
2
—
—
tosc
K4
D Startup from Reset
nRST
192
—
196
nosc
K5
D Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ
20
—
—
ns
K6
D Wait recovery startup time
tWRS
—
—
14
tcyc
3.8.6.1
Power On and Low Voltage Reset (POR and LVR)
The release level VPORR and the assert level VPORA are derived from the VDD2.5 supply. The assert level
VLVRA is derived from the VDD2.5 supply. They are also valid if the device is powered externally. After
releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time tCQOUT
no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup
time possible is given by tuposc (refer to Table 17).
3.8.6.2
SRAM Data Retention
The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a
reset operation.
3.8.6.3
External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG module generates an internal reset
and the CPU starts fetching the reset vector without doing a clock quality check, if there was stable
oscillation before reset.
3.8.6.4
Stop Recovery
The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check
is performed in the same manner as for POR before releasing the clocks to the system.
3.8.6.5
Pseudo Stop and Doze Recovery
Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in
either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events
in the system. After twrs, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or
continues to execute code if the wakeup event was not an interrupt.
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MOTOROLA
Electrical Characteristics
3.9
Freescale Semiconductor, Inc.
External Bus Timing Specifications
Table 22 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
Table 22. External Bus Input Timing Specifications
Num
Freescale Semiconductor, Inc...
L1
Rating 1
C
Symbol
Min
Max
Unit
tCYC
23
—
ns
tCVCH
13
—
ns
tCHCII
0
—
ns
CLKOUT
Control Inputs
high 2
L2a
Control input valid to CLKOUT
L3a
CLKOUT high to control inputs invalid 2
Data Inputs
1
2
L4
Data input (DATA[15:0]) valid to CLKOUT high
tDIVCH
9
—
ns
L5
CLKOUT high to data input (DATA[15:0]) invalid
tCHDII
0
—
ns
Timing specifications have been indicated taking into account the full drive strength for the pads.
TA pins are being referred to as control inputs.
1.5 V
CLKOUT(45MHz)
tSETUP
tHOLD
Input Setup & Hold
Invalid
Input Rise Time
VH = VIH
VL = VIL
Input Fall Time
VH = VIH
VL = VIL
1.5 V Valid 1.5 V
Invalid
tRISE = 1.5 ns
tFALL = 1.5 ns
CLKOUT
L4
L5
Inputs
Figure 6. General Input Timing Requirements
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Electrical Characteristics
3.9.1
Freescale Semiconductor, Inc.
Read and Write Bus Cycles
Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7
and Figure 8.
Table 23. External Bus Output Timing Specifications
Num
C
Rating
Symbol
Min
Max
Unit
tCHCV
—
0.5tCYC + 10
ns
tCHBV
—
0.5tCYC + 10
ns
Control Outputs
Freescale Semiconductor, Inc...
L6a
CLKOUT high to chip selects valid
1
2
L6b
CLKOUT high to byte select (BS[1:0]) valid
L6c
CLKOUT high to output select (OE) valid 3
tCHOV
—
0.5tCYC + 10
ns
L7a
CLKOUT high to control output (BS[1:0], OE) invalid
tCHCOI
0.5tCYC + 2
—
ns
L7b
CLKOUT high to chip selects invalid
tCHCI
0.5tCYC + 2
—
ns
Address and Attribute Outputs
L8
CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
tCHAV
—
10
ns
L9
CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
tCHAI
2
—
ns
Data Outputs
1
2
3
20
L10
CLKOUT high to data output (DATA[15:0]) valid
tCHDOV
—
13
ns
L11
CLKOUT high to data output (DATA[15:0]) invalid
tCHDOI
2
—
ns
L12
CLKOUT high to data output (DATA[15:0]) high impedance
tCHDOZ
—
9
ns
CSn transitions after the falling edge of CLKOUT.
BSn transitions after the falling edge of CLKOUT.
OE transitions after the falling edge of CLKOUT.
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S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
L6a
L6a
L7b
L7b
CSn
L8
L8
L9
ADDR[21:0]
L1
L6c
L7a
Freescale Semiconductor, Inc...
OE
L8
L9
R/W
L6b
L6b
L7a
L7a
BS[1:0]
L10
L4
L11
DATA[15:0]
L5
L12
TA (H)
Figure 7. Read/Write (Internally Terminated) Bus Timing
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S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
L6a
L7b
CSn
L8
L9
ADDR[21:0]
L6c
L7a
Freescale Semiconductor, Inc...
OE
R/W
L6b
L7a
BS[1:0]
L4
L5
DATA[15:0]
L2a
L3a
TA
Figure 8. Read Bus Cycle Terminated by TA
22
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3.10 Analog-to-Digital Converter Characteristics
Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to
obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the
sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside
of this range it will effectively be clipped.
Table 24. ATD Operating Characteristics in 5 V Range
Conditions shown in Table 6 unless otherwise noted
Freescale Semiconductor, Inc...
Num C
Rating
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA ÷ 2
—
—
VDDA ÷ 2
VDDA
V
V
VRH – VRL
4.50
5.00
5.25
V
fATDCLK
0.5
—
2.0
MHz
M4
D ATD 10-bit Conversion PeriodClock
NCONV10
@ 2.0MHz fATDCLK TCONV10
14
7
—
—
28
14
Cycles
µs
M5
D ATD 8-bit Conversion PeriodClock Cycles 2
@ 2.0MHz fATDCLK
NCONV8
TCONV8
12
6
—
—
26
13
Cycles
µs
M6
D Recovery Time (VDDA = 5.0 V)
tREC
—
—
20
µs
M7
P Reference Supply current 1 ATD module enabled
IREF
—
—
0.375
mA
M8
P Reference Supply current 2 ATD modules enabled
IREF
—
—
0.750
mA
M1
D Reference Potential
M2
C Differential Reference Voltage 1
M3
D ATD Clock Frequency
1
Low
High
Cycles 2
Full accuracy is not guaranteed when differential voltage is less than 4.50 V
Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.
2
Table 25. ATD Operating Characteristics in 3.3 V Range
Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.
Num C
Rating
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA ÷ 2
—
—
VDDA ÷ 2
VDDA
V
V
VRH–VRL
3.0
3.3
3.6
V
fATDCLK
0.5
—
2.0
MHz
N4
D ATD 10-bit Conversion PeriodClock
NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10
14
7
—
—
28
14
Cycles
µs
N5
D ATD 8-bit Conversion PeriodClock Cycles 2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
12
6
—
—
26
13
Cycles
µs
N6
D Recovery Time (VDDA=5.0 V)
tREC
—
—
20
µs
N7
P Reference Supply current 1 ATD module enabled
IREF
—
—
0.375
mA
N8
P Reference Supply current 2 ATD modules enabled
IREF
—
—
0.250
mA
N1
D Reference Potential
N2
C Differential Reference Voltage 1
N3
D ATD Clock Frequency
1
2
Low
High
Cycles 2
Full accuracy is not guaranteed when differential voltage is less than 3.0 V
Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.
3.10.1 Factors Influencing Accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the
accuracy of the ATD.
23
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3.10.1.1 Source Resistance
Due to the input pin leakage current as specified in Table 15 in conjunction with the source resistance there
will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance RS,
results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or operating
conditions are less than the worst case, or leakage-induced errors are acceptable, larger values of source
resistance are allowed.
3.10.1.2 Source Capacitance
Freescale Semiconductor, Inc...
When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of
the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as, Cf ≥ 1024 × (CINS – CINN).
3.10.1.3 Current Injection
There are two cases to consider:
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than VRH and 0x000 for values less
than VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the
accuracy of the conversion depending on the source resistance. The additional input voltage error
on the converted channel can be calculated as VERR = K × RS × IINJ, with IINJ being the sum of the
currents injected into the two pins adjacent to the converted channel.
Table 26. ATD Electrical Characteristics
Conditions are shown in Table 6 unless otherwise noted
Num C
Rating
P1
C Max input Source Resistance
P2
T Total Input Capacitance
Non Sampling
Sampling
Symbol
Min
Typ
Max
Unit
RS
—
—
1
KΩ
CINN
CINS
—
—
—
—
10
22
pF
pF
P3
C Disruptive Analog Input Current
INA
–2.5
—
2.5
mA
P4
C Coupling Ratio positive current injection
Kp
—
—
TBD
A/A
P5
C Coupling Ratio negative current injection
Kn
—
—
TBD
A/A
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3.10.2 ATD Accuracy
Table 27 and Table 28 specify the ATD conversion performance excluding any errors due to current
injection, input capacitance and source resistance.
Table 27. ATD Conversion Performance in 5 V Range
Conditions shown in Table 6 unless otherwise noted.
VREF = VRH – VRL = 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Freescale Semiconductor, Inc...
Num C
Rating
Symbol
Min
Typ
Max
Unit
Q1
P 10-bit Resolution
LSB
—
5
—
mV
Q2
P 10-bit Differential Nonlinearity
DNL
–1
—
1
Counts
Q3
P 10-bit Integral Nonlinearity
INL
–2.5
±1.5
2.5
Counts
Q4
P 10-bit Absolute Error 1
AE
–3
±2.0
3
Counts
Q5
P 8-bit Resolution
LSB
—
20
—
mV
Q6
P 8-bit Differential Nonlinearity
DNL
–0.5
—
0.5
Counts
Q7
P 8-bit Integral Nonlinearity
INL
–1.0
±0.5
1.0
Counts
Q8
P 8-bit Absolute Error 1
AE
–1.5
±1.0
1.5
Counts
1
These values include the quantization error which is inherently 1/2 count for any A/D converter.
Table 28. ATD Conversion Performance in 3.3 V Range
Conditions shown in Table 6 unless otherwise noted.
VREF = VRH – VRL = 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
3.25
—
mV
R1
P 10-bit Resolution
LSB
—
R2
P 10-bit Differential Nonlinearity
DNL
–1.5
—
1.5
Counts
R3
P 10-bit Integral Nonlinearity
INL
–3.5
±1.5
3.5
Counts
Error 1
R4
P 10-bit Absolute
AE
–5
±2.0
5
Counts
R5
P 8-bit Resolution
LSB
—
13
—
mV
R6
P 8-bit Differential Nonlinearity
DNL
–0.5
—
0.5
Counts
R7
P 8-bit Integral Nonlinearity
INL
–1.5
±1.0
1.5
Counts
AE
–1.5
±1.0
1.5
Counts
R8
1
P 8-bit Absolute
Error 1
These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure 8.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
–1
DNL ( i ) = ----------------------1 LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑ DNL ( i )
i=1
25
Vn – V0
= ------------------–n
1 LSB
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10-bit Absolute Error Boundary
0x3FF
0x3FE
8-bit Absolute Error Boundary
DNL
0x3FD
0xFF
0x3FC
LSB
0x3FB
VI–1
0x3FA
VI
0x3F9
0xFE
0x3F8
0x3F6
0x3F5
0xFD
0x3F4
0x3F3
8-bit Resolution
10-bit Resolution
Freescale Semiconductor, Inc...
0x3F7
9
2
8
7
Ideal Transfer Curve
6
5
10-bit Transfer Curve
1
4
3
2
8-bit Transfer Curve
1
0
VIN
0
10
5
20
15
30
25
40 50
35
5055 5065 5075 5085 5095 5105 5115
5060 5070 5080 5090 5100 5110 5120
mV
Figure 9. ATD Accuracy Definitions
NOTE
Figure 8 shows only definitions, for specification values refer to Table 27.
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3.10.3 ATD Electrical Specifications
Table 29 lists the DC electrical characteristics for the ATD module. Table 27 lists the analog-to-digital
conversion performance specifications.
Table 29. ATD Electrical Characteristics (Operating) 1
Freescale Semiconductor, Inc...
Num C
Rating
2
S1
S2
Reference Potential Low
S3
Voltage Difference VRH – VRL 3
S4
Analog Input Voltage
S5
S6
Digital Input
Voltage
S7
Analog Supply
Current
High
High
Low
S8
–40°C 4
Run
Pseudo
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA ÷ 2
—
—
VDDA ÷ 2
VDDA
V
V
VRH – VRL
4.5
—
5.5
V
VINDC
–0.3
—
VDDA + 0.3
V
VIH
VIL
0.7 × VDDA
VSSA – 0.3
—
—
VDDA + 0.3
0.2 × VDDA
V
V
IDDArun
—
TBD
TBD
mA
25°C 4
—
TBD
TBD
mA
85°C 4
—
TBD
TBD
mA
105°C 4
—
TBD
TBD
mA
125°C 4
—
TBD
TBD
mA
–40°C 4
—
TBD
TBD
µA
25°C 4
—
17
TBD
µA
85°C 4
—
TBD
TBD
µA
105°C 4
—
TBD
TBD
µA
—
TBD
TBD
µA
—
TBD
TBD
µA
Stop
IDDApseudo_stop
125°C 4
S9
–40°C 4
Stop
25°C 4
—
17
TBD
µA
85°C 4
—
TBD
TBD
µA
105°C 4
—
TBD
TBD
µA
125°C 4
—
TBD
TBD
µA
(low power)
1
2
3
4
5
IDDAstop
S10
Reference Supply Current
IREF
—
200
250
µA
S11
Input Injection Current 5
IINJ
—
—
2
mA
S12
Input Current, Off Channel 6
IOFF
–200
—
200
nA
S13
S14
Total Input
Capacitance
CINN
CINS
—
—
—
—
10
15
pF
pF
S15
Disruptive Analog Input Current 7
INA
–3
—
3
mA
A/A
Not Sampling
Sampling
Ratio 8
S16
Coupling
—
—
10–4
S17
Incremental Error due to injection current
(All channels with 10k < Rs < 100k)9
—
—
±1
Counts
S18
Incremental Error due to injection current
(Channel under test Rs=10k, IINJ=±3mA) 9
—
—
±1
Counts
S19
Incremental Capacitance during
Sampling 10
—
—
5
pF
K
CSAMP
All voltages referred to VSSA, –40 to 125oC, VDDA = 5.0 V ±10% and 2.0 MHz conversion rate unless otherwise
noted. Refer to Table 6 for additional operating conditions.
To obtain full-scale, full-range results, VSSA < VRL < VINDC < VRH < VDDA. Sample buffer amp cannot drive beyond
the power supply levels. If the input level goes outside of this range, it will effectively be clipped.
Full accuracy is not guaranteed when the differential reference voltage is less than 4.5 V.
85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
The input injection current is specified to 1 count of error.
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6
7
8
9
Freescale Semiconductor, Inc...
10
Freescale Semiconductor, Inc.
Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 to 12 °C, in the ambient temperature range of 50 to 125 °C.
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater than VRH and 0x000 for values less than VRL. This assumes that VDDA ≥ AVRH and VRL ≥ VSSA due to the
presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
Coupling Ratio, K, is defined as the ratio of the output current, IOUT, measured on the pin under test to the injection
current, IINJ, when both adjacent pins are overstressed with the specified injection current. K = IOUT ÷ IINJ. The input
voltage error on the channel under test is calculated as Verr = IINJ x K x RS.
Total injection current is determined by the number of channels injecting (for example, 15), external injection voltage
(VINJ – VPOSCLAMP, or VINJ – VNEGCLAMP), and the external source impedance, Rs, wherein all input channels have
the same values. To determine the error voltage on the converted channel, only the two adjacent channels are
expected to contribute to the error voltage: Verrj = (VINJ – VCLAMP) × K × 2.
For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 × CSAMP. The
value of CSAMP in the new design may be reduced, or increased slightly.
Table 30. ATD Performance Specifications 1
Num C
Rating
Symbol
Min
Typ
Max
Unit
T1
D 10-bit Resolution
LSB
—
5
—
mV
T2
D 10-bit Differential Nonlinearity 2
DNL
–1
—
1
Counts
T3
D 10-bit Integral Nonlinearity 2
INL
–2
—
2
Counts
T4
D 10-bit Absolute Error 2, 3
AE
–2.5
—
2.5
Counts
T5
D Max input Source Impedance 4
RS
—
—
100
kΩ
1
All voltages referred to VSSA, VDDA = 5.0 V±10%, ATD clock = 2.1 Mhz., –40 to 125 °C.
Note: 1 LSB = 1 Count (At VREF = 5.12 V, one 8 bit count = 20 mV, one 10-bit count = 5 mV)
3 These values include quantization error which is inherently 1/2 count for any A/D converter.
4 This value is based on error attributed to the specified leakage value of TBD nA resulting in an error of less than 1/2
LSB (2.5 mV). If operating conditions are less than worst case or leakage-induced error is acceptable, larger values
of source resistance is allowable.
2
3.10.4 ATD Timing Specifications
Table 31. ATD Timing Specifications
Num C
Rating
Symbol
U1
D ATD Module Clock Frequency
U2
D ATD Conversion Clock Frequency
U3
D ATD 10-bit Conversion Period*
U4
D Stop Recovery Time (VDDA = 5.0 V)
Clock Cycles
Conv. Time
Min
Typ
Max
Unit
Fclk
—
—
25.0
MHz
Fatdclk
0.5
—
2.0
MHz
NCONV10*
TCONV10
14*
7
—
—
28*
14
Cycles*
µsec
TSR
—
—
100
µsec
Table 32. ATD External Trigger Timing Specifications
Num
V1
1
28
C
Parameter
D ETRIG Minimum Period
Symbol
Min
Max
Unit
TPERIOD
—
1 sample +
1 conv. +
1 ATD clock
CYCLE
V2
D ETRIG Minimum Pulse Width
tPW
2
—
SYS CLK
V3
D ETRIG Level Recovery 1
tLR
1
—
SYS CLK
V4
D Conversion Start Delay
tDLY
—
2
SYS CLK
Time prior to end of conversion that the ETRIG pin must be deactivated so that another conversion sequence does
not start.
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tPW
tPERIOD
Edge Sensitive
Falling Edge Active
ETRIG
tDLY
Coversion Activity
tDLY
ADx
Max Frequency
Freescale Semiconductor, Inc...
Level Sensitive
tPW
Low Active
ETRIG
Sequence
Complete Flag
ASCIF
Coversion Activity
ADx
tDLY
Max Frequency
Level Sensitive
Low Active
tDLY
ETRIG
tLR
Sequence
Complete Flag
ASCIF
Coversion Activity
ADx
tDLY
Figure 10. ATD External Trigger Timing Diagram
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3.11 Serial Peripheral Interface Electrical
Specifications
3.11.1 Master Mode
Figure 11 and Figure 12 illustrate master mode timing. Timing values are shown in Table 33.
Table 33. SPI Master Mode Timing Characteristics 1
Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Freescale Semiconductor, Inc...
W1a P Operating Frequency
Symbol
Min
Typ
Max
Unit
fop
DC
—
1/4
fbus
W1b P SCK Period tsck = 1/fop
tsck
4
—
2048
tbus
W2
D Enable Lead Time
tlead
1/2
—
—
tsck
W3
D Enable Lag Time
W4
D Clock (SCK) High or Low Time
W5
W6
W9
D Data Valid (after Enable Edge)
tlag
1/2
—
—
tsck
twsck
tbus − 30
—
1024 tbus
ns
D Data Setup Time (Inputs)
tsu
25
—
—
ns
D Data Hold Time (Inputs)
thi
0
—
—
ns
tv
—
—
25
ns
tho
0
—
—
ns
W11 D Rise Time Inputs and Outputs
tr
—
—
25
ns
W12 D Fall Time Inputs and Outputs
tf
—
—
25
ns
W10 D Data Hold Time (Outputs)
1
The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent
between the Master and the Slave timing shown in Table 34.
3.11.2 Slave Mode
Figure 13 and Figure 14 illustrate the slave mode timing. Timing values are shown in Table 34.
Table 34. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
X1a P Operating Frequency
fop
DC
—
1/4
fbus
X1b P SCK Period tsck = 1/fop
tsck
4
—
2048
tbus
X2
D Enable Lead Time
tlead
1
—
—
tcyc
X3
D Enable Lag Time
tlag
1
—
—
tcyc
X4
D Clock (SCK) High or Low Time
twsck
tcyc − 30
—
—
ns
X5
D Data Setup Time (Inputs)
tsu
25
—
—
ns
X6
D Data Hold Time (Inputs)
thi
25
—
—
ns
X7
D Slave Access Time
ta
—
—
1
tcyc
X8
D Slave SIN Disable Time
tdis
—
—
1
tcyc
X9
D Data Valid (after SCK Edge)
tv
—
—
25
ns
tho
0
—
—
ns
X11 D Rise Time Inputs and Outputs
tr
—
—
25
ns
X12 D Fall Time Inputs and Outputs
tf
—
—
25
ns
X10 D Data Hold Time (Outputs)
30
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PCSx
(OUTPUT)
W11
W2
W1b
SCK
(CPOL = 0)
(OUTPUT)
W3
W4
W4
SCK
(CPOL = 1)
(OUTPUT)
W12
W5
W6
Freescale Semiconductor, Inc...
SIN
(INPUT)
MSB In 2
Bit 6 ... 1
LSB In
W9
W9
SOUT
(OUTPUT)
MSB Out 2
1
2
W10
Bit 6 ... 1
LSB Out
If configured as output.
LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 11. SPI Master Timing (CPHA = 0)
PCSx
(OUTPUT)
W2
W11
W1b
SCK
(CPOL = 0)
(OUTPUT)
W3
W12
W4
W11
W12
W4
SCK
(CPOL = 1)
(OUTPUT)
W5
W6
SIN
(INPUT)
MSB In 2
Bit 6 ... 1
LSB In
W9
W10
SOUT
(OUTPUT)
Port Data
1
2
Master MSB Out 2
Bit 6 ... 1
Master LSB Out
Port Data
If configured as output.
LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI Master Timing (CPHA =1)
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Electrical Characteristics
Freescale Semiconductor, Inc.
SS
(INPUT)
X11
X2
X12
X1b
SCK
(CPOL = 0)
(INPUT)
X11
X4
X12
X4
SCK
(CPOL = 1)
(INPUT)
X7
X10
X9
SOUT
(OUTPUT)
Freescale Semiconductor, Inc...
X3
Slave MSB Out
X8
X10
Bit 6 ... 1
Slave LSB Out
X5
X6
SIN
(INPUT)
Bit 6 ... 1
MSB In
LSB In
Figure 13. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
X11
X2
X12
X1b
SCK
(CPOL = 0)
(INPUT)
X11
X4
X12
X4
SCK
(CPOL = 1)
(INPUT)
X3
X9
X8
X7
SOUT
(OUTPUT)
X10
Slave MSB Out
Bit 6 ... 1
Slave LSB Out
X5
X6
SIN
(INPUT)
MSB In
Bit 6 ... 1
LSB In
Figure 14. SPI Slave Timing (CPHA =1)
32
MAC7100 Microcontroller Family Hardware Specifications
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Electrical Characteristics
Freescale Semiconductor, Inc.
3.12 FlexCAN Electrical Specifications
Table 35. FlexCAN Wake-up Pulse Characteristics
Conditions are shown in Table 6 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Y1
P FlexCAN Wake-up dominant pulse filtered
tWUP
—
—
2
µs
Y2
P FlexCAN Wake-up dominant pulse passed
tWUP
5
—
—
µs
Freescale Semiconductor, Inc...
3.13 Program Flash and Data Flash Timing
Characteristics
NOTE
Unless otherwise noted the abbreviation NVM (Non-Volatile Memory) is
used for both program Flash and data Flash.
3.13.1 NVM timing
The time base for all NVM program or erase operations is derived from the system clock divided by two
(Fsys/2). A minimum system frequency fNVMfsys is required for performing program or erase operations.
The NVM modules do not have any means to monitor the frequency and will not prevent program or erase
operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM
modules at a lower frequency a full program or erase transition is not assured.
The Flash and Data Flash program and erase operations are timed using a clock derived from the system
frequency using the CFMCLKD register. The frequency of this clock must be set within the limits specified
as fNVMOP. The minimum program and erase times shown in Table 36 are calculated for maximum fNVMOP
and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2 MHz.
3.13.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on the
frequency fNVMOP and can be calculated according to the following formula.
1
1
t swpgm = 9 ⋅ ------------------ + 25 ⋅ --------f NVMOP
f bus
3.13.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t bwpgm = 4 ⋅ ------------------ + 9 ⋅ --------f NVMOP
f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.
33
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Electrical Characteristics
Freescale Semiconductor, Inc.
3.13.1.3 Sector Erase
Erasing a 4k byte Flash sector takes:
1
t era ≈ 4000 ⋅ -----------------f NVMOP
The setup time can be ignored for this operation.
3.13.1.4 Mass Erase
Erasing a NVM block takes:
1
t mass ≈ 20000 ⋅ -----------------f NVMOP
Freescale Semiconductor, Inc...
The setup time can be ignored for this operation.
3.13.1.5 Blank Check
The time it takes to perform a blank check on the Flash or Data Flash is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc
Table 36. NVM Timing Characteristics 1
Num C
Rating
Symbol
Typ
Max
Unit
0.5
—
50 2
MHz
1
—
—
MHz
fNVMOP
150
—
200
kHz
tswpgm
46 3
—
74.5 4
µs
—
31 4
Z1
D System Clock/2
Z2
D Bus frequency for Programming or Erase Operations fNVMBUS
Z3
D Operating Frequency
Z4
Z5
Z6
Z7
Z8
Z9
P Single Word Programming Time
D Flash Burst Programming consecutive word
D Flash Burst Programming Time for 32 Words
P Sector Erase Time
P Mass Erase Time
D Blank Check Time Flash per block
Z10 D Blank Check Time Data Flash per block
1
2
3
4
5
6
7
34
fNVMfsys
tbwpgm
tbrpgm
Min
20.4
3
678.4
tera
20 5
tmass
100 5
tcheck
11
6
tcheck
11 6
3
µs
4
µs
—
1035.5
—
26.7
4
ms
—
133 4
ms
7
—
32778
—
2058 7
tcyc
tcyc
Conditions are shown in Table 6 unless otherwise noted
Restrictions for oscillator in crystal mode apply!
Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus.
Maximum erase and programming times are achieved under particular combinations of fNVMOP and bus frequency
fbus. Refer to formulae in Section 3.13.1.1, “Single Word Programming,” through Section 3.13.1.4, “Mass Erase,” for
more information.
Minimum erase times are achieved under maximum NVM operating frequency fNVMOP.
Minimum time, if first word in the array is not blank
Maximum time to complete check on an erased block
MAC7100 Microcontroller Family Hardware Specifications
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MOTOROLA
Electrical Characteristics
Freescale Semiconductor, Inc.
3.13.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase
cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is
incremented every time a sector or mass erase event is executed.
Table 37. NVM Reliability Characteristics
Conditions shown in Table 6 unless otherwise noted.
Num
C
Rating
Z10
C Program/Data Flash Program/Erase endurance (–40C to +125C)
Z11
C Program/Data Flash Data Retention Lifetime
Min
Unit
10,000
Cycles
15
Years
Freescale Semiconductor, Inc...
NOTE
All values shown in Table 37 are target values and subject to
characterization.
For Flash cycling performance, each Program operation must be preceded
by an erase.
35
MAC7100 Microcontroller Family Hardware Specifications
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Device Pin Assignments
4
Freescale Semiconductor, Inc.
Device Pin Assignments
The MAC7100 Family is available in 208-pin ball grid array (MAP BGA), 144-pin low profile quad flat
(LQFP), 112-pin LQFP, and 100-pin LQFP package options. The family of devices offer pin-compatible
packaged devices to assist with system development and accommodate a direct application enhancement
path. Refer to Table 1 for a comparison of the peripheral sets and package options for each device.
Most pins perform two or more functions, which is described in more detail in the MAC7100
Microcontroller Family Reference Manual (MAC7100RM/D). Figure 15, Figure 16, Figure 17, Figure 18,
and Figure 19 show the pin assignments for the various packages.
MAC7141PV Pin Assignments
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A
/ PCS0_A
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
PG4
PG5
PG6
PG7
VSSX
VDDX
N/C
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PF15
PF14
PF13
PF12
PF11
PF10
PF9
PF8
PF7
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
/
/
/
/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MAC7141
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CNTX_A
CNRX_A
CNTX_B
CNRX_B
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
VDDX
VSSX
PD4 / IRQ
PD3 / XIRQ
/ XCLKS
CLKOUT
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
PB9 / PCS0_B / SS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
MODB / PD0
MODA / PD1
Freescale Semiconductor, Inc...
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.1
Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP
36
MAC7100 Microcontroller Family Hardware Specifications
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MOTOROLA
Device Pin Assignments
MAC7121PV Pin Assignments
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A
/ PCS0
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
PG4
PG5
PG8
PG9
PG10
PG11
PG6
PG7
VSSX
VDDX
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PF15
PF14
PF13
PF12
PF11
PF10
PF9
PF8
PF7
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
/
/
/
/
/
/
/
/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MAC7121
112 LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CNTX_A
CNRX_A
CNTX_C
CNRX_C
CNTX_D
CNRX_D
CNTX_B
CNRX_B
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
VDDX
VSSX
PD4 / IRQ
PD3 / XIRQ
CLKOUT
/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
PA14
PA13
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
Freescale Semiconductor, Inc...
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.2
Freescale Semiconductor, Inc.
Figure 16. Pin Assignments for MAC7121 in 112-pin LQFP
37
MAC7100 Microcontroller Family Hardware Specifications
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MOTOROLA
Device Pin Assignments
MAC7101PV Pin Assignments
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A / PCS0_A
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MAC7101
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PH10 / AN10_B
PE9 / AN9_A
PH9 / AN9_B
PE8 / AN8_A
PH8 / AN8_B
PE7 / AN7_A
PH7 / AN7_B
PE6 / AN6_A / RDY'
PH6 / AN6_B
PE5 / AN5_A / MSEO'
PH5 / AN5_B
PE4 / AN4_A / MDO1'
PH4 / AN4_B
PE3 / AN3_A / MDO0'
PH3 / AN3_B
PE2 / AN2_A / EVTI'
PH2 / AN2_B
PE1 / AN1_A / EVTO'
PH1 / AN1_B
PE0 / AN0_A / MCKO'
PH0 / AN0_B
VDDX
VSSX
PD15
PD14
PD13
PD4 / IRQ
PD3 / XIRQ
CLKOUT
/ XCLKS
VSSX
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
/ PF6
/ PF5
/ PF4
/ PF3
/ PF2
/ PF1
/ PF0
PC8
PC9
PC10
PC11
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VSSX
VDDX
PA15
PA14
PA13
PD11
PD12
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/ PG4
/ PG5
/ PG8
/ PG9
/ PG10
/ PG11
/ PG6
/ PG7
/ PC0
/ PC1
/ PC2
/ PC3
VSSX
VDDX
/ PB0
/ PB1
/ PB2
/ PB3
/ PB4
/ PB5
/ PB6
/ PB7
/ PB8
/ PF15
/ PF14
/ PF13
/ PF12
/ PC4
/ PC5
/ PC6
/ PC7
/ PF11
/ PF10
/ PF9
/ PF8
/ PF7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
CNTX_A
CNRX_A
CNTX_C
CNRX_C
CNTX_D
CNRX_D
CNTX_B
CNRX_B
eMIOS6
eMIOS5
eMIOS4
eMIOS3
eMIOS2
NEXPR / eMIOS1
NEXPS / eMIOS0
Freescale Semiconductor, Inc...
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
MCKO
PA0 /
EVTO
PA1 /
EVTI
PA2 /
MDO0
PA3 /
MDO1
PA4 /
MSEO
PA5 /
RDY
PA6 /
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
VSSX
VDDX
PE15 / AN15_A
PH15 / AN15_B
PE14 / AN14_A
PH14 / AN14_B
PE13 / AN13_A
PH13 / AN13_B
PE12 / AN12_A
PH12 / AN12_B
PE11 / AN11_A
PH11 / AN11_B
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.3
Freescale Semiconductor, Inc.
Figure 17. Pin Assignments for MAC7101 in 144-pin LQFP
38
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MOTOROLA
Device Pin Assignments
MAC7111PV Pin Assignments
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MAC7111
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
CNTX_A / PG4
CNRX_A / PG5
CNTX_C / PG8
CNRX_C / PG9
CNTX_D / PG10
CNRX_D / PG11
CNTX_B / PG6
CNRX_B / PG7
ADDR0 / PC0
ADDR1 / PC1
ADDR2 / PC2
ADDR3 / PC3
VSSX
VDDX
SDA
/ PB0
SCL
/ PB1
SIN_A / PB2
SOUT_A / PB3
SCK_A / PB4
SS_A
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
ADDR4 / PC4
ADDR5 / PC5
ADDR6 / PC6
ADDR7 / PC7
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7 / DATA7
PA8 / DATA8
PA9 / DATA9
PA10 / DATA10
PA11 / DATA11
PA12 / DATA12
PD5 / ADDR16
PC15 / ADDR15
PC14 / ADDR14
PC13 / ADDR13
PC12 / ADDR12
VDDX
VSSX
PD15 / R/W
PD14 / CS0
PD13 / CS1
PD4 / IRQ
PD3 / XIRQ
CLKOUT
/ XCLKS
TA
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
ADDR8 / PC8
ADDR9 / PC9
ADDR10 / PC10
ADDR11 / PC11
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VSSX
VDDX
DATA15 / PA15
DATA14 / PA14
DATA13 / PA13
OE
/ PD11
/ PD12
CS2
/ PD0
MODB BS0
/ PD1
MODA BS1
SS_B / PCS0_B / PB9
Freescale Semiconductor, Inc...
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0 / DATA0 / MCKO
PA1 / DATA1 / EVTO
PA2 / DATA2 / EVTI
PA3 / DATA3 / MDO0
PA4 / DATA4 / MDO1
PA5 / DATA5 / MSEO
PA6 / DATA6 / RDY
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
VSSX
VDDX
PD10 / ADDR21
PD9 / ADDR20
PD8 / ADDR19
PD7 / ADDR18
PD6 / ADDR17
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.4
Freescale Semiconductor, Inc.
Figure 18. Pin Assignments for MAC7111 in 144-pin LQFP
39
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Device Pin Assignments
Freescale Semiconductor, Inc...
4.5
Freescale Semiconductor, Inc.
MAC7131VF Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSSX
VSSX
PG0
PG14
PA2
PA5
TCLK
TDI
PE15
PE14
PH14
PE12
PH11
VRL
VRH
VDDA
B
VSSX
VSSX
PG2
PG15
PA0
PA4
TMS
TDO
PD9
PH15
PE13
PH12
PE10
PH9
VDDA
PH8
C
PG5
PG3
VSSX
PG1
PA1
PA3
PA6
VSS2.5 VDDX
PD6
PH13
PE11
VDDA
PE8
PE7
PH7
D
PG9
PG8
PG4
VSSX
VSSX VSS2.5 VSS2.5 PD10
PD7
VSSA
VSSA
PH10
PE9
PE6
PH6
E
PG6
PG11
PG10
VSSX
PE4
PE5
PH5
PH4
F
PC0
PG7
PC1
VSSX
PE2
PE3
PH3
PH2
G
PB0
PC2
PC3
VSSX
VSSX
VSSX
VSSX
VSSX
PH0
PH1
PE1
PE0
H
PB3
PB2
PB1
VDDX
VSSX
VSSX
VSSX
VSSX
PA8
PA9
PA7
PA10
J
PB5
PB6
PB4
VSSX
VSSX
VSSX
VSSX
VSSX
PD5
PA12
PA11
PC15
K
PB7
PB8
PF15
VSSX
VSSX
VSSX
VSSX
VSSX
PC13
PC12
PC14
VDDX
L
PF14
PF13
PC4
VSSX
PD13
PD14
PD15
PD4
M
PF12
PC5
PC6
VSSX
VSSX
TA
N
PF11
PF10
PC7
VSSX
VSSR
VSSR VSS2.5 VSS2.5 VSSPLL VSSPLL VSSX
VSSX
VSSX
PB11
PB14
PB15
P
PF9
PF8
VSSX
PF5
PC8
PC10
VDDX VSS2.5 VDDR
VDDX
PA15
PD11
PD12
VSSX
PB12
PB13
R
PF7
VSSX
PF6
PF3
PF1
PC9
PG12
PG13
VSSX
VSSX
TEST
PA13
PD1
PB10
VSSX
VSSX
T
VSSX
VSSX
PF4
PF2
PF0
PC11 RESET VSSPLL
XFC
EXTAL XTAL
PA14
PD0
PB9
VSSX
VSSX
PD8
PD3 CLKOUT
Figure 19. Pin Assignments for MAC7131 in 208-pin MAP BGA
40
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Mechanical Information
5
Mechanical Information
5.1
100-Pin LQFP Package
L
60
41
61
D
S
M
DETAIL A
DETAIL A
21
80
1
A
H A-B
M
S
F
20
-D0.20
D
S
0.05 A-B
J
S
0.20
M
C A-B
S
D
M
C
-C-
N
S
E
SEATING
PLANE
P
-A-,-B-,-D-
0.20
V
C A-B
D
M
B
0.20
Freescale Semiconductor, Inc...
L
B
H A-B
-B-
0.05 D
-A-
B
S
S
S
40
D
DETAIL C
-H-
0.20
DATUM
PLANE
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90 °
0.10
H
M
G
U
T
DATUM-HPLANE
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN MAX
13.90 14.10
13.90 14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10 °
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95 17.45
0.13
--0°
--16.95 17.45
0.35
0.45
1.6 REF
Figure 20. 100-Pin LQFP Mechanical Dimensions (Case No. 983)
41
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Mechanical Information
5.2
Freescale Semiconductor, Inc.
112-Pin LQFP Package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
V
B
Freescale Semiconductor, Inc...
L
M
28
B1
57
29
F
D
56
0.13
N
T L-M N
ROTATED 90 °COUNTERCLOCKWISE
S1
A
S
C2
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
(Y)
VIEW AB
M
BASE
METAL
SECTION J1-J1
A1
C
AA
J
V1
(Z)
θ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--- 1.600
0.050 0.150
1.350 1.450
0.270 0.370
0.450 0.750
0.270 0.330
0.650 BSC
0.090 0.170
0.500 REF
0.325 BSC
0.100 0.200
0.100 0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090 0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure 21. 112-Pin LQFP Mechanical Dimensions (Case No. 987)
42
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Mechanical Information
5.3
144-Pin LQFP Package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
1
108
4X
J1
L
J1
M
CL
B
V
Freescale Semiconductor, Inc...
140X
B1
VIEW Y
36
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION.
ALLWABLE
DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
72
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
AA
F
C2
0.05
R2
θ
R1
0.08
M
0.25
BASE
METAL
D
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90 ° )
144 PL
X
X=L, M OR N
G
VIEW Y
V1
73
37
P
(K)
C1
(Y)
VIEW AB
E
MILLIMETERS
DIM MIN MAX
A
20.00 BSC
A1
10.00 BSC
B
20.00 BSC
B1
10.00 BSC
C
1.40
1.60
C1
0.05
0.15
C2
1.35
1.45
D
0.17
0.27
E
0.45
0.75
F
0.17
0.23
G
0.50 BSC
J
0.09
0.20
K
0.50 REF
P
0.25 BSC
R1
0.13
0.20
R2
0.13
0.20
S
22.00 BSC
S1
11.00 BSC
V
22.00 BSC
V1
11.00 BSC
Y
0.25 REF
Z
1.00 REF
AA
0.09
0.16
θ
0°
θ1
0°
7°
θ2
11 °
13 °
θ1
(Z)
Figure 22. 144-Pin LQFP Mechanical Dimensions (Case No. 918)
43
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Mechanical Information
5.4
Freescale Semiconductor, Inc.
208-Pin MAP BGA Package
LASER MARK FOR PIN A1
IDENTIFICATION IN THIS AREA
M
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASEMENT SHALL EXCLUDE ANY
EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
K
E
DIM
A
A1
A2
b
D
E
e
S
M
X
D
X
Freescale Semiconductor, Inc...
0.2 4X
MILLIMETERS
MIN
MAX
--2.00
0.40
0.60
1.00
1.30
0.50
0.70
17.00 BSC
17.00 BSC
1.00 BSC
0.50 BSC
15X e
METALIZED MARK FOR PIN A1
IDENTIFICATION IN THIS AREA
S
3
208X
b
0.3
M
X Y Z
0.1
M
Z
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
15X e
S
5
0.2 Z
A
A2
A1
Z
0.2 Z 208X
4
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VIEW M M
VIEW K
(ROTATED 90˚ CLOCKWISE)
Figure 23. 208-Pin MAP BGA Mechanical Dimensions (Case No. 1159A-01)
44
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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MOTOROLA
Mechanical Information
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
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MAC7100 Microcontroller Family Hardware Specifications
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MOTOROLA
Freescale Semiconductor, Inc.
HOW TO REACH US:
USA / EUROPE / Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo, 106-8573 Japan
81-3-3440-3569
Freescale Semiconductor, Inc...
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE:
http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to
use Motorola products. There are no express or implied copyright licenses granted hereunder to
design or fabricate any integrated circuits or integrated circuits based on the information in this
document.
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application
or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,
and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
All other product or service names are the property of their respective owners. Motorola, Inc. is
an Equal Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
MAC7100EC/D, Rev. 0.1,
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
HOW TO REACH US:
USA / EUROPE / Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo, 106-8573 Japan
81-3-3440-3569
Freescale Semiconductor, Inc...
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE:
http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to
use Motorola products. There are no express or implied copyright licenses granted hereunder to
design or fabricate any integrated circuits or integrated circuits based on the information in this
document.
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application
or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,
and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
All other product or service names are the property of their respective owners. Motorola, Inc. is
an Equal Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
MAC7100EC/D, Rev. 0.1,
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Mechanical Information
48
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA