CS5651 CS5651 High Performance Dual Channel Current Mode Controller with ENABLE Description The CS5651 is a high performance, fixed frequency, dual current mode controller specifically designed for Off-Line and DC to DC converter applications. It offers the designer a cost effective solution with minimal external components. This integrated circuit features a unique oscillator for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, and two high Features current totem pole outputs ideally suited for driving power MOSFETs. One of the outputs, VOUT2 is switchable via the ENABLE2 pin. Also included are protective features consisting of input and reference undervoltage lockouts, each with hysteresis; cycle-by-cycle current limiting; and a latch for single pulse metering of each output. The CS5651 is pin compatible with the MC34065H. Block Diagram VCC 5.0V Ref VREF VCC Undervoltage Lockout ■ Oscillator has Precise Duty Cycle Limit and Frequency Control ■ 500kHz Current Mode Operation ■ Automatic Feed Forward Compensation ■ Separate Latching PWMs for Cycle-By-Cycle Current Limiting ■ Internally Trimmed Reference with Undervoltage Lockout ■ Switchable Second Output ■ Two High Current Totem Pole Outputs ■ Input Undervoltage Lockout with Hysteresis VREF Undervoltage Lockout VOUT1 SYNC Latching PWM 1 CT Oscillator RT Sense1 + VFB1 - Error Amp 1 16L PDIP & SO Wide VOUT2 COMP1 Latching PWM 2 ENABLE2 VFB2 Package Options + - Sense2 Error Amp 2 COMP2 Gnd Pwr Gnd SYNC 1 16 VCC CT 2 15 VREF RT 3 14 ENABLE2 VFB1 4 13 VFB2 COMP1 5 12 COMP2 SENSE1 6 11 Sense2 VOUT1 7 10 VOUT2 Gnd 8 9 Pwr Gnd Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 3/9/99 1 A ® Company CS5651 Absolute Maximum Ratings Output Current, Source or Sink (Note 1) ......................................................................................................................400mA Output Energy (capacitive load per cycle) .......................................................................................................................5.0µJ Current Sense, Enable and Voltage ......................................................................................................................-0.3 to +5.5V Feedback Inputs Sync Input High State (Voltage).............................................................................................................................................5.5V Low State (Reverse Current)..........................................................................................................................-5.0mA Error Amp Output Sink Current......................................................................................................................................10mA Storage Temperature Range ................................................................................................................................-65 to +150°C Operating Junction Temperature...................................................................................................................................+150°C Lead Temperature Soldering Wave Solder (through hole styles only)..........................................................................10 sec. max, 260°C peak Reflow (SMD styles only)...........................................................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: VCC = 15V, RT = 8.2kΩ, CT = 3.3nF, 0°C ≤ TA ≤ 70°C [Note 2], unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.9 5.0 5.1 V ■ Reference Section Reference Output Voltage, VREF IOUT = 1.0mA, TJ = 25°C Line Regulation 11V ≤ VCC ≤ 15V 2.0 20.0 mV Load Regulation 1.0mA ≤ IOUT ≤ 10mA 3.0 25.0 mV 5.15 V Total Output Variation over Line, Load and Temperature 4.85 Output Short Circuit Current 30 100 46.5 49.0 51.5 kHz 0.2 1.0 % mA ■ Oscillator and PWM Sections Total Frequency Variation 11V ≤ VCC ≤ 15V, Tlow ≤ TA≤ Thigh over Line and Temperature Frequency Change with Voltage 11V ≤ VCC ≤ 15V Duty Cycle at each Output Maximum SYNC Current High State VIN = 2.4V Low State VIN = 0.8V 46.0 49.5 52.0 % 170 80 250 160 µA 2.50 2.58 V -0.1 -1.0 µA ■ Error Amplifiers Voltage Feedback Input VOUT = 2.5V Input Bias Current VFB = 5.0V Open-Loop Voltage Gain 2.0V ≤ VOUT ≤ 4.0V Unity Gain Bandwidth 2.42 65 100 dB TJ = 25°C (Note 5) 0.7 1.0 MHz Power Supply Rejection Ratio VCC = 11V to 15V 60 90 dB Output Current Source VOUT = 3.0V, VFB = 2.3V Sink VOUT = 1.2V, VFB = 2.7V -0.45 2.00 -1.00 12.00 mA mA Output Voltage Swing High State RL = 15kΩ to ground, VFB = 2.3V Low State RL = 15kΩ to VREF, VFB = 2.7V 5.0 6.2 V 2 0.8 1.1 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ■ Current Sense Section Current Sense Input Voltage Gain (Notes 3 and 4) 2.75 3.00 3.25 V/V Maximum Current Sense Input Threshold (Note 3) 0.9 1.0 1.1 V -2.0 -30.0 µA 150 300 ns VREF 1.5 V V V Input Bias Current Propagation Delay Current Sense Input to Output (Note 5) ■ Output 2 Enable Pin Enable Pin Voltage High State Low State ENABLE2 enabled ENABLE2 disabled 3.5 0.0 Low State Input Current VIL = 0V 100 250 400 µA 0.4 2.5 13.0 12.0 0.1 1.6 13.5 13.4 V V V V VCC = 6.0V, ISINK = 1.0mA 0.1 1.1 V Output Voltage Rise Time CL = 1.0nF (Note 5) 28 150 ns Output Voltage Fall Time CL = 1.0nF (Note 5) 25 150 ns 14 10.0 4.0 15 11.0 V V V 0.6 20 1.0 25 mA mA ■ Drive Outputs Output Voltage Low State High State Output Voltage with UVLO Activated ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA ■ Undervoltage Lockout Section Start-Up Threshold Minimum Operating Voltage Hysteresis 13 9.0 ■ Total Device Start-Up Current Operating Current VCC = 12V (Note 2) Note 4: Comparator gain is defined as: Note 1: Maximum package power dissipation limits must be observed. AV= Note 2: Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. ∆V Compensation ∆V Current Sense Note 5: These parameters are guaranteed by design but not 100% tested in production. Note 3: This parameter is measured at latch trip point with VFB = 0V. 3 CS5651 Electrical Characteristics: VCC = 15V, RT = 8.2kΩ, CT = 3.3nF, 0°C ≤ TA ≤ 70°C [Note 2], unless otherwise specified. PACKAGE PIN # PIN SYMBOL FUNCTION 16 L PDIP & SO Wide 1 SYNC A positive going pulse applied to this input will synchronize the oscillator. A DC voltage within the range of 2.4V to 5.5V will inhibit the oscillator. 2 CT Timing capacitor CT connects pin to ground setting oscillator frequency. 3 RT Resistor RT connects to ground setting the charge current for CT. Its value must be between 4.0kΩ and 16kΩ. 4 VFB1 The inverting input of error amplifier 1. Normally it is connected to the switching power supply output. 5 COMP1 The output of error amplifier 1, for loop compensation. 6 Sense1 Output 1 pulse by pulse current limit. 7 VOUT1 Drives the power switch at output 1. 8 Gnd 9 Pwr Gnd 10 VOUT2 Drives the power switch at output 2. 11 Sense2 Output 2 pulse by pulse current limit. 12 COMP2 Output of error amplifier 2, for loop compensation. 13 VFB2 14 ENABLE2 15 VREF 5.0V reference output. It can source current in excess of 30mA. 16 VCC The positive supply of the IC. The minimum operating voltage range after start-up is 9V. Logic ground Power ground. Power device return is connected to this pin. Inverting input of error amplifier 2. Normally it is connected to the switching power supply output. Output 2 disable. A logic low at this pin disables VOUT2. Typical Performance Characteristics Timing Resistor vs. Oscillator Frequency Max. Output Duty Cycle vs. Oscillator Frequency F 100p pF 220 pF F pF 500 330 2.2n nF nF 5.0 F 10n 10 3.3 12 F 1.0n 14 MAXIMUM DUTY CYCLE (%) 50 C T= RT TIMING RESISTOR (KΩ) 16 8.0 VCC= 6.0 15V TA=25°C 4.0 10k 30k 50k 100k 300k 500k 48 46 44 42 VCC = 15V RT = 4.0kΩ to 16kΩ CL = 15pF TA = 25°C 40 38 10k 1.0M f OSC OSCILLATOR FREQUENCY (Hz) 40 30 60 PHASE 90 20 120 0 150 -20 10k 100k 1.0k 10k 100k 1.0M Vth, CURRENT SENSE INPUT THRESHHOLD (V) 60 100k 300k 500k 1.0M 1.2 Phase Margin (DEGREES) VCC = 15V VO = 1.5V TO 2.5V RL = 100kΩ TA = 25°C GAIN 50k Current Sense Input Threshold vs. Error Amp Output Voltage 0 100 80 30k f OSC OSCILLATOR FREQUENCY (Hz) Error Amp Open-Loop Gain & Phase vs. Frequency AVOL, OPEN-LOOP VOLTAGE GAIN (dB) CS5651 Package Pin Description 180 10M VCC = 15V 1.0 0.8 TA = 125°C TA = 25°C 0.6 TA = -55°C 0.4 0.2 0 0 f, FREQUENCY (Hz) 1.0 2.0 3.0 4.0 5.0 6.0 ERROR AMP OUTPUT VOLTAGE (V) 4 7.0 Reference Voltage Change vs. Source Current Reference Short Circuit Current vs. Temperature ∆ VREF, REFERENCE Voltage (mV) VCC = 15V -4.0 -8.0 TA = –55°C -12 TA = 25°C -16 TA = 125°C -20 120 ISC, REFERENCE SHORT CIRCUIT CURRENT (mA) 0 100 80 60 -55 -24 0 20 40 60 80 100 I ref, REFERENCE SOURCE CURRENT (mA) 120 SOURCE SATURATION (LOAD TO GROUND) -1.0 TA= –55°C TA= –55°C TA=25°C 1.0 GND 0 0 SINK SATURATION (LOAD TO VCC) 200 400 600 OUTPUT LOAD CURRENT (mA) 50 75 100 125 32 VCC=15V 80µS PULSED LOAD 120Hz RATE TA=25°C -2.0 2.0 25 Supply Current vs. Supply Voltage ICC, SUPPLY CURRENT (mA) Vsat, OUTPUT SATURATION VOLTAGE (V) VCC 0 TA, AMBIENT TEMPERATURE (°C) Output Saturation Voltage vs. Load Current 0 -25 RT=8.2kΩ CT=3.3nF VFB 1, 2=0V 24 CURRENT SENSE 1, 2=0V TA=25°C 16 8.0 0 0 800 4.0 8.0 12 16 20 VCC, SUPPLY VOLTAGE (V) - CS-5651 Operating Description making this controller suitable for high frequency power conversion applications. The CS5651 is a high performance, fixed frequency, dual channel current mode PWM controller for Off-Line and DC to DC converter applications. Each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. The oscillator, reference, and undervoltage lockout circuits are common to both channels. In noise sensitive applications it may be necessary to synchronize the converter with an external system clock. This can be accomplished by applying an external clock signal. For reliable synchronization, the oscillator frequency should be set about 10% slower than the clock frequency. The rising edge of the clock signal applied to SYNC, terminates the charging of CT and VOUT2 conduction. By tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. Oscillator The oscillator has both precise frequency and duty cycle control. The oscillator frequency is programmed by the timing components RT and CT. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink, that generates a symmetrical 50 percent duty cycle waveform at CT. The oscillator peak and valley thresholds are 3.5V and 1.6V respectively. The source/ sink current is controlled by resistor RT. For proper operation over temperature range RT’s value should be between 4.0kΩ to 16kΩ. Error Amplifier Each channel contains a fully-compensated error amplifier with access to the output and inverting input. The amplifier features a typical dc voltage gain of 100 dB, and a unity gain bandwidth of 1.0 MHz with 71 degrees of phase margin. The non-inverting input is internally biased at 2.5V. The converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. The maximum input bias current is -1.0 µA which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider resistance. As CT charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non-overlapping output duty cycles. Output 2 is enabled while CT is charging, and Output 1 is enabled during the discharge. Even at 500kHz, each output is capable of approximately 44% duty cycle, Its output voltage is offset by two diode drops (≈1.4V) and divided by three before it connects to the inverting input of the current sense comparator. This guarantees that both 5 CS5651 Typical Performance Characteristics: continued CS5651 Operating Description: continued comparator has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 14V and 10V for the CS5651. The VREF comparator disables the outputs until the internal circuitry is functional. This comparator has upper and lower thresholds of 3.6V and 3.4V. The guaranteed minimum operating voltage after turn-on is 11V for CS5651. outputs are disabled when the error amplifier output is at its lowest state (VOUT(LOW)). This occurs when the power supply is operating at light or no-load conditions, or at the beginning of a soft-start interval. The minimum allowable error amplifier feedback resistance is limited by the amplifier’s source current capability (0.5 mA) and the output voltage (VOUT(High)) required to reach the current sense comparator 1.0V clamp level with the error amplifier inverting input at ground. This condition happens during initial system start up or when the sensed output is shorted: Outputs and Power Ground Each channel contains a single totem-pole output stage specifically designed for driving a power MOSFET. The outputs have up to ±1.0A peak current capability and have a typical rise and fall time of 28ns with a 1.0nF load. Internal circuitry has been added to keep the outputs in active pull-down mode whenever undervoltage lockout is active. An external pull-down resistor is not needed. RF(min) ≈ (3 x 1.0V) + 1.4V = 8.8kΩ 0.5mA Current Sense Comparator and PWM Latch Cross-conduction current in the totem-pole output stage has been minimized for high speed operation. The average added power due to cross-conduction with VCC = 15V is only 60mW at 500kHz. The CS5651 operates as a current mode controller. Output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output. The error signal controls the peak inductor current on a cycleby-cycle basis. The current sense comparator-PWM Latch combination ensures that only a single pulse appears at the output during any given oscillator cycle. The current is converted to a voltage by connecting sense resistor RSense in series with the source of output switch Q1 and ground. This voltage is monitored via the Sense1,2 pins and compared to a voltage derived from the error amp output. The peak current under normal operating conditions is controlled by the voltage at COMP where: Ipk = Although the outputs were optimized for MOSFET’s, they can easily supply the negative base current required by bipolar NPN transistors for enhanced turn-off. Because the outputs do not contain internal current limiting circuitry, an external series resistor may be required to prevent the peak output current from exceeding the ±1.0A maximum rating. The sink saturation voltage (VOL) is less than 0.4V at 100mA. A separate Power Ground pin is provided and will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly important when the Ipk(max) clamp level is reduced. VCOMP – 1.4V 3RSense This input is used to switch VOUT2. VOUT1 can be used to control circuitry that runs continuously; e.g. volatile memENABLE2 Abnormal operating conditions occur when the power supply output is overloaded or if output voltage is too high. Under these conditions, the current sense comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch current is: Ipk(max) = ory, the system clock, or a remote controlled receiver. The VOUT2 output can control the high power circuitry that can be turned off when not needed. 1.0V RSense Voltage Reference Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. The 5.0V bandgap reference is trimmed to ±2.0% tolerance. The reference has short circuit protection and is capable of sourcing 30mA for powering any additional external circuitry. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. The addition of an RC filter on the current sense input reduces this spike to an acceptable level. Design Considerations High frequency circuit layout techniques are imperative to prevent pulse-width jitter. This is usually caused by excessive noise pick-up imposed on the current sense or voltage feed-back inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit board layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input fil- Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stages are enabled. VCC and the reference output VREF are monitored by separate comparators. Each 6 ter capacitor. Ceramic bypass capacitors (0.1µF) connected directly to VCC and VREF may be required to improve noise filtering. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs. The error amp compensation circuitry and the converter output voltage-divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Timing Diagram SYNC Capacitor CT Latch 1 “Set” Input COMP1 Sense1 Latch 1 “Reset” Input VOUT1 ENABLE2 0V Latch 2 “Set” Input COMP2 Sense2 Latch 2 “Reset” Input VOUT2 Typical Application Diagram VIN Dual Boost Regulator VCC 5.0V CF2 VREF 2.5V R Reference Regulator Internal Bias R + - + 3.4V - VREF UVLO CF1 + + VCC + UVLO - 14V L1 D1 20kΩ Sync VOUT1 RT + Current Sense 2R Comparator 1 + 1.0VREF R + 1.0V RFB1 VFB1 RFB2 COMP1 + Error Amp 1 VFB2 + Error Amp 2 L2 VOUT1 D2 RSense1 + Sense1 Q2 + VOUT2 RFB4 PWM Latch 1 S RQ 250µA ENABLE2 RFB3 Q1 Oscillator + CT Current Sense Comparator 2 2R + 1.0mA R 1.0V PWM Latch 2 S RQ R VOUT2 Sense2 COMP2 Gnd VOUT1 COUT1 Pwr Gnd 7 RSense2 VOUT2 COUT2 CS5651 Operating Description: continued CS5651 Package Specification PACKAGE THERMAL DATA PACKAGE DIMENSIONS IN mm (INCHES) Lead Count Metric Max Min 19.69 18.67 10.50 10.10 16 Lead PDIP 16 Lead SO Wide D English Max Min .775 .735 .413 .398 Thermal Data RΘJC RΘJA 16 Lead PDIP 42 80 typ typ 16 Lead SO Wide 23 105 ˚C/W ˚C/W Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) REF: JEDEC MS-001 Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. D Surface Mount Wide Body (DW); 300 mil wide 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 2.49 (.098) 2.24 (.088) 1.27 (.050) 0.40 (.016) 2.65 (.104) 2.35 (.093) 0.32 (.013) 0.23 (.009) D REF: JEDEC MS-013 0.30 (.012) 0.10 (.004) Ordering Information Part Number CS5651GN16 CS5651GDW16 CS5651GDWR16 Rev. 3/9/99 Description 16L PDIP 16L SO Wide 16L SO Wide (Tape & Reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 8 © 1999 Cherry Semiconductor Corporation