Very Low Power/Voltage CMOS SRAM 1M X 8 bit BSI BS62LV8007 FEATURES GENERAL DESCRIPTION • Vcc operation voltage : 2.7V ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 1.5uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options The BS62LV8007 is a high performance , very low power CMOS Static Random Access Memory organized as 1,048,576 words by 8 bits and operates from a range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE1) , an active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The BS62LV8007 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV8007 is available in 48B BGA and 44L TSOP2 packages. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS62LV8007EC BS62LV8007FC BS62LV8007EI BS62LV8007FI O O A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SPEED ( ns ) 55ns : 3.0~3.6V 70ns : 2.7~3.6V POWER DISSIPATION STANDBY Operating ( I CCSB1, Max ) PKG TYPE ( ICC , Max ) Vcc=3V Vcc=3V 70ns 55ns +0 C to +70 C 2.7V ~ 3.6V 55 / 70 5uA 30mA -40 O C to +85O C 2.7V ~ 3.6V 55 / 70 10uA 31mA TSOP2-44 24mA BGA-48-0912 TSOP2-44 25mA BGA-48-0912 FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE1 NC NC DQ0 DQ1 VCC GND DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 Vcc RANGE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BS62LV8007EC BS62LV8007EI A5 A6 A7 OE CE2 A8 NC NC DQ7 DQ6 GND VCC DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14 1 2 3 4 5 6 NC OE A0 A1 A2 CE2 B NC NC A3 A4 CE1 NC C D0 NC A5 A6 NC D4 D VSS D1 A17 A7 D5 VCC E VCC D2 VCC A16 D6 VSS F D3 NC A14 A15 NC D7 G NC NC A12 A13 WE NC H A18 A8 A9 A10 A11 A19 A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 22 2048 Row Memory Array 2048 X 4096 Decoder 4096 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CE2 WE OE Vdd Gnd 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 512 Column Decoder 18 Control Address Input Buffer A11A9 A8 A3 A2 A1 A0A10 A19 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV8007 1 Revision 1.1 Jan. 2004 BSI BS62LV8007 PIN DESCRIPTIONS Name Function A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE1 CE2 OE Not selected (Power Down) X H X X X X L X I/O OPERATION Vcc CURRENT High Z ICCSB, ICCSB1 Output Disabled H L H H High Z ICC Read H L H L DOUT ICC Write L L H X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias T STG Storage Temperature PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA -40 to +85 -60 to +150 O O RANGE Commercial C Industrial C O O 0 C to +70 C O O -40 C to +85 C Vcc 2.7V ~ 3.6V 2.7V ~ 3.6V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS62LV8007 AMBIENT TEMPERATURE 2 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 10 pF VI/O=0V 12 pF 1. This parameter is guaranteed and not 100% tested. Revision 1.1 Jan. 2004 BSI BS62LV8007 DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME PARAMETER VIL Guaranteed Input Low Voltage(3) Vcc=3V -0.5 -- 0.8 V VIH Guaranteed Input High Voltage(3) Vcc=3V 2.0 -- Vcc+0.3 V IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE1 = VIH or CE2 = VIL or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=3V -- -- 0.4 V VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=3V 2.4 -- -- V ICC(4) Operating Power Supply Current CE1= VIL, CE2= VIH, IDQ = 0mA, F = Fmax(2) Vcc=3V --- --- 31 25 mA ICCSB Standby Current-TTL CE1 = VIH or CE2= VIL, IDQ = 0mA Vcc=3V -- -- 1 mA Standby Current-CMOS CE1≧Vcc-0.2V or CE2≦0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=3V -- 1.5 10 uA ICCSB1(5) MIN. TYP. (1) MAX. TEST CONDITIONS 55ns 70ns UNITS 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 30mA(@55ns)/24mA(@70ns) during 0~70oC operation. 5.IccsB1 is 5uA at Vcc=3.0V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL VDR (3) ICCDR tCDR tR PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc for Data Retention CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V Data Retention Current CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.8 2.5 uA 0 -- -- ns -- -- ns Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time TRC (2) 25OC 1. Vcc = 1.5V, TA = + 2. tRC = Read Cycle Time 3. IccDR(Max.) is 1.3uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE1 Vcc tR t CDR CE1 ≥ Vcc - 0.2V VIH LOW VCC DATA RETENTION WAVEFORM (2) VIH ( CE2 Controlled ) Data Retention Mode Vcc VDR ≧ 1.5V Vcc CE2 R0201-BS62LV8007 VIL Vcc tR t CDR CE2 ≦ 0.2V 3 VIL Revision 1.1 Jan. 2004 BSI BS62LV8007 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) WAVEFORM Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load CL = 30pF+1TTL CL = 100pF+1TTL INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 70ns DESCRIPTION CYCLE TIME : 55ns Vcc=3.0~3.6V Vcc=2.7~3.6V MIN. TYP. MAX. MIN. TYP. MAX. UNIT tAVAX tAVQV tRC tAA Read Cycle Time t E1LQV tACS1 Chip Select Access Time (CE1) t E2LQV tGLQV tACS2 tOE Chip Select Access Time (CE2) tELQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tGLQX tEHQZ tOLZ tCHZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns Chip Deselect to Output in High Z -- -- 35 -- -- 30 ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 30 -- -- 25 ns tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns R0201-BS62LV8007 Address Access Time Output Enable to Output Valid 4 70 -- -- 55 -- -- ns -- -- 70 -- -- 55 ns -- -- 70 -- -- 55 ns -- -- 70 -- -- 55 ns -- -- 35 -- -- 30 ns Revision 1.1 Jan. 2004 BSI BS62LV8007 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE2 t ACS2 t ACS1 CE1 t (5) CLZ (5) t CHZ t OH D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t CE2 t t CE1 t t OE ACS2 OLZ ACS1 (5) t t CLZ OHZ (5) (1,5) CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV8007 5 Revision 1.1 Jan. 2004 BSI BS62LV8007 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 70ns DESCRIPTION (Vcc=2.7~3.6V) MIN. TYP. MAX. CYCLE TIME : 55ns (Vcc=3.0~3.6V) MIN. TYP. MAX. UNIT t AVAX t WC Write Cycle Time 70 -- -- 55 -- -- ns t E1LWH t CW Chip Select to End of Write 70 -- -- 55 -- -- ns t AVWL t AS Address Set up Time 0 -- -- 0 -- -- ns t AVWH t AW Address Valid to End of Write 70 -- -- 55 -- -- ns t WLWH t WP Write Pulse Width 35 -- -- 30 -- -- ns t WHAX t WR Write Recovery Time 0 -- -- 0 -- -- ns t WLOZ t WHZ Write to Output in High Z -- -- 30 -- -- 25 ns t DVWH t DW Data to Write Time Overlap 30 -- -- 25 -- -- ns t WHDX t DH Data Hold from Write Time 0 -- -- 0 -- -- ns t GHOZ t OHZ Output Disable to Output in High Z -- -- 30 -- -- 25 ns t WHQX t OW End of Write to Output Active 5 -- -- 5 -- -- ns (CE2,CE1 , WE) SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE CE2 (5) (11) t CW (5) CE1 t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS62LV8007 6 Revision 1.1 Jan. 2004 BSI BS62LV8007 WRITE CYCLE2 (1,6) t WC ADDRESS CE2 (11) t (5) CE1 t WE AW CW t t WP WR (3) (2) t AS (4,10) t OW t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS62LV8007 7 Revision 1.1 Jan. 2004 BSI BS62LV8007 ORDERING INFORMATION BS62LV8007 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 F: BGA-48-0912 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP2-44 R0201-BS62LV8007 8 Revision 1.1 Jan. 2004 BSI BS62LV8007 1.4 Max. 0.25± 0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 3.375 D1 N D E D1 E1 e 48 12.0 9.0 5.25 3.75 0.75 E1 2.625 E ± 0.1 e SOLDER BALL 0.35±0.05 VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS62LV8007 9 Revision 1.1 Jan. 2004