LTC1654 Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package U FEATURES DESCRIPTIO ■ The LTC®1654 is a dual, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC). It is available in a 16-lead narrow SSOP package, making it the smallest dual 14-bit DAC available. It includes output buffer amplifiers and a flexible serial interface. ■ ■ ■ ■ ■ ■ ■ ■ 14-Bit Monotonic Over Temperature Individually Programmable Speed/Power: 3µs Settling Time at 930µA 8.5µs Settling Time at 540µA 3V to 5V Single Supply Operation Maximum Update Rate: 0.9MHz Buffered True Rail-to-Rail Voltage Outputs User Selectable Gain Power-On Reset and Clear Function Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Smallest Dual 14-Bit DAC: 16-Lead Narrow SSOP Package The LTC1654 has REFHI pins for each DAC that can be driven up to VCC. The output will swing from 0V to VCC in a gain of 1 configuration or VCC/2 in a gain of 1/2 configuration. It operates from a single 2.7V to 5.5V supply. The LTC1654 has two programmable speeds: a FAST and SLOW mode with ±1LSB settling times of 3µs or 8.5µs respectively and supply currents of 930µA and 540µA in the two modes. The LTC1654 also has shutdown capability, power-on reset and a clear function to 0V. U APPLICATIO S ■ ■ ■ ■ , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245. Digital Calibration Industrial Process Control Automatic Test Equipment Offset/Gain Adjustment Multiplying DAC W ■ BLOCK DIAGRA CS/LD SCK REFHI B CONTROL LOGIC INPUT LATCH SDI DAC REGISTER + DAC B VOUT B – 32-BIT SHIFT REGISTER X1/X1/2 B REFHI A INPUT LATCH DAC REGISTER + DAC A VOUT A – SDO CLR POWER-ON RESET X1/X1/2 A REFLO B REFLO A 1654 BD 1654fb 1 LTC1654 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) VCC to GND .............................................. – 0.5V to 7.5V TTL Input Voltage, REFHI, REFLO, X1/X1/2 ........................................ – 0.5V to 7.5V VOUT, SDO .................................. – 0.5V to (VCC + 0.5V) Operating Temperature Range LTC1654C ............................................. 0°C to 70°C LTC1654I ........................................ – 40°C to 85°C Maximum Junction Temperature .......................... 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW X1/X1/2 B 1 16 VCC CLR 2 15 VOUT B SCK 3 14 REFHI B SDI 4 13 REFLO B CS/LD 5 12 AGND DGND 6 11 REFLO A SDO 7 10 REFHI A X1/X1/2 A 8 9 LTC1654CGN LTC1654IGN GN PART MARKING VOUT A 1654 1654I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL DAC n DNL PARAMETER CONDITIONS ● Resolution Monotonicity Differential Nonlinearity MIN ● Guaranteed Monotonic (Note 2) ● INL Integral Nonlinearity Integral Nonlinearity (Note 2) ● ZSE Zero Scale Error 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C ● ● VOS Offset Error 0°C ≤ TA ≤ 70°C (Note 3) – 40°C ≤ TA ≤ 85°C (Note 3) ● ● VOSTC Offset Error Tempco TYP MAX 14 14 Bits Bits ±0.3 ±1.2 0 ±1 LSB ±4 LSB 6.5 9.0 mV mV ±6.5 ±9.0 mV mV ±15 µV/°C ±24 ● Gain Error Gain Error Drift UNITS 5 LSB ppm/°C Power Supply VCC Positive Supply Voltage For Specified Performance ● 5.5 V ICC Supply Current (SLOW/FAST) 2.7V ≤ VCC ≤ 5.5V (Note 5) SLOW 2.7V ≤ VCC ≤ 5.5V (Note 5) FAST 2.7V ≤ VCC ≤ 3.3V (Note 5) SLOW 2.7V ≤ VCC ≤ 3.3V (Note 5) FAST In Shutdown (Note 5) ● ● ● ● ● 540 930 350 680 3 850 1400 500 1000 10 µA µA µA µA µA Short-Circuit Current Low VOUT Shorted to GND ● 70 120 mA Short-Circuit Current High VOUT Shorted to VCC ● 80 120 mA Output Impedance to GND Input Code = 0 ● 40 200 Ω Power Supply Rejection REFHIA, REFHIB = 4.096V (VCC = 5V ±10%) REFHIA, REFHIB = 2.048V (VCC = 3V ±10%) Input Code = 16383 ● 2.5 mV/V 2.7 Op Amp DC Performance PSR 1654fb 2 LTC1654 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.20 1.25 0.9 3.8 V/µs V/µs 8.5 3.0 µs µs AC Performance ● ● Voltage Output Slew Rate (Note 8) SLOW (Note 8) FAST Voltage Output Settling Time (Note 4) to ±1LSB, SLOW (Note 4) to ±1LSB, FAST Digital Feedthrough (Note 7) 1 nV•s Midscale Glitch Impulse DAC Switch Between 8000 and 7FFF 20 nV•s Output Noise Voltage Density at 10kHz, SLOW at 10kHz, FAST 170 150 nV/√Hz nV/√Hz VIH Digital Input High Voltage VCC = 5V ● VIL Digital Input Low Voltage VCC = 5V ● VOH Digital Output High Voltage VCC = 5V, IOUT = – 1mA, DOUT Only ● VOL Digital Output Low Voltage VCC = 5V, IOUT = 1mA, DOUT Only ● VIH Digital Input High Voltage VCC = 3V ● VIL Digital Input Low Voltage VCC = 3V ● VOH Digital Output High Voltage VCC = 3V, IOUT = – 1mA, DOUT Only ● VOL Digital Output Low Voltage VCC = 3V, IOUT = 1mA, DOUT Only ● 0.4 V ILEAK Digital Input Leakage VIN = GND to VCC ● ±10 µA CIN Digital Input Capacitance (Note 6) 10 pF Digital I/O 2.4 V 0.8 VCC – 0.4 V V 0.4 2.4 V V 0.8 VCC – 0.4 V V Reference Input Reference Input Resistance REFHI to REFLO ● 30 Reference Input Range (Note 6) ● 0 Reference Input Current In Shutdown ● 60 kΩ VCC V 1 µA Switching Characteristics (VCC = 4.5V to 5.5V) ● t1 SDI Valid to SCK Setup 30 ns t2 SDI Valid to SCK Hold (Note 6) ● 0 ns t3 SCK High Time (Note 6) ● 15 ns t4 SCK Low Time (Note 6) ● 15 ns t5 CS/LD Pulse Width (Note 6) ● 15 ns t6 LSB SCK to CS/LD (Note 6) ● 10 ns t7 CS/LD Low to SCK (Note 6) ● 10 ns t8 SD0 Output Delay CLOAD = 100pF ● 5 t9 SCK Low to CS/LD Low (Note 6) ● 10 ns t10 CLR Pulse Width (Note 6) ● 30 ns ● 45 ns 100 ns Switching Characteristics (VCC = 2.7V to 5.5V) t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold (Note 6) ● 0 ns t3 SCK High Time (Note 6) ● 20 ns t4 SCK Low Time (Note 6) ● 20 ns t5 CS/LD Pulse Width (Note 6) ● 20 ns t6 LSB SCK to CS/LD (Note 6) ● 15 ns t7 CS/LD Low to SCK (Note 6) ● 15 ns 1654fb 3 LTC1654 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 150 ns Switching Characteristics (VCC = 2.7V to 5.5V) t8 SDO Output Delay CLOAD = 100pF ● 5 t9 SCK Low to CS/LD Low (Note 6) ● 15 ns t10 CLR Pulse Width (Note 6) ● 45 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from low code kL to code 16383. See Applications Information (page 11). Note 3: Offset error is measured at low code kL. See Applications Information (page 11). Note 4: DAC switched between code 2 kL and code 16383. See Applications Information (page 11) for definition of low code kL. Note 5: Digital inputs at 0V or VCC. Note 6: Guaranteed by design. Note 7: CS/LD = 0, VOUT = 4.096V and data is being clocked in. Note 8: 100pF load capacitor. U W TYPICAL PERFOR A CE CHARACTERISTICS Differential Nonlinearity (DNL) vs Input Code 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 8192 16383 8192 0 16383 OUTPUT PULL-DOWN VOLTAGE (V) GAIN ERROR (LSB) 0 –2.5 CODE: ALL 1s 0.9 VREFHI = 4.096V 0.8 0.8 0.7 0.7 CODE: ALL ZEROS 0.6 0.5 TA = 125°C 0.4 65 TEMPERATURE (°C) 95 125 1654 G04 TA = 25°C TA = 25°C TA = 125°C 0.6 0.5 0.4 TA = –55°C 0.3 0.3 0.2 0.2 0 125 95 Minimum Supply Headroom vs Load Current (Output Sourcing) 0.9 TA = –55°C 0.1 35 5 35 65 TEMPERATURE (°C) 1.0 1.0 5.0 2.5 –25 1654 G03 Minimum Output Voltage vs Load Current (Output Sinking) Gain Error vs Temperature 5 –2.50 –55 1654 G02 1654 G01 –25 0 INPUT CODE INPUT CODE –5.0 –55 1.25 –1.25 VCC – VOUT (V) 0 2.50 0 –0.5 –2.0 Offset vs Temperature OFFSET ERROR (mV) 2.0 DNL (LSB) INL (LSB) Integral Nonlinearity (INL) vs Input Code 0.1 0 0 10 5 OUTPUT SINK CURRENT (mA) 15 1645 G05 0 10 5 LOAD CURRENT (mA) 15 1645 G06 1654fb 4 LTC1654 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Logic Input Voltage Large-Signal Settling—Slow Mode Large-Signal Settling—Fast Mode SUPPLY CURRENT (mA) 3.0 VOUT 1V/DIV VOUT 1V/DIV CS/LD 2V/DIV CS/LD 2V/DIV 1.5 0 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) 5 TIME (2µs/DIV) TIME (2µs/DIV) 1654 G08 1654 G09 1654 G07 Midscale Glitch—Fast Mode Midscale Glitch—Slow Mode VOUT Glitch at Power-Up VCC 0.5V/DIV VOUT 10mV/DIV VOUT 10mV/DIV CS/LD 2V/DIV CS/LD 2V/DIV TIME (1µs/DIV) 1654 G10 VOUT 50mV/DIV TIME (1µs/DIV) 1654 G11 TIME (50ms/DIV) 1654 G12 1654fb 5 LTC1654 U U U PI FU CTIO S X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of 1/2 Pin. When this pin is tied to VOUT, the output range will be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when REFLO = 0V). When this pin is tied to REFLO, the output range will be REFLO to REFHI (0V to REFHI when REFLO = 0V). These pins should not be left floating. CS/LD (Pin 5): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the SCK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, the control/address bits are decoded. CLR (Pin 2): The Asynchronous Clear Input. SDO (Pin 7): The output of the shift register that becomes valid on the rising edge of the serial clock. DGND/AGND (Pins 6, 12): Digital and Analog Grounds. SCK (Pin 3): The TTL Level Input for the Serial Interface Clock. VOUT A/B (Pins 9, 15): The Buffered DAC Outputs. SDI (Pin 4): The TTL Level Input for the Serial Interface Data. Data on the SDI pin is latched into the shift register on the rising edge of the serial clock. The LTC1654 allows either a 24-bit or 32-bit word. When a 24-bit word is used, the first 8 bits are control and address followed by 16 data bits. The last two of the 16 data bits are don’t cares. When a 32-bit word (required for daisy-chain operation) is used, the first 8-bits are don’t cares and the following 24-bits are as above. REFHI A/B (Pins 10, 14): The Reference High Inputs of the LTC1654. There is a gain of 1 from this pin to the output in a gain of 1 configuration. In a gain of 1/2 configuration, there is a gain of 1/2 from this pin to VOUT. REFLO A/B (Pins 11, 13): The Reference Low Inputs of the LTC1654. These inputs can swing up to VCC – 1.5V. VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V. Requires a 0.1µF bypass capacitor to ground. WU W TI I G DIAGRA S t2 t6 t1 t4 t3 t7 SCK t9 SDI X X C3 B0 X X t5 CS/LD t8 SDO X (PREVIOUS WORD) X C3 X X X CURRENT WORD 1654 TD01 1654fb 6 X X SDI SDO SCK CS/LD 1 X X 2 X X X 4 X X X DON’T CARE 5 C3 SDI 3 1 SCK CS/LD C1 3 X X 6 X X 7 X X CONTROL BITS C2 2 8 A1 7 ADDRESS BITS A2 6 A0 8 B13 9 B12 10 B11 11 B10 12 B9 13 B8 14 B7 15 B5 17 DATA WORD B6 16 B4 18 B3 19 C3 C3 9 C1 11 C2 C1 CONTROL BITS C2 10 C0 C0 12 A3 A3 A2 14 A1 15 A1 16 A0 A0 PREVIOUS STREAM A2 ADDRESS BITS 13 B13 B13 17 B12 B12 18 32-BIT DATA STREAM B10 B10 20 B13 t1 B9 B9 21 22 t8 t3 t2 B7 B7 t4 23 B12 B6 18 21 B5 25 B1 B5 DATA WORD B6 24 B2 20 PREVIOUS B12 17 B8 B8 SDO PREVIOUS B13 SDI SCK B11 B11 19 Figure 1a. 24-Bit Load Sequence (for Non-Daisy-Chained Applications) A3 5 B4 B4 26 B0 22 B3 B3 27 X 23 B2 B2 28 X 24 B1 B1 29 B0 B0 30 1654TD02a X X 31 X X 32 1654 TD02b CURRENT STREAM WU W TI I G DIAGRA S Figure 1b. 32-Bit Load Sequence (for Single and Daisy-Chained LTC1654s) C0 4 24-BIT DATA STREAM LTC1654 1654fb 7 LTC1654 U OPERATIO Serial Interface The data on the SDI input is loaded into the shift register on the rising edge of SCK. The MSB is loaded first. The Clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. If no daisy-chaining is required, the input word can be 24-bit wide, as shown in the timing diagrams. The 8 MSBs, which are loaded first, are the control and address bits followed by a 16-bit data word. The last two LSBs in the data word are don’t cares. The input word can be a stream of three 8-bit wide segments as shown in the “24-Bit Update” timing diagram. If daisy-chaining is required or if the input needs to be written in two 16-bit wide segments, then the input word can be 32 bits wide and the top 8 bits (MSBs) are don’t cares. The remaining 24 bits are control/address and data. This is also shown in the timing diagrams. The buffered output of the internal 32-bit shift register is available on the SDO pin, which swings from GND to VCC. Multiple LTC1654s may be daisy-chained together by connecting the SDO pin to the SDI pin of the next IC. The SCK and CS/LD signals remain common to all ICs in the daisy-chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all DACs simultaneously. Table 1 shows the truth table for the control/address bits. When the supplies are first applied, the LTC1654 uses SLOW mode, the outputs are set at 0V, and zeros are loaded into the 32-bit input shift register. About 300ns after power-up, the outputs are released from 0V (AGND) and will go to the voltage on the REFLO pin. When CLR goes active, zeros are loaded into the input and DAC latch and the outputs are forced to AGND. After CLR is forced high, the ouputs will go to the voltage on the REFLO pin. Three examples are given to illustrate the DAC’s operation: 1. Load and update DAC A in FAST mode. Leave DAC B unchanged. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in FAST mode CS/LD CS/LD clock in 0101 0000 XXXXXXXX XXXXXXXX; Step 2: Load and update DAC A with DATA CS/LD clock in 0011 0000 + DATA; CS/LD 2. Load and update DAC A in SLOW mode. Power down DAC B. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in SLOW mode CS/LD clock in 0110 0000 XXXXXXXX XXXXXXXX; CS/LD Step 2: Load and update DAC A with DATA CS/LD clock in 0011 0000 + DATA; CS/LD Step 3: Power down DAC B CS/LD clock in 0100 0001 XXXXXXXX XXXXXXXX; CS/LD 3. Power down both DACs at the same time. Perform the following sequence for the control, address and DATA bits: Step 1: Power down both DACs simultaneously CS/LD clock in 0100 1111 XXXXXXXX XXXXXXXX; CS/LD 1654fb 8 LTC1654 U OPERATIO Voltage Output The LTC1654 comes complete with rail-to-rail voltage output buffer amplifiers. These amplifiers will swing to within a few millivolts of either supply rail when unloaded and to within a 450mV of either supply rail when sinking or sourcing 5mA. There are two GAIN configuration modes for the LTC1654: a) GAIN of 1: (X1/X1/2 tied to REFLO) VOUT = (VREFHI – VREFLO)(CODE/16384) + VREFLO b) GAIN of 1/2: (X1/X1/2 tied to VOUT) VOUT = (1/2)(VREFHI – VREFLO)(CODE/16384) + VREFLO The LTC 1654 has two SPEED modes: A FAST mode and a SLOW mode. When operating in the FAST mode, the output amplifiers will settle in 3µs (typ) to 14 bits on a 4V output swing. In the SLOW mode, they will settle in 8.5µs. The total supply current is 930µA in the FAST mode and 540µA in the SLOW mode. The output noise voltage density at 10kHz is 170nV/√Hz in SLOW mode and 150nV/√Hz in FAST mode. Power Down Each DAC can also be independently powered down to less than 5µA/DAC of supply current. The reference pin also goes into a high impedance state when the DAC is powered down and the reference current will drop to below 0.1µA. The amplifiers’ output stage is also three-stated but the VOUT pins still have the internal gain-setting resistors connected to them resulting in an effective resistance from VOUT to REFLO. This resistance is typically 90k when the X1/X1/2 pin is tied to VOUT and 36k when X1/X1/2 is tied to REFLO. Because of this resistance, VOUT will go to VREFLO when the DAC is powered down and VOUT is unloaded. 1654fb 9 LTC1654 U OPERATIO Table 1. CONTROL ADDRESS (n) C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 Load Input Register n 0 0 0 0 DAC A 0 0 1 DAC B 0 0 0 1 Update (Power-Up) DAC Register n 0 0 0 1 0 Load Input Register n, Update (Power-Up) All 0 0 1 0 Reserved (Do Not Use) 0 0 1 1 Load and Update n 0 0 1 1 Reserved (Do Not Use) 1 0 0 Reserved (Do Not Use) 0 1 0 0 Power Down n 0 0 1 0 1 Fast n (Speed States are Maintained Even If DAC is Put in Power-Down Mode) 0 1 0 1 Reserved (Do Not Use) 0 1 1 0 Reserved (Do Not Use) 0 1 1 0 Slow n (Default State is Slow When Supplies are Powered Up) 0 1 1 1 Reserved (Do Not Use) 0 1 1 1 Reserved (Do Not Use) 1 0 0 0 Reserved (Do Not Use) 1 0 0 0 Reserved (Do Not Use) 1 0 0 1 Reserved (Do Not Use) 1 0 0 1 Reserved (Do Not Use) 1 0 1 0 Reserved (Do Not Use) 1 0 1 0 Reserved (Do Not Use) 1 0 1 1 Reserved (Do Not Use) 1 0 1 1 Reserved (Do Not Use) 1 1 0 0 Reserved (Do Not Use) 1 1 0 0 Reserved (Do Not Use) 1 1 0 1 Reserved (Do Not Use) 1 1 0 1 Reserved (Do Not Use) 1 1 1 0 Reserved (Do Not Use) 1 1 1 0 Reserved (Do Not Use) 1 1 1 1 Both DACs 1 1 1 1 No Operation INPUT WORD CONTROL C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (14 + 2 DON'T CARE LSBs) A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1654 TABLE 1654fb 10 LTC1654 U W U U APPLICATIO S I FOR ATIO Rail-to-Rail Output Considerations Rail-to-rail DACs take full advantage of the supply range available to them, but cannot produce output voltages above VCC or below ground. See Figure 2a. The offset, gain error and linearity of the LTC1654 are defined and tested in output ranges that avoid limiting. The low code kL used in these measurements is defined as the code which gives a nominal output of 32mV above ground; see Table 2. If REFLO is tied to GND, the output for the lowest codes may limit at 0V, as shown in Figure 2b. Similarly, limiting can occur near full scale if the REFHI pin is tied to VCC, as shown in Figure 2c. VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 8192 INPUT CODE (a) 16383 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1654 F02 Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC GAIN Table 2. Low Code kL VREFHI, V 4.096 2.048 1 128 256 1/2 256 512 Note: VREFLO = O 1654fb 11 LTC1654 U U DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits (n). It is also the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Nominal LSBs: Voltage Offset Error (VOS): Normally, DAC offset is the voltage at the output when the DAC is loaded with all zeros. The DAC can have a true negative offset, but because the part is operated from a single supply, the output cannot go below 0V. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 3. Zero-Scale Error (ZSE): The output voltage when the DAC is loaded with all zeros. Since this is a single supply part, this value cannot be less than 0V. OUTPUT VOLTAGE NEGATIVE OFFSET 0V DAC CODE 1654 F01 Figure 3. Effect of Negative Offset Therefore, the offset of the part is measured at low code kL: VOS = (kL )( VFS ) 2n – 1 kL ⎞ ⎛ ⎜⎝ 1 – n ⎟⎠ 2 –1 VOUT (kL ) – LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/16383 LTC1654 LSB = 4.09575V/16383 = 250µV Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between low code kL and full scale. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/16383)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal one LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB ∆V OUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in nV • s. 1654fb 12 LTC1654 U TYPICAL APPLICATIO S This circuit shows how to use an LTC1654 and an LT®1077 to make a wide bipolar output swing 14-bit DAC with an offset that can be digitally programmed. VOUTA, which can be set by loading the appropriate code for DAC A, sets the offset. As this value changes, the transfer curve for the output moves up and down as illustrated in the graph below. A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset 5V 0.1µF LTC1654 2 3 µP 4 5 6 7 8 X1/X1/2 B VCC CLR VOUT B SCK REFHI B SDI REFLO B CS/LD AGND DGND REFLO A SDO REFHI A X1/X1/2 A VOUT A 16 15 14 49.9k 1% 13 15V + 12 100k 1% 11 10 VOUT 2 (VOUTB – VOUTA) LT1077 – –15V 9 49.9k 1% 1654 TA02 100k 1% 10 VOUTA ≅ 0V 5 VOUTA ≅ 2.5V VOUT 1 0 CODE VOUTA ≅ 5V 16383 –5 –10 1654 TA03 1654fb 13 LTC1654 U TYPICAL APPLICATIO S Dual 14-Bit Voltage Output DAC 2.7V TO 5.5V 0.1µF LTC1654 1 2 3 µP 4 5 6 7 8 X1/X1/2 B VCC CLR VOUT B SCK REFHI B SDI REFLO B CS/LD AGND DGND REFLO A SDO REFHI A X1/X1/2 A VOUT A 16 15 OUTPUT B: 0V TO VCC 14 13 12 11 10 9 OUTPUT A: 0V TO VCC 1654 TA01 1654fb 14 LTC1654 U PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ± .005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .053 – .068 (1.351 – 1.727) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0502 1654fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1654 U TYPICAL APPLICATIO A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset 5V 0.1µF LTC1654 1 2 3 µP 4 5 6 7 8 X1/X1/2 B VCC CLR VOUT B SCK REFHI B SDI CS/LD REFLO B AGND DGND REFLO A SDO REFHI A X1/X1/2 A VOUT A 16 15 14 13 49.9k 1% 15V + 12 11 VOUT 2 (VOUTB – VOUTA) LT1077 100k 1% – 10 –15V 9 49.9k 1% 100k 1% 1654 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin 5V, Low Power Complete VOUT DAC in SO-8 Package LTC1452 Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC LT1460 Micropower Precision Reference Low Cost, 10ppm Drift LT1461 Precision Voltage Reference Ultralow Drift 3ppm/°C, Initial Accuracy: 0.04% LT1634 Micropower Precision Reference Low Drift 10ppm/°C, Initial Accuracy: 0.05% 16 Linear Technology Corporation References 1654fb LT/LT 0705 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2000