Infineon HYB18T512400AF-3S 512-mbit ddr2 sdram Datasheet

D a t a S he et , Rev. 1.3, J a n. 2 00 5
HYB18T512400AF
HYB18T512800AF
HYB18T512160AF
512-Mbit DDR2 SDRAM
DDR2 SDRAM
RoHS Compliant Products
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S he et , Rev. 1.3, J a n. 2 00 5
HYB18T512400AF
HYB18T512800AF
HYB18T512160AF
512-Mbit DDR2 SDRAM
DDR2 SDRAM
RoHS Compliant Products
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
Revision History:
2005-01
Previous Version:
2004-09 (Rev. 1.2)
Rev. 1.3
Page
Subjects (major changes since last revision)
113
Added tDS1, tDH1 derating for Single-Ended DQS for DDR2-400 and DDR2-533
All
Added 50 Ohm support
All
Document contains green products only
Chapter 8
Pull-up and Pull-Down Driver Characteristics have been updated
We Listen to Your Comments
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Template: mp_a4_s_rev300 / 2004-11-30
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Table of Contents
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
13
2
2.1
2.2
2.3
Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TFBGA Ball Out Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
20
23
24
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.22.1
3.22.2
3.23
3.23.1
3.23.2
3.23.3
3.23.4
3.24
3.24.1
3.24.2
3.25
3.26
3.26.1
3.26.2
3.27
3.28
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR2 SDRAM Extended Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable (Qoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-ended and Differential Data Strobe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register EMR(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register EMR(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous CKE LOW Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
28
29
29
31
33
33
33
34
35
36
39
45
46
47
49
50
53
56
57
58
58
60
62
62
65
66
67
67
67
68
69
73
73
73
74
74
4
Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5
5.1
5.2
AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Data Sheet
5
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Table of Contents
5.3
5.4
5.5
5.5.1
5.6
5.7
5.8
5.9
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Strength Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6.1
6.1.1
Currents Measurement Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7
7.1
7.2
7.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Speed Grade Defenitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
AC Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slew Rate Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Slew Rate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition for Input Setup (tIS) and Hold Time (tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition for Data Setup (tDS) and Hold Time (tDH), differential Data Strobes . . . . . . . . . . . . . . .
Definition Data Setup (tDS1) and Hold Time (tDH1), Single-Ended Data Strobes . . . . . . . . . . . . . .
Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup (tIS) and Hold (tIH) Time Derating Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
10
Product Namenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Data Sheet
6
79
81
82
84
86
88
89
89
105
105
105
105
105
106
106
106
107
108
110
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Data Sheet
High Performance DDR667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Performance for DDR2–400B and DDR2–533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Definition (BA[2:0] = 000B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-ended and Differential Data Strobe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . .
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . .
Off Chip Driver Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-Chip-Driver Adjust Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Selection for Precharge by Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Command Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Delay Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSTL_18 Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Strength Default Pull-up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Strength Default Pull–down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Strength Calibrated Pull-up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Strength Default Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Strength Default Pull–down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . .
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specification for DDR2–667C and DDR2-667D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specification for DDR2–533C and DDR2–400B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Measurement Test Conditions for DDR2–667C and DDR2–667D . . . . . . . . . . . . . . . . . . . . . .
IDD Measurement Test Condition for DDR2–533C and DDR2–400B . . . . . . . . . . . . . . . . . . . . . . .
ODT current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definition Speed Bins for DDR667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definition Speed Bins for DDR533 and DDR400 . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
11
12
13
14
19
19
23
30
31
33
34
35
37
37
40
49
58
66
67
75
76
76
77
77
78
78
78
79
79
80
81
81
81
82
83
85
85
86
87
88
89
89
90
91
92
93
94
95
96
96
97
97
98
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Tables
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Data Sheet
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . .
Derating Values for Input Setup and Hold Time (DDR2-667). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533) . . . . . . . . . . . . . . . . .
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667) . . . . . . . . . . . .
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533). . . . . . .
Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533). . . . .
Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
101
104
104
110
111
112
112
113
116
116
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Data Sheet
Pin Configuration for ×4 components, P-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for ×8 components, P-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for ×16 components, P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram 32 Mbit × 4 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram 16 Mbit × 8 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram 8 Mbit × 16 I/O ×4 Internal Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence after Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCD Impedance Adjustment Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagram Adjust Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagram Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings). . . . . . . . . . . . . . .
ODT Timing for Precharge Power-Down and Active Power-Down Mode. . . . . . . . . . . . . . . . . . . .
ODT Mode Entry Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT Mode Exit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Activate Command Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activate to Read Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . .
Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . .
Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . .
Read to Write Timing Example: Read followed by a write to the same bank . . . . . . . . . . . . . . . .
Write to Read Timing Example: Write followed by a read to the same bank . . . . . . . . . . . . . . . . .
Basic Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by Write Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Seamless Read Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Seamless Read Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Read Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Seamless Write Operation Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Seamless Write Operation Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation with Data Mask Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Interrupt Timing Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Interrupt Timing Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Followed by Precharge Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Followed by Precharge Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Followed by Precharge Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Followed by Precharge Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation Followed by Precharge Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Precharge Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Precharge Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit) . .
Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit) .
Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank . . . . . . . . . .
Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank, . . . . . . . . . .
Write with Auto-Precharge Example 1 (tRC Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Auto-Precharge Example 2 (WR + tRP Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
20
21
22
24
25
26
27
28
36
38
38
39
41
42
43
44
45
46
47
47
48
48
48
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
59
59
60
60
61
61
63
63
64
64
65
65
68
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
List of Figures
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Data Sheet
Self Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Active Power-Down Mode Entry and Exit after an Activate Command . . . . . . . . . . . . . . . . . . . . . 70
Active Power-Down Mode Entry and Exit Example after a Read Command . . . . . . . . . . . . . . . . . 71
Active Power-Down Mode Entry and Exit Example after a Write Command . . . . . . . . . . . . . . . . . 71
Active Power-Down Mode Entry and Exit Example after a Write Command with AP . . . . . . . . . . 72
Precharge Power Down Mode Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Auto-Refresh command to Power-Down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MRS, EMRS command to Power-Down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Input Frequency Change Example during Precharge Power-Down mode . . . . . . . . . . . . . . . . . . . 74
Asynchronous Low Reset Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Full Strength Default Pull-up Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Full Strength Default Pull–down Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Reduced Strength Default Pull-up Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reduced Strength Default Pull–down Driver Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . 90
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . 90
Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Input Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Setup and Hold Time (Differential Data Strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Setup and Hold Time (Single Ended Data Strobes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Slew Rate Definition Nominal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Slew Rate Definition Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Package Pinout PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Package Pinout PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
512-Mbit DDR2 SDRAM
DDR2 SDRAM
1
HYB18T512400AF
HYB18T512800AF
HYB18T512160AF
Overview
This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main
characteristics.
1.1
Features
The 512-Mbit DDR2 SDRAM offers the following key features:
•
•
•
•
•
•
•
•
•
1.8 V ± 0.1 V Power Supply
1.8 V ± 0.1 V (SSTL_18) compatible I/O
DRAM organisations with 4, 8 and 16 data
in/outputs
Double Data Rate architecture: two data transfers
per clock cycle, four internal banks for concurrent
operation
CAS Latency: (2), 3, 4 and 5
Burst Length: 4 and 8
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
•
•
•
•
•
•
•
•
•
•
•
Table 1
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
Average Refresh Period 7.8 µs
Full and reduced Strength Data-Output Drivers
1K page size for ×4 & ×8, 2K page size for ×16
Packages:
P-TFBGA-60 for ×4 & ×8 components
P-TFBGA-84 for ×16 components
RoHS Compliant Products1)
High Performance DDR667
Product Type Speed Code
–3
–3S
Unit
Speed Grade
DDR2–667C 4–4–4
DDR2–667D 5–5–5
—
333
333
MHz
333
266
MHz
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
200
200
MHz
12
15
ns
12
15
ns
45
45
ns
57
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the
Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium,
polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
11
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Overview
Table 2
High Performance for DDR2–400B and DDR2–533C
Product Type Speed Code
–3.7
–5
Unit
Speed Grade
DDR2–533C 4–4–4
DDR2–400B 3–3–3
—
266
200
MHz
266
200
MHz
200
200
MHz
15
15
ns
15
15
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
45
40
ns
60
55
ns
Description
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
The 512-Mb DDR2 DRAM is a high-speed DoubleData-Rate-2 CMOS Synchronous DRAM device
containing 536,870,912 bits and internally configured
as a quad-bank DRAM. The 512-Mb device is
organized as either 32 Mbit × 4 I/O × 4 banks, 16 Mbit
× 8 I/O × 4 banks or 8 Mbit × 16 I/O × 4 banks chip.
These synchronous devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications. See Table 3 for performance figures.
A 16-bit address bus for ×4 and ×8 organised
components and a 15-bit address bus for ×16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The device is designed to comply with all DDR2 DRAM
key features:
1.
2.
3.
4.
5.
posted CAS with additive latency,
write latency = read latency - 1,
normal and weak strength data-output driver,
Off-Chip Driver (OCD) impedance adjustment
On-Die Termination (ODT) function.
Data Sheet
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA package.
12
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Overview
1.3
Ordering Information
Table 3
Ordering Information for RoHS compliant products
Part Number
Org. Speed
HYB18T512400AF–5
×4
HYB18T512800AF–5
×8
HYB18T512160AF–5
×16
HYB18T512400AF–3.7 ×4
CAS1)RCD2)RP3) Clock CAS1)RCD2)RP3)
Latencies
(MHz) Latencies
Clock Package
(MHz)
DDR2–400 3–3–3
200
—
—
DDR2–533 4–4–4
266
3–3–3
200
P-TFBGA-60
P-TFBGA-84
P-TFBGA-60
HYB18T512800AF–3.7 ×8
HYB18T512160AF–3.7 ×16
HYB18T512400AF–3
×4
HYB18T512800AF–3
×8
HYB18T512160AF–3
×16
HYB18T512400AF–3S ×4
P-TFBGA-84
DDR2–667 4–4–4
333
3–3–3
200
P-TFBGA-60
P-TFBGA-84
5–5–5
333
4–4–4
266
P-TFBGA-60
HYB18T512800AF–3S ×8
HYB18T512160AF–3S ×16
P-TFBGA-84
1) CAS: Column Adress Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
Note: For product nomenclature see Chapter 10 of this data sheet
Data Sheet
13
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2
Pin Configuration and Block Diagrams
The pin configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Pin#/Buffer
Type columns are explained in Table 5 and Table 6 respectively. The pin numbering for the FBGA package is
depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 4
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8 organizations
E8
CK
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
F8
CK
I
SSTL
Note: CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
F2
CKE
I
SSTL
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active PowerDown (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After VREF has become stable during power-on and
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit, VREF must be maintained to this input. CKE must
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are disabled
during power-down
Clock Signals ×16 organization
J8
CK
I
SSTL
K8
CK
I
SSTL
K2
CKE
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
G7
CAS
I
SSTL
F3
WE
I
SSTL
Note: RAS, CAS and WE (along with CS) define the command
being entered.
G8
CS
I
SSTL
Chip Select
Note: All command are masked when CS is registered HIGH. CS
provides for external rank selection on systems with
multiple memory ranks. CS is considered part of the
command code.
Data Sheet
14
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
Bank Address Bus 1:0
G3
BA1
I
SSTL
Note: BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also
determines if the mode register or extended mode register
is to be accessed during a MRS or EMRS(1) cycle
H8
A0
I
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
H3
A1
I
SSTL
H7
A2
I
SSTL
J2
A3
I
SSTL
J8
A4
I
SSTL
J3
A5
I
SSTL
J7
A6
I
SSTL
K2
A7
I
SSTL
K8
A8
I
SSTL
K3
A9
I
SSTL
Note: Address Signal 10/Autoprecharge provides the row address
for Activate commands and the column address and AutoPrecharge bit A10 (=AP) for Read/Write commands to
select one location out of the memory array in the respective
bank. A10(=AP) is sampled during a Precharge command
to determine whether the Precharge applies to one bank
(A10=LOW) or all banks (A10=HIGH). If only one bank is to
be precharged, the bank is selected by BA[1:0]. The
address inputs also provide the op-code during Mode
Register Set commands.
H2
A10
I
SSTL
AP
I
SSTL
K7
A11
I
SSTL
L2
A12
I
SSTL
L8
A13
I
SSTL
NC
–
–
Address Signal 13
Note: 512 Mbit components
Note: 256 Mbit components
Address Signals ×16 organization
L2
BA0
I
SSTL
L3
BA1
I
SSTL
L1
NC
–
–
Data Sheet
Bank Address Bus 1:0
15
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
M8
A0
I
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
Data Signals ×4/×8 organizations
C8
DQ0
I/O
SSTL
Data Signal 3:0
C2
DQ1
I/O
SSTL
D7
DQ2
I/O
SSTL
Note: Bi-directional data bus. DQ[3:0] for ×4 components, DQ[7:0]
for ×8 components
D3
DQ3
I/O
SSTL
Data Signals ×8 organization
D1
DQ4
I/O
SSTL
D9
DQ5
I/O
SSTL
B1
DQ6
I/O
SSTL
B9
DQ7
I/O
SSTL
Data Signal 7:4
Data Signals ×16 organization
Data Sheet
16
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
G8
DQ0
I/O
SSTL
Data Signal 15:0
G2
DQ1
I/O
SSTL
Note: Bi-directional data bus. DQ[15:0] for ×16 components
H7
DQ2
I/O
SSTL
H3
DQ3
I/O
SSTL
H1
DQ4
I/O
SSTL
H9
DQ5
I/O
SSTL
F1
DQ6
I/O
SSTL
F9
DQ7
I/O
SSTL
C8
DQ8
I/O
SSTL
C2
DQ9
I/O
SSTL
D7
DQ10
I/O
SSTL
D3
DQ11
I/O
SSTL
D1
DQ12
I/O
SSTL
D9
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
B9
DQ15
I/O
SSTL
Data Strobe ×4/×8 organisations
B7
DQS
I/O
SSTL
Data Strobe
A8
DQS
I/O
SSTL
Note: Output with read data, input with write data. Edge aligned
with read data, centered with write data. For the ×16, LDQS
corresponds to the data on DQ[7:0]; UDQS corresponds to
the data on DQ[15:8]. The datastrobes DQS, LDQS, UDQS
may be used in single ended mode or paired with the
optional complementary signals DQS, LDQS, UDQS and
RDQS to provide differential pair signaling to the system
during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals
Data Strobe ×8 organisations
B3
RDQS
I
SSTL
Read Data Strobe
A2
RDQS
I
SSTL
Read Data Strobe
Data Strobe Upper Byte
Data Strobe ×16 organization
B7
UDQS
I/O
SSTL
A8
UDQS
I/O
SSTL
F7
LDQS
I/O
SSTL
E8
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×4/×8 organizations
Data Sheet
17
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
B3
DM
I
SSTL
Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading. LDM and UDM
are the input mask signals for ×16 components and control
the lower or upper bytes. For ×8 components the data mask
function is disabled, when RDQS/RDQS are enabled by
EMRS(1) command.
Data Mask ×16 organization
B3
UDM
I
SSTL
Data Mask Upper Byte
F3
LDM
I
SSTL
Data Mask Lower Byte
Power Supplies ×4/×8/×16 organizations
A9,C1,C3,C7,
C9
VDDQ
PWR
–
I/O Driver Power Supply
A1
VDD
VSSQ
PWR
–
Power Supply
PWR
–
Power Supply
VSS
PWR
–
Power Supply
A7,B2,B8,D2,
D8
A3,E3
Power Supplies ×4/×8 organizations
E2
E1
E9,H9,L1
E7
J1,K9
VREF
VDDL
VDD
VSSDL
VSS
AI
–
I/O Reference Voltage
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
AI
–
I/O Reference Voltage
PWR
–
I/O Driver Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
Power Supplies ×16 organization
J2
E9, G1, G3,
G7, G9
VREF
VDDQ
VDDL
E1, J9, M9, R1 VDD
E7, F2, F8, H2, VSSQ
J1
H8
J7
J3,N1,P9
VSSDL
VSS
Not Connected ×4/×8 organizations
G1, L3,L7, L8
NC
NC
–
Not Connected
Note: No internal electrical connection is present
Not Connected ×4 organization
A2, B1, B9,
D1, D9
Data Sheet
NC
NC
–
Not Connected
18
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
–
Not Connected
SSTL
On-Die Termination Control
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
Other Pins ×4/×8 organizations
F9
ODT
I
Note: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is
applied to each DQ, DQS, DQS and DM signal for ×4 and
DQ, DQS, DQS, RDQS, RDQS and DM for ×8
configurations. For ×16 configuration ODT is applied to
each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM
signal. The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Other Pins ×16 organization
K9
Table 5
ODT
I
SSTL
On-Die Termination Control
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Data Sheet
19
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2.1
TFBGA Ball Out Diagrams
!
6331
$13
6$$1
$-
"
$13
6331
.#
$1
6$$1
#
6$$1
$1
6$$1
.#
6331
$1
$
$1
6331
.#
6$$,
62%&
633
%
633$,
#+
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#+%
7%
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(
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!
*
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+
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!
.#
,
.#
.# !
6$$
.#
633
.#
6331
6$$1
.#
633
6$$
6$$
633
-004
Figure 1
Pin Configuration for ×4 components, P-TFBGA-60 (top view)
Note:
1. VDDL and VSSDL are power and ground for the
DLL.They are isolated on the device from VDD,
VDDQ, VSS, and VSSQ
Data Sheet
2. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit
20
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
6$$
.#
2$13
633
$1
6331
6$$1
!
6331
$13
6$$1
$-
2$13
"
$13
6331
$1
$1
6$$1
#
6$$1
$1
6$$1
$1
6331
$1
$
$1
6331
$1
6$$,
62%&
633
%
633$,
#+
6$$
#+%
7%
&
2!3
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'
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!
(
!
!
!
!
*
!
!
!
!
+
!
!
!
.#
,
.#
.# !
.#
633
6$$
6$$
633
-004
Figure 2
Pin Configuration for ×8 components, P-TFBGA-60 (top view)
Note:
4. VDDL and VSSDL are power and ground for the DLL.
They are isolated on the device from VDD, VDDQ, VSS
and VSSQ.
5. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit.
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is
disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
Data Sheet
21
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
!
6331
5$13
6$$1
5$-
"
5$13
6331
$1
$1
6$$1
#
6$$1
$1
6$$1
$1
6331
$1
$
$1
6331
$1
6$$
.#
633
%
6331
,$13
6$$1
$1
6331
,$-
&
,$13
6331
$1
6$$1
$1
6$$1
'
6$$1
$1
6$$1
$1
6331
$1
(
$1
6331
$1
6$$,
62%&
633
*
633$,
#+
6$$
#+%
7%
+
2!3
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/$4
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,
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!!0
!
-
!
!
!
!
.
!
!
!
!
0
!
!
!
.#
2
.#
.#
6$$
.#
633
$1
6331
6$$1
.#
633
6$$
6$$
633
-004
Figure 3
Pin Configuration for ×16 components, P-TFBGA-84 (top view)
Note:
3. VDDL and VDDSL are power and ground for the DLL.
They are isolated on the device from VDD, VDDQ, VSS
and VSSQ.
1. UDQS/UDQS is data strobe for DQ[15:8],
LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the
data mask signal for DQ[15:8]
Data Sheet
22
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
2.2
512 Mbit DDR2 Addressing
Table 7
512 Mbit DDR2 Addressing
Configuration
128 Mb x 4
64 Mb x 8
32 Mb x 16
Note
Bank Address
BA[1:0]
BA[1:0]
BA[1:0]
Number of Banks
4
4
4
Auto-Precharge
A10 / AP
A10 / AP
A10 / AP
Row Address
A[13:0]
A[13:0]
A[12:0]
Column Address
A11, A[9:0]
A[9:0]
A[9:0]
Number of Column
Address Bits
11
10
10
1)
Number of I/Os
4
8
16
2)
Page Size [Bytes]
1024 (1K)
1024 (1K)
2048 (2K)
3)
1) Refered to as ’colbits’
2) Refered to as ’org’
3) PageSize = 2colbits × org/8 [Bytes
Data Sheet
23
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
$-
$13 $ 13
$1 $1
Block Diagrams
/$ 4
2.3
2ECEIVERS
$ ATA
#+
#+
7RITE
&)&/
$ RIV ERS
-ASK
# /, # OLUM N
#$OLUMN
ECODER
#OLUMN
$ ECODER
#$OLUM
N
EC ODER
$ECODER
# OLUMN !DDRESS
# OUNTER,ATCH
"ANK # ONTROL
,OGIC
2EFRESH #OUNTER
-ODE
2EGIS TERS
# OM MAND
$ECODE
# ONTROL ,OGIC
2OW !DDRESS -58
X
)/ 'ATING
$- -ASK ,OGIC
3ENS E !MPLIFIER
-EMORY
!RRAY
X X 2 OW !DDRESS
,ATC H $ECODER
"ANK "ANK " ANK "ANK "ANK "ANK "ANK "ANK 2EAD ,ATCH
# /, -58
# /, )NPUT
2 EGISTER
$ 13
'ENERATOR
$ATA
$1 3
$1 3
$RIVERS
$,,
# + #+
/$4 #ONTROL
Figure 4
!
!
"!
"!
2!3
#!3
7%
#3
#+
#+
#+%
!DDRESS 2EGISTER
-0"4
Block Diagram 32 Mbit × 4 I/O ×4 Internal Memory Banks
Note:
1. 128Mb × 4 Organisation with 14 Row, 2 Bank and
11 Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
device; it does not represent an actual circuit
implementation.
3. DM is a unidirectional signal (input only), but is
internally loaded to match the load of the
bidirectional DQ and DQS signals.
24
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
$-
2$ 13 2$ 13
$13 $ 13
/$ 4
$1 $1
Pin Configuration and Block Diagrams
2ECEIVERS
#+
#+
7RITE
&)&/
$ RIV ERS
$ ATA
-ASK
# /, # OLUM N
#
$OLUMN
ECODER
#OLUMN
$ ECODER
#$OLUM
N
EC ODER
$ECODER
# OLUMN !DDRESS
# OUNTER,ATCH
"ANK # ONTROL
,OGIC
2EFRESH #OUNTER
-ODE
2EGIS TERS
# OM MAND
$ECODE
# ONTROL ,OGIC
2OW !DDRESS -58
X )/ 'ATING
$- -ASK ,OGIC
3ENS E !MPLIFIER
-EMORY
!RRAY
X X 2 OW !DDRESS
,ATC H $ECODER
"ANK "ANK "ANK "ANK "ANK "ANK "ANK "ANK 2EAD ,ATCH
# /, )NPUT
2 EGISTER
-58
# /, $ 13
'ENERATOR
$ATA
$1 3
$1 3
$RIVERS
$ ,,
# + #+
/$4 #ONTROL
Figure 5
!
!
"!
"!
2!3
#!3
7%
#3
#+
#+
#+%
!DDRESS 2EGISTER
-0"4
Block Diagram 16 Mbit × 8 I/O ×4 Internal Memory Banks
Note:
1. 64Mb × 8 Organisation with 14 Row, 2 Bank and 10
Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
device; it does not represent an actual circuit
implementation.
3. DM is a unidirectional signal (input only), but is
internally loaded to match the load of the
bidirectional DQ and DQS signals.
25
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
5 $ - ,$ -
,$ 13 ,$ 13
/$ 4
$ 1 $1
5 $ 13 5$ 13
Pin Configuration and Block Diagrams
2ECEIVERS
# /, # /, # OLUM N
#OLUMN
$ ECODER
#OLUMN
$ ECODER
#$EC
OLUM
N
ODER
$ECODER
#OLUMN !DDRESS
# OUNTER,ATCH
"ANK # ONTROL
,OGIC
2EFRESH #OUNTER
-ODE
2EGIS TERS
# OM MAND
$ ECODE
#ONTROL ,OGIC
2OW !DDRESS -58
X )/ 'ATING
$- -ASK ,OGIC
3ENS E !MPLIFIER
-EMORY
!RRAY
X X 2 OW !DDRESS
,ATC H $ECODER
"ANK "ANK "ANK "ANK "ANK "ANK "ANK "ANK 2EAD ,ATCH
#+
#+
7RITE
&)&/
$RIV ERS
$ ATA
-ASK
)NPUT
2 EGISTER
-58
# /, $1 3
'ENERATOR
$ATA
$1 3
$1 3
$RIVERS
$,,
# + #+
/$4 #ONTROL
Figure 6
!
!
"!
"!
2!3
#!3
7%
#3
#+
#+
#+%
!DDRESS 2EGISTER
-0"4
Block Diagram 8 Mbit × 16 I/O ×4 Internal Memory Banks
Note:
1. 32Mb × 16 Organisation with 13 Row, 2 Bank and
10 Column External Adresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
Data Sheet
device; it does not represent an actual circuit
implementation.
3. LDM, UDM is a unidirectional signal (input only), but
is internally loaded to match the load of the
bidirectional LDQS and UDQS signals.
26
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3
Functional Description
3.1
Simplified State Diagram
#+%,
)NITIALIZATION
3EQUENCE
3ELF
2EFRESH
/#$
CALIBRATION
32&
02
3ETTING
-23 OR
%-23
#+%(
)DLE
!LL BANKS
PRECHARGED
% -23
2%&
2EFRESHING
#+%,
#+%,
!#4
#+%(
0RECHARGE
0OWER
$OWN
!CTIVATING
#+%,
#+%,
#+%,
!CTIVE 0OWER
$OWN
#+%(
#+%,
!UTOMATIC 3EQUENCE
#OMMAND 3EQUENCE
"ANK
!CTIVE
7RITE
2EAD
7RITE
2EAD
72!
2$!
2EAD
7RITING
2EADING
7RITE
72!
2$!
2$!
7RITING
WITH !0
0202!
0202!
0202!
2EADING WITH
!0
0RECHARGING
-0&4
Figure 7
Simplified State Diagram
Note: This Simplified State Diagram is intended to
provide a floorplan of the possible state
transitions and the commands to control them. In
particular situations involving more than one
Data Sheet
bank, enabling / disabling on-die termination,
Power-Down entry / exit, timing restrictions
during state transitions - among other things - are
not captured in full detail.
27
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.2
Basic Functionality
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
3.3
Power On and Initialization
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
3. Apply NOP or Deselect commands and take CKE
high.
4. Continue NOP or Deselect Commands for 400 ns,
then issue a Precharge All command.
5. Issue EMRS(2) command.
6. Issue EMRS(3) command.
7. Issue EMRS(1) command to enable DLL.
8. Issue a MRS command for “DLL reset”.
9. Issue Precharge-all command.
10. Issue 2 or more Auto-refresh commands.
11. Issue the final MRS command to turn the DLL on
and to set the necessary operating parameter.
12. At least 200 clocks after step 8, issue EMRS(1)
commands to either execute the OCD calibration or
select the OCD default. Issue the final EMRS(1)
command to exit OCD calibration mode and set the
necessary operating parameters.
13. The DDR2 SDRAM is now ready for normal
operation.
1. Apply power and attempt to maintain CKE below
0.2 × VDDQ and ODT at a low state (all other inputs
may be undefined). To guarantee ODT off, VREF
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for VDD / VDDQ
is specified as 20.0 ms. The power interval is
defined as the amount of time it takes for VDD / VDDQ
to power-up from 0 V to 1.8 V ± 100 mV. At least
one of these two sets of conditions must be met:
– VDD, VDDL and VDDQ are driven from a single power
converter output, AND
– VTT is limited to 0.95 V max, AND
– VREF tracks VDDQ/2
or
– Apply VDD before or at the same time as VDDL.
– Apply VDDL before or at the same time as VDDQ.
– Apply VDDQ before or at the same time as VTT &
VREF.
2. Start clock (CK, CK) and maintain stable power and
clock condition for a minimum of 200 µs.
CK, CK
CKE
ODT "low"
tRP
400 ns
NOP
PRE
ALL
EMRS(2)
tMRS
tMRS
EMRS(3)
tMRS
EMRS(1)
tMRS
MRS
tRP
PRE
ALL
tRFC
1st Auto
refresh
2nd Auto
refresh
tRFC
tMRS
MRS
Follow OCD
flowchart
EMRS(1)
OCD
tMRS
EMRS(1)
OCD
Any
Command
min. 200 cycles to lock the DLL
Extended
Mode
Register(1) Set
with DLL enable
Figure 8
Data Sheet
Mode
Register
Set with
DLL reset
Mode
Register
Set w/o
DLL reset
OCD Drive(1)
or
OCD default
OCD
calibration
mode exit
Initialization Sequence after Power up
28
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.4
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS
latency, DLL reset function, write recovery time (WR)
are user defined variables and must be programmed
with a Mode Register Set (MRS) command.
Additionally, DLL disable function, additive CAS
latency, driver impedance, On Die Termination (ODT),
single-ended strobe and Off Chip Driver impedance
adjustment (OCD) are also user defined variables and
must be programmed with an Extended Mode Register
Set (EMRS) command.
All banks must be in a precharged state and CKE must
be high at least one cycle before the Mode Register Set
Command can be issued. Either MRS or EMRS
Commands are activated by the low signals of CS,
RAS, CAS and WE at the positive edge of the clock.
When both bank addresses BA[1:0] are 0, the DDR2
SDRAM enables the MRS command. When the bank
addresses BA0 is 1 and BA1is 0, the DDR2 SDRAM
enables the EMRS(1) command.
The address input data during this cycle defines the
parameters to be set as shown in the MRS and EMRS
tables. A new command may be issued after the mode
register set command cycle time (tMRD).
Contents of the Mode Register (MR) or Extended Mode
Registers (EMR(1, 2, 3)) can be altered by re-executing
the MRS and EMRS Commands. If the user chooses to
modify only a subset of the MR or EMR variables, all
variables must be redefined when the MRS or EMRS
commands are issued.
MRS, EMRS and DLL Reset do not affect array
contents, which means reinitialization including those
can be executed any time after power-up without
affecting array contents.
After initial power up, all MRS and EMRS Commands
must be issued before read or write cycles may begin.
3.5
DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the
various operating modes of DDR2 SDRAM. It programs
CAS latency, burst length, burst sequence, test mode,
DLL reset, Write Recovery (WR) and various vendor
specific options to make DDR2 SDRAM useful for
various applications.
command and clock cycle requirements during normal
operation as long as all banks are in the precharged
state. The mode register is divided into various fields
depending on functionality.
Burst length is defined by A[2:0] with options of 4 and 8
bit burst length. Burst address sequence type is defined
by A3 and CAS latency is defined by A[6:4]. A7 is used
for test mode and must be set to 0 for normal DRAM
operation. A8 is used for DLL reset. A[11:9] are used for
write recovery time (WR) definition for Auto-Precharge
mode. With address bit A12 two Power-Down modes
can be selected, a “standard mode” and a “low-power”
Power-Down mode, where the DLL is disabled.
Address bit A13 and all “higher” address bits have to
be set to 0 for compatibility with other DDR2 memory
products with higher memory densities.
The default value of the mode register is not defined,
therefore the mode register must be written after
power-up for proper operation. The mode register is
written by asserting low on CS, RAS, CAS, WE,
BA[1:0], while controlling the state of address pins
A[13:0]. The DDR2 SDRAM should be in all bank
precharged (idle) mode with CKE already high prior to
writing into the mode register. The mode register set
command cycle time (tMRD) is required to complete
the write operation to the mode register. The mode
register contents can be changed using the same
Data Sheet
29
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
"! "! "!
!
!
0$
W
REG ADDR
!
!
!
!
!
!
!
!
!
!
!
72
$,,
4-
#,
"4
",
W
W
W
W
W
W
!
-0"4
Table 8
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2, Bank Address
BA1
15
Bank Address [1]
0B
BA1, Bank Address
BA0
14
Bank Address [0]
BA0, Bank Address
0B
A13
13
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
PD
12
w
WR
[11:9] w
A13, Address bit 13
Active Power-Down Mode Select
0B
PD, Fast exit
PD, Slow exit
1B
Write Recovery2)
Note: All other bit combinations are illegal.
001B
010B
011B
100B
110B
WR, 2
WR, 3
WR, 4
WR, 5
WR, 6
DLL
8
w
DLL Reset
0B
DLL, No
DLL, Yes
1B
TM
7
w
Test Mode
0B
TM, Normal Mode
TM, Vendor specific test mode
1B
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
010B
011B
100B
101B
011B
Data Sheet
CL, 2
CL, 3
CL, 4
CL, 5
CL, 6
30
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Table 8
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BT
3
w
Burst Type
BT, Sequential
0B
1B
BT, Interleaved
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by
tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to
fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN.
3.6
DDR2 SDRAM Extended Mode Register Set (MRS)
The Extended Mode Register EMR(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
"! "! "!
!
!
!
!
!
EMR(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
BA0, while controlling the state of the address pins
!
!
!
!
!
!
!
!
!
1OFF 2$13 $13
/#$ 0ROGRAM
2TT
!,
2TT
$)#
$,,
W
W
W
W
W
W
W
REG ADDR
W
-0"4
Table 9
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2, Bank Address
BA1
15
Bank Address [1]
0B
BA1, Bank Address
BA0
14
Bank Address [0]
BA0, Bank Address
0B
Data Sheet
31
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Table 9
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
A13
13
w
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13, Address bit 13
Qoff
12
Output Disable
QOff, Output buffers enabled
0B
1B
QOff, Output buffers disabled
RDQS
11
Read Data Strobe Output (RDQS, RDQS)
0B
RDQS, Disable
RDQS, Enable
1B
DQS
10
Complement Data Strobe (DQS Output)
0B
DQS, Enable
DQS, Disable
1B
OCD
[9:7]
Program
Off-Chip Driver Calibration Program
000B OCD, OCD calibration mode exit, maintain setting
001B OCD, Drive (1)
010B OCD, Drive (0)
100B OCD, Adjust mode
111B OCD, OCD calibration default
AL
Additive Latency
[5:3]
Note: All other bit combinations are illegal.
000B
001B
010B
011B
100B
101B
AL, 0
AL, 1
AL, 2
AL, 3
AL, 4
AL, 5
RTT
2,6
Nominal Termination Resistance of ODT
00B RTT, ∞ (ODT disabled)
01B RTT, 75 Ohm
10B RTT, 150 Ohm
11B RTT, 50 Ohm2)
DIC
1
Off-chip Driver Impedance Control
0B
DIC, Full (Driver Size = 100%)
1B
DIC, Reduced
DLL
0
DLL Enable
DLL, Enable
0B
1B
DLL, Disable
1) w = write only register bits
2) optional for DDR2-400/533 & 667
Data Sheet
32
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables On-Die termination (ODT) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
3.7
Address bit A12 have to be set to 0 for normal
operation. With A12 set to 1 the SDRAM outputs are
disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to
be set to access the EMRS(1). A13 and all “higher”
address bits have to be set to 0 for compatibility with
other DDR2 memory products with higher memory
densities. Refer to Extended Mode Register Definition.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically reenabled and reset upon exit of Self-Refresh operation.
3.8
Any time the DLL is reset, 200 clock cycles must occur
before a Read command can be issued to allow time for
the internal clock to be synchronized with the external
clock. Failing to wait for synchronization to occur may
result in a violation of the tAC or tDQSCK parameters.
Output Disable (Qoff)
DRAM outputs allows users to measure IDD currents
during Read operations, without including the output
buffer current and external load currents.
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMR(1) is set to 0). When the Qoff bit is set to 1,
the DRAM outputs will be disabled. Disabling the
3.9
Single-ended and Differential Data Strobe Signals
in ×8 components only. If RDQS is enabled in ×8
components, the DM function is disabled. RDQS is
active for reads and don’t care for writes.
Table 10 lists all possible combinations for DQS, DQS,
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
Table 10
Single-ended and Differential Data Strobe Signals
EMRS(1)
Strobe Function Matrix
Signaling
A11
A10
RDQS/DM
(RDQS Enable) (DQS Enable)
RDQS
DQS
DQS
0 (Disable)
0 (Enable)
DM
Hi-Z
DQS
DQS
0 (Disable)
1 (Disable)
DM
Hi-Z
DQS
Hi-Z
single-ended DQS signals
1 (Enable)
0 (Enable)
RDQS
RDQS
DQS
DQS
differential DQS signals
1 (Enable)
1 (Disable)
RDQS
Hi-Z
DQS
Hi-Z
single-ended DQS signals
Data Sheet
33
differential DQS signals
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.10
Extended Mode Register EMR(2)
The Extended Mode Registers EMR(2) and EMR(3)
are reserved for future use and must be programmed
when setting the mode register during initialization.The
extended mode register EMR(2) is written by asserting
LOW on CS, RAS, CAS, WE, BA0 and HIGH on BA1,
while controlling the states of the address pins. The
DDR2 SDRAM should be in all bank precharge with
"! "! "!
!
!
!
!
!
CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (tMRD) must be satisfied to complete the write
operation to the EMR(2). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
!
!
!
!
!
!
!
!
!
REG ADDR
-0"4
Table 11
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA1
15
Bank Adress[1]
BA1, Bank Address
1B
BA0
14
Bank Adress[0]
0B
BA0, Bank Address
A
[13:0]
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A[13:0], Address bits
1) w = write only
Data Sheet
34
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.11
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
"! "! "!
!
!
!
!
!
initialization. The EMRS(3) is written by asserting low
on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
while controlling the state of the address pins.
!
!
!
!
!
!
!
!
!
REG ADDR
-0"4
Table 12
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA1
15
Bank Adress[1]
1B
BA1, Bank Address
BA0
14
Bank Adress[0]
BA0, Bank Address
1B
A
[13:0] w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A[13:0], Address bits
1) w = write only
Data Sheet
35
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.12
Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and
the flow chart below is an example of the sequence.
Every calibration mode command should be followed
by “OCD calibration mode exit” before any other
command being issued. MRS should be set before
entering OCD impedance adjustment and On Die
Termination (ODT) should be carefully controlled
depending on system environment.
OCD Impedance Adjustment Flow Chart
3TART
%-23 /#$ CALIBRATION MODE EXIT
%-23 $RIVE $1 $13 (IGH $13 ,OW
%-23 $RIVE $1 $13 ,OW $13 (IGH
!,, /+
!,, /+
4EST
4EST
.EED #ALIBRATION
.EED #ALIBRATION
%-23 /#$ CALIBRATION MODE EXIT
%-23 /#$ CALIBRATION MODE EXIT
%-23
%NTER !DJUST -ODE
%-23
%NTER !DJUST -ODE
", CODE INPUT TO ALL $1S
)NC $EC OR ./0
", CODE INPUT TO ALL $1S
)NC $EC OR ./0
%-23 /#$ CALIBRATION MODE EXIT
%-23 /#$ CALIBRATION MODE EXIT
%-23 /#$ CALIBRATION MODE EXIT
%ND
-0&4
Figure 9
OCD Impedance Adjustment Flow Chart
Note: MR should be set before entering OCD impedance adjustment and ODT should be carefully controlled
depending on system environment
Data Sheet
36
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the
following EMRS(1) mode. In drive mode all outputs are
driven out by DDR2 SDRAM and drive of RDQS is
dependent on EMR(1) bit enabling RDQS operation. In
Drive(1)mode, all DQ, DQS (and RDQS) signals are
driven HIGH and all DQS (and RDQS) signals are
driven LOW. InDrive(0) mode, all DQ, DQS (and
RDQS) signals are driven LOW and all DQS (and
RDQS) signals are driven HIGH. In adjust mode, BL =
4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a
nominal impedance value of 18 Ohms during nominal
Table 13
temperature and voltage conditions. Output driver
characteristics for OCD calibration default are specified
in the following table. OCD applies only to normal full
strength output drive setting defined by EMR(1) and if
half strength is set, OCD default driver characteristics
are not applicable. When OCD calibration adjust mode
is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or
driver strength is set to default, subsequent EMRS(1)
commands not intended to adjust OCD characteristics
must specify A[9:7] as’000’ in order to maintain the
default or calibrated value.
Off Chip Driver Program
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low
0
1
0
Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high
1
0
0
Adjust mode
1
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must
issue the ADJUST EMRS(1) command along with a 4
bit burst code to DDR2 SDRAM as in the following
table. For this operation, Burst Length has to be set to
BL = 4 via MRS command before activating OCD and
controllers must drive the burst code to all DQs at the
same time. DT0 in the table means all DQ bits at bit
time 0, DT1 at bit time 1, and so forth. The driver output
impedance is adjusted for all DDR2 SDRAM DQs
Table 14
simultaneously and after OCD calibration, all DQs of a
given DDR2 SDRAM will be adjusted to the same driver
strength setting. The maximum step count for
adjustment is 16 and when the limit is reached, further
increment or decrement code has no effect. The default
setting may be any step within the maximum step count
range. When Adjust mode command is issued, AL from
previously set value must be applied.
Off-Chip-Driver Adjust Program
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP (no operation)
NOP (no operation)
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by 1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other Combinations
Data Sheet
Illegal
37
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
For proper operation of adjust mode, WL = RL - 1 =
AL + CL - 1 clocks and tDS / tDH should be met as shown
in Figure 10. Input data pattern for adjustment, DT[0:3]
is fixed and not affected by MRS addressing mode (i.e.
sequential or interleave). Burst length of 4 have to be
programmed in the MRS for OCD impedance
adjustment.
CK, CK
CMD
NOP
EMRS(1)
NOP
NOP
NOP
NOP
NOP
WL
EMRS(1)
NOP
tWR
DQS
DQS_in
tDS tDH
DQ_in
DT0
DT1
DT2
DT3
DM
Figure 10
OCD1
OCD calibration
mode exit
OCD adjust mode
Timing Diagram Adjust Mode
Drive Mode
driven out tOIT after “enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration
mode exit” command. See Figure 11.
Both Drive(1) and Drive(0) are used for controllers to
measure DDR2 SDRAM Driver impedance before OCD
impedance adjustment. In this mode, all outputs are
CK, CK
CMD
EMRS(1)
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tOIT
tOIT
DQS_in
EMRS(1)
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
DQS high for Drive(1)
DQS high for Drive(0)
DQ_in
OCD calibration
mode exit
Enter Drive Mode
Figure 11
Data Sheet
Timing Diagram Drive Mode
38
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off termination resistance for each DQ, DQS, DQS, DM for ×4
and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the
same pin) and RDQS for ×8 configuration via the ODT
control pin. DQS and RDQS are only terminated when
enabled by EMR(1).
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM
controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function
can be used for all active and standby modes. ODT is
turned off and not supported in Self-Refresh mode.
For ×16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
VDDQ
VDDQ
sw2
Rval1
Rval2
EA
DRAM
Input
Buffer
Rval3
Rval3
sw1
sw2
sw3
EL
Rval2
Input
Pin
ODT_funct2
VSSQ
VSSQ
Functional Representation of ODT
Target: Rval1 = Rval2 = Rval3 = 2 × Rtt
Switch sw1, sw2 or sw3 are enabled by the ODT pin.
Selection between sw1, sw2 or sw3 is determined by
“Rtt (nominal)” in EMRS(1) address bits A6 & A2.
Data Sheet
sw3
Rval1
VSSQ
Figure 12
VDDQ
SE
sw1
CO
3.13
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
39
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
ODT Truth Tables
organisations (×4, ×8 and ×16). To activate termination
of any of these pins, the ODT function has to be
enabled in the EMRS(1) by address bits A6 and A2.
The ODT Truth Table shows which of the input pins are
terminated depending on the state of address bit A10
and A11 in the EMRS(1) for all three device
Table 15
ODT Truth Table
Input Pin
EMRS(1)
Address Bit A10
EMRS(1)
Address Bit A11
x4 components
DQ[3:0]
X
DQS
X
DQS
0
DM
X
X
x8 components
DQ[7:0]
X
DQS
X
DQS
0
X
RDQS
X
1
RDQS
0
1
DM
X
0
x16 components
DQ[7:0]
X
DQ[15:8]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
Data Sheet
40
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
ODT timing modes
Depending on the operating mode asynchronous or
synchronous ODT timings apply.
•
Asynchronous ODT timings (tAOFPD, tAONPD) apply when
the on-die DLL is disabled.
•
Synchronous ODT timings (tAOND, tAOFD, tAON, tAOF)
apply for all other modes.
These modes are:
T1
T0
T3
T2
Slow Exit Active Power Down Mode (with MRS bit
A12 is set to “1”)
Precharge Power Down Mode
T4
T5
T6
T7
T8
CK, CK
CKE
t IS
t IS
t IS
ODT
tAOND (2 tck)
tAOFD (2.5 tck)
Rtt
DQ
tAON(min)
tAOF(min)
tAON(max)
tAOF(max)
ODT01
Figure 13
ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings)
Note:
to turn on. ODT turn on time max. (tAON.MAX) is when
the ODT resistance is fully on. Both are measured
from tAOND.
3. ODT turn off time min. (tAOF.MIN) is when the device
starts to turn off the ODT resistance.ODT turn off
time max. (tAOF.MAX) is when the bus is in high
impedance. Both are measured from tAOFD.
1. Synchronous ODT timings apply for Active Mode
and Standby Mode with CKE HIGH and for the
“Fast Exit” Active Power Down Mode (MRS bit A12
set to “0”). In all these modes the on-die DLL is
enabled.
2. ODT turn-on time (tAON.MIN) is when the device
leaves high impedance and ODT resistance begins
Data Sheet
41
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T
1
T
0
T
3
T
2
T
4
T
5
T
6
T
7
T
8
CK, CK
CKE
"low"
t
ODT
t
IS
IS
tAOFPDmax
tAOFPDmin
DQ
Rtt
tAONPD,min
tAONPD,max
ODT02
Figure 14
ODT Timing for Precharge Power-Down and Active Power-Down Mode
Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down
Mode (MRS bit A12 set to “1”), where the on-die DLL is disabled in this mode of operation.
ODT timing mode switch
When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two additional
timing parameters (tANPD and tAXPD) define if synchronous or asynchronous ODT timings have to be applied.
Mode entry
As long as the timing parameter tANPD.MIN is satisfied
when ODT is turned on or off before entering these
power-down modes, synchronous timing parameters
Data Sheet
can be applied. If tANPD.MIN is not
asynchronous timing parameters apply.
42
satisfied,
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T-5
T-4
T-3
T-2
T-1
T0
T1
T2
CK, CK
tANPD (3 tck)
tIS
CKE
ODT turn-off, tANPD >= 3 tck :
tIS
ODT
Synchronous
timings apply
RTT
tAOFD
ODT turn-off, tANPD <3 tck :
ODT
Asynchronous
timings apply
RTT
tAOFPDmax
ODT turn-on, tANPD >= 3 tck :
tIS
ODT
tAOND
Synchronous
timings apply
RTT
tIS
ODT turn-on, tANPD < 3 tck :
tAONPDmax
ODT
Asynchronous
timings apply
RTT
ODT03
Figure 15
Data Sheet
ODT Mode Entry Timing Diagram
43
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Mode exit
As long as the timing parameter tAXPD.MIN is satisfied
when ODT is turned on or off after exiting these powerdown modes, synchronous timing parameters can be
T0
T1
T5
applied. If tAXPD.MIN is not satisfied, asynchronous timing
parameters apply.
T6
T7
T8
T9
T10
CK,
CK
t IS
tAXPD
CKE
t IS
ODT turn-off, tAXPD >= tAXPDmin:
Synchronous
timings apply
ODT
Rtt
tAOFD
ODT turn-off, tAXPD < tAXPDmin:
Asynchronous
timings apply
t IS
ODT
Rtt
tAOFPDmax
ODT turn-on, tAXPD >= tAXPDmin:
Synchronous
timings apply
t IS
ODT
Rtt
t IS
tAOND
ODT turn-on, tAXPD < tAXPDmin:
Asynchronous
timings apply
ODT
Rtt
tAONPDmax
ODT04
Figure 16
Data Sheet
ODT Mode Exit Timing Diagram
44
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.14
Bank Activate Command
latency must be programmed into the device to delay
the R/W command which is internally issued to the
device. The additive latency value must be chosen to
assure tRCD.MIN is satisfied. Additive latencies of 0, 1, 2,
3, 4 and 5 are supported. Once a bank has been
activated it must be precharged before another Bank
Activate command can be applied to the same bank.
The bank active and precharge times are defined as
tRAS and tRP, respectively. The minimum time interval
between successive Bank Activate commands to the
same bank is determined by tRC. The minimum time
interval between Bank Active commands to different
banks is tRRD.
The Bank Activate command is issued by holding CAS
and WE HIGH with CS and RAS LOW at the rising edge
of the clock. The bank addresses BA[1:0] are used to
select the desired bank. The row addresses A0 through
A13 are used to determine which row to activate in the
selected bank for ×4 and ×8 organized components.
For ×16 components row addresses A0 through A12
have to be applied. The Bank Activate command must
be applied before any Read or Write operation can be
executed. Immediately after the bank active command,
the DDR2 SDRAM can accept a read or write command
(with or without Auto-Precharge) on the following clock
cycle. If a R/W command is issued to a bank that has
not satisfied the tRCD.MIN specification, then additive
T0
T1
T2
T3
T4
Tn
Tn+1
Tn+2
Tn+3
CK, CK
Internal RAS-CAS delay tRCDmin.
Address
Bank A
Bank A
Row Addr. Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
NOP
Bank B
Addr.
Bank A
Row Addr.
Bank A
Precharge
NOP
Bank B
Precharge
Bank A
Activate
Bank A to Bank B delay tRRD.
additive latency AL=2 Read A
Begins
Command Bank A
Activate
Posted CAS
Read A
Bank B
Activate
Posted CAS
Read B
tRAS Row Active Time (Bank A)
tRP Row Precharge Time (Bank A)
tCCD
tRC Row Cycle Time (Bank A)
ACT
Figure 17
Bank Activate Command Cycle
tRCD = 3, AL = 2, tRP = 3, tRRD = 2
Data Sheet
45
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.15
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
HIGH, CS and CAS LOW at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE HIGH) or a
write operation (WE LOW). The DDR2 SDRAM
provides a wide variety of fast access modes. A single
Read or Write Command will initiate a serial read or
write operation on successive clock cycles at data rates
of up to 533 Mb/sec/pin for main memory. The
boundary of the burst cycle is restricted to specific
segments of the page length.
Command (CA[11, 9:0]). The second, third and fourth
access will also occur within this segment, however,
the burst order is a function of the starting address, and
the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the
page length of 2048 is divided into 256 uniquely
addressable segments (8-bits × 4 I/O each). The 8-bit
burst operation will occur entirely within one of the 256
segments (defined by CA[7:0]) beginning with the
column address supplied to the device during the Read
or Write Command (CA[11, 9:0]).
A new burst access must not interrupt the previous 4 bit
burst operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (tCCD) is a minimum of 2
clocks for read or write cycles.
For example, the 32 Mbit × 4 I/O × 4 Bank chip has a
page length of 2048 bits (defined by CA[11, 9:0]).
In case of a 4-bit burst operation (burst length = 4) the
page length of 2048 is divided into 512 uniquely
addressable segments (4-bits × 4 I/O each). The 4-bit
burst operation will occur entirely within one of the 512
segments (defined by CA[8:0]) starting with the column
address supplied to the device during the Read or Write
T0
T1
T2
T3
For 8 bit burst operation (BL = 8) the minimum CAS to
CAS delay (tCCD) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation.
For details see Chapter 3.20.
T4
T5
T6
T7
T12
CK, CK
CMD
READ A
NOP
READ B
tC C D
NOP
READ C
NOP
NOP
NOP
NOP
NOP
tC C D
DQS,
DQS
DQ
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout C0
Dout C1
Dout C2
Dout C3
RB
Figure 18
Read Timing Example
CL = 3, AL = 0, RL = 3, BL = 4
Data Sheet
46
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.16
Posted CAS
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the bank activate command (or any
time during the RAS to CAS delay time, tRCD period).
The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The
Read Latency (RL) is the sum of AL and the CAS
1
0
2
3
4
latency (CL). Therefore if a user chooses to issue a
Read/Write command before the tRCD.MIN, then AL
greater than 0 must be written into the EMR(1). The
Write Latency (WL) is always defined as RL - 1 (Read
Latency -1) where Read Latency is defined as the sum
of Additive Latency plus CAS latency (RL=AL+CL). If a
user chooses to issue a Read command after the
tRCD.MIN period, the Read Latency is also defined as
RL = AL + CL.
5
6
7
8
9
10
11
CK, CK
WL = RL -1 = 4
CMD
Activate Read
Bank A Bank A
Write
Bank A
AL = 2
DQS,
DQS
CL = 3
tRCD
RL = AL + CL = 5
DQ
Dout0Dout1 Dout2Dout3
Din0
Din1
Din2
Din3
PostCAS
Figure 19
Activate to Read Timing Example: Read followed by a write to the same bank
Activate to Read delay < tRCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
CK, CK
WL = RL -1 = 4
CMD
Write
Bank A
Activate Read
Bank A Bank A
AL = 2
DQS,
DQS
CL = 3
tRCD
RL = AL + CL = 5
DQ
Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
Din0
Din1
Din2
Din3
PostCAS3
Figure 20
Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay < tRCD.MIN: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
Data Sheet
47
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
0
1
2
3
4
5
6
7
8
9
10
11
CK, CK
AL = 0
CMD
Activate
Bank A
Read
Bank A
Write
Bank A
CL = 3
DQS,
DQS
WL = RL -1 = 2
tRCD
RL = AL + CL = 3
DQ
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS2
Figure 21
Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay = tRCD.MIN: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CK, CK
WL = 3
CMD
Activate
Bank A
Write
Bank A
Read
Bank A
tRCD > tRCDmin.
DQS,
DQS
RL = 4
DQ
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS5
Figure 22
Read to Write Timing Example: Read followed by a write to the same bank
Activate to Read delay > tRCD.MIN: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CK, CK
WL = 3
CMD
Activate
Bank A
Write
Bank A
Read
Bank A
tRCD > tRCDmin.
DQS,
DQS
RL = 4
DQ
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS5
Figure 23
Write to Read Timing Example: Write followed by a read to the same bank
AL = 2, CL = 3, RL = 5, WL = 4, tWTR = 2, BL = 4
Data Sheet
48
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.17
Burst Mode Operation
Burst mode operation is used to provide a constant flow
of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that
define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM
supports 4 bit and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported,
however, sequential address ordering is nibble based
for ease of implementation. The burst length is
programmable and defined by the addresses A[2:0] of
Table 16
the MR. The burst type, either sequential or
interleaved, is programmable and defined by the
address bit 3 (A3) of the MR. Seamless burst read or
write operations are supported. Interruption of a burst
read or write operation is prohibited, when burst length
= 4 is programmed. For burst interruption of a read or
write burst when burst length = 8 is used, see
Chapter 3.21. A Burst Stop command is not supported
on DDR2 SDRAM devices.
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
8
Note:
1. PageSize and Length is a function of I/O organization:
128Mb x 4 organization (CA[9:0], CA11); Page Size = 1 kByte; Page Length = 2048
64Mb x 8 organization (CA[9:0]); Page Size = 1 kByte; Page Length = 1024
32Mb x 16 organization (CA[9:0]); Page Size = 2 kByte; Page Length = 1024
2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR
components
Data Sheet
49
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.18
Read Command
The Read command is initiated by having CS and CAS
LOW while holding RAS and WE HIGH at the rising
edge of the clock. The address inputs determine the
starting column address for the burst. The delay from
the start of the command until the data from the first cell
appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven
LOW one clock cycle before valid data (DQ) is driven
t CH
onto the data bus. The first bit of the burst is
synchronized with the rising edge of the data strobe
(DQS). Each subsequent data-out appears on the DQ
pin in phase with the DQS signal in a source
synchronous manner. The RL is equal to an additive
latency (AL) plus CAS latency (CL). The CL is defined
by the Mode Register Set (MRS). The AL is defined by
the Extended Mode Register Set (EMRS(1)).
t CL
t CK
CLK
CLK, CLK
CLK
t DQSCK
t AC
DQS
DQS,
DQS
DQS
t RPRE
t RPST
t LZ
DQ
Dout
t DQSQmax
t QH
Dout
Dout
Dout
t DQSQmax
t HZ
t QH
DO-Read
Figure 24
Basic Read Timing Diagram
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
<= t DQSCK
DQS,
DQS
AL = 2
CL = 3
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
BRead523
Figure 25
Read Operation Example 1
RL = 5 (AL = 2, CL = 3, BL = 4)
Data Sheet
50
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
< = tD Q S C K
DQS,
DQS
CL = 3
RL = 3
DQ's
Dout A0
Dout A1
Dout A2
Dout A3 Dout A4
Dout A5
Dout A6
Dout A7
BRead303
Figure 26
Read Operation Example 2
RL = 3 (AL = 0, CL = 3, BL = 8)
T0
T3
T1
T4
T5
T6
T7
T8
T9
CK, CK
CMD
P o ste d C A S
READ A
NOP
NOP
P o ste d C A S
W R IT E A
NOP
NOP
NOP
NOP
NOP
BL/2 + 2
DQS,
DQS
WL = RL - 1 = 4
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Din A0
Din A1
Din A2
Din A3
BRBW514
Figure 27
Read followed by Write Example
RL = 5, WL = (RL-1) = 4, BL = 4
The minimum time from the read command to the write command is defined by a read-to-write turn-around time,
which is BL/2 + 2 clocks.
Data Sheet
51
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
Posted CAS
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
AL = 2
CL = 3
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
SBR523
Figure 28
Seamless Read Operation Example 1
RL = 5, AL = 2, CL = 3, BL = 4
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
T0
T1
T2
T3
T4
T5
T6
T7
T9
T8
CK, CK
CMD
Posted CAS
READ A
NOP
NOP
NOP
Posted CAS
NOP
READ B
NOP
NOP
NOP
NOP
DQS,
DQS
CL = 3
DQ
RL = 3
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
Dout B0
Dout B1
Dout B2
Dout B3
Dout B4
SBR_BL8
Figure 29
Seamless Read Operation Example 2
RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
Data Sheet
52
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.19
Write Command
successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is
complete. The time from the completion of the burst
write to bank precharge is named “write recovery time”
(tWR) and is the time needed to store the write data into
the memory array. tWR is an analog timing parameter
(see Chapter 5) and is not the programmed value for
WR in the MRS.
The Write command is initiated by having CS, CAS and
WE LOW while holding RAS HIGH at the rising edge of
the clock. The address inputs determine the starting
column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL –
1). A data strobe signal (DQS) has to be driven LOW
(preamble) a time tWPRE prior to the WL. The first data
bit of the burst cycle must be applied to the DQ pins at
the first rising edge of the DQS following the preamble.
The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on
t DQSH
t DQSL
DQS
DQS,
DQS
DQS
t
t WPRE
Din
t
Figure 30
Din
Din
WPST
Din
t DH
DS
Basic Write Timing
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
<= t DQSS
Precharge
Completion of
the Burst Write
DQS,
DQS
tWR
WL = RL-1 = 4
DQ
NOP
DIN A0
DIN A1
DIN A2
DIN A3
BW543
Figure 31
Write Operation Example 1
RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
Data Sheet
53
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
Bank A
Activate
Completion of
the Burst Write
<= t DQSS
DQS,
DQS
tRP
tWR
WL = RL-1 = 2
DQ
DIN A0
DIN A1
DIN A2
DIN A3
BW322
Figure 32
Write Operation Example 2
RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
CMD
NOP
NOP
Posted CAS
NOP
NOP
READ A
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
CL=3
AL=2
tWTR
WL = RL - 1 = 4
DIN A0
DIN A1
DIN A2
DIN A3
RL=5
BWBR
Figure 33
Write followed by Read Example
RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + tWTR, where tWTR
is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but
the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
Data Sheet
54
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
WRITE A
Posted CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
WL = RL - 1 = 4
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN B0
DIN B1
DIN B2
DIN B3
SBR
Figure 34
Seamless Write Operation Example 1
RL = 5, WL = 4, BL = 4
The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
W R IT E A
NOP
NOP
NOP
W R IT E B
NOP
NOP
NOP
NOP
DQS,
DQS
W L = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN
SBW_BL8
Figure 35
Seamless Write Operation Example 2
RL = 3, WL = 2, BL = 8, non interrupting
The seamless non interrupting 8-bit write operation is supported by enabling a write command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
Data Sheet
55
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.20
Write Data Mask
One write data mask input (DM) for ×4 and ×8
components and two write data mask inputs (LDM,
UDM) for ×16 components are supported on DDR2
SDRAM’s, consistent with the implementation on DDR
SDRAM’s. It has identical timings on write operations
as the data bits, and though used in a uni-directional
manner, is internally loaded identically to data bits to
T
insure matched system timing. Data mask is not used
during read cycles. If DM is HIGH during a write burst
coincident with the write data, the write data bit is not
written to the memory. For ×8 components the DM
function is disabled, when RDQS / RDQS are enabled
by EMRS(1).
T
$13(
$13,
$13 $13
T
$1
$IN
T
T
702%
$IN
$IN
T
$3
7034
$IN
$(
$-
DONgT CARE
-044
Figure 36
Write Data Mask Timing
4
4
4
4
4
4
4
4
4
4
4
4
#,+
#,+
#-$
7RITE !
./0
./0
./0
./0
./0
./0
0RECHARGE
./0
"ANK !
!CTIVATE
./0
T$133
$13
$13
7, 2, $1
T72
$IN
!
$IN
!
$IN
!
T20
$IN
!
$-
-044
Figure 37
Write Operation with Data Mask Example
RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
Data Sheet
56
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.21
Burst Interruption
Interruption of a read or write burst is prohibited for
burst length of 4 and only allowed for burst length of 8
under the following conditions:
6. Read or Write burst with Auto-Precharge enabled is
not allowed to be interrupted.
7. Read burst interruption is allowed by a Read with
Auto-Precharge command.
8. Write burst interruption is allowed by a Write with
Auto-Precharge command.
9. All command timings are referenced to burst length
set in the mode register. They are not referenced to
the actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual
burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 +
tWR, where tWR starts with the rising clock after the
un-interrupted burst end and not from the end of the
actual burst end.
1. A Read Burst can only be interrupted by another
Read command. Read burst interruption by a Write
or Precharge Command is prohibited.
2. A Write Burst can only be interrupted by another
Write command. Write burst interruption by a Read
or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks
after the previous Read command. Any other Read
burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks
after the previous Write command. Any other Read
burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any
bank inside the DDR2 SDRAM.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ S,
DQS
DQ
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout B4
Dout B5
Dout B6
Dout B7
RBI
Figure 38
Read Interrupt Timing Example 1
CL = 3, AL = 0, RL = 3, BL = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
NOP
W R IT E A
NOP
W R IT E B
NOP
NOP
NOP
NOP
NOP
NOP
DQ S,
DQS
DQ
Din A0
Din A1
Din A2
Din A3
Din B0
Din B1
Din B2
Din B3
Dout B4
Din B5
Din B6
Din B7
WBI
Figure 39
Write Interrupt Timing Example 2
CL = 3, AL = 0, WL = 2, BL = 8
Data Sheet
57
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.22
Precharge Command
The Pre-charge Command can be used to precharge
each bank independently or all banks simultaneously. 3
address bits A10, BA[1:0] are used to define which
bank to precharge when the command is issued.
The Precharge Command is used to precharge or close
a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are
LOW and CAS is HIGH at the rising edge of the clock.
Table 17
Bank Selection for Precharge by Address Bits
A10
BA1
BA0
Precharge Bank(s)
0
0
0
Bank 0 only
0
0
1
Bank 1 only
0
1
0
Bank 2 only
0
1
1
Bank 3 only
1
Don’t Care
Don’t Care
all banks
Note: The bank address assignment is the same for activating and precharging a specific bank.
3.22.1
Read Followed by a Precharge
The following rules apply as long as the tRTP timing
parameter - Internal Read to Precharge Command
delay time - is less or equal two clocks, which is the
case for operating frequencies less or equal 266 MHz
(DDR2 400 and 533 speed sorts).
The term (tRTP - 2×tCK) is 0 clocks for operating
frequencies less or equal 266 MHz (DDR2-400 and
DDR2-533 product speed sorts). The term (tRTP - 2×tCK)
is one clock for frequencies higher then 266 MHz
(DDR2-667 speed sort).
Minimum Read to Precharge command spacing to the
same bank = AL + BL/2 clocks. For the earliest possible
precharge, the Precharge command may be issued on
the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the
minimum tRAS timing is satisfied.
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
T0
T1
T2
T3
1. The RAS precharge time (tRP) has been satisfied
from the clock at which the precharge begins.
2. The RAS cycle time (tRC.MIN) from the previous bank
activation has been satisfied.
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
NOP
READ A
Precharge
AL + BL/2 clks
Bank A
Activate
NOP
NOP
NOP
NOP
tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
DQ
Dout A0
>=tRAS
Dout A1
Dout A2
Dout A3
CL = 3
>=tRC
>=tRTP
BR-P413
Figure 40
Read Operation Followed by Precharge Example 1
RL = 4 (AL = 1, CL = 3), BL = 4, tRTP ≤ 2 CKs
Data Sheet
58
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
NOP
NOP
READ A
NOP
Precharge
NOP
NOP
AL + BL/2 clks
Bank A
Activate
tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
DQ
Dout A0
>=tRAS
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
CL = 3
>=tRC
>=tRTP
first 4-bit prefetch
Figure 41
BR-P413(8)
second 4-bit prefetch
Read Operation Followed by Precharge Example 2
RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
NOP
READ A
NOP
NOP
Precharge
AL + BL/2 clks
Bank A
Activate
NOP
NOP
tRP
DQS,
DQS
AL = 2
CL = 3
RL = 5
DQ
Dout A0
>=tRAS
Dout A1
Dout A2
Dout A3
CL = 3
>=tRC
>=tRTP
Figure 42
BR-P523
Read Operation Followed by Precharge Example 3
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 CKs
Data Sheet
59
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
NOP
READ A
Precharge
A
NOP
NOP
NOP
AL + BL/2 clocks
Bank A
Activate
NOP
tRP
DQS,
DQS
AL = 2
CL = 4
RL = 6
DQ
Dout A0
>=tRAS
Dout A1
Dout A2
Dout A3
CL = 4
>=tRC
>=tRTP
Figure 43
BR-P624
Read Operation Followed by Precharge Example 4
T1
T2
CK, CK
READ A
NOP
NOP
T4
NOP
NOP
T5
T6
P re ch a rg e
A L + B L /2 clks + 1
DQS,
DQS
CL = 4
E-
RL = 4
DQ
T7
T8
NOP
NOP
RE
CMD
T3
LE
T0
A
RL = 6, (AL = 2, CL = 4), BL = 4, tRTP ≤ 2 CKs
B ank A
A ctiva te
tR P
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
PR
> = tR A S
first 4-bit prefetch
Figure 44
> = tR T P
BR-P404(8)
second 4-bit prefetch
Read Operation Followed by Precharge Example 5
RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 CKs
3.22.2
Write followed by Precharge
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 + tWR. For write cycles, a delay
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(tWR) referenced from the completion of the burst write
Data Sheet
to the Precharge command. No Precharge command
should be issued prior to the tWR delay, as DDR2
SDRAM does not support any burst interrupt by a
Precharge command. tWR is an analog timing
parameter (see Chapter 7) and is not the programmed
value WR in the MR.
60
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
A
Completion of
the Burst Write
DQS,
DQS
tWR
WL = 3
DQ
DIN A0
DIN A1
DIN A2
DIN A3
BW-P3
Figure 45
Write followed by Precharge Example 1
WL = (RL - 1) = 3, BL = 4, tWR = 3
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
A
Completion of
the Burst Write
DQS,
DQS
tWR
WL = 4
DQ
DIN A0
DIN A1
DIN A2
DIN A3
BW-P4
Figure 46
Write followed by Precharge Example 2
WL = (RL - 1) = 4, BL = 4, tWR = 3
Data Sheet
61
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23
Auto-Precharge Operation
Before a new row in an active bank can be opened, the
active bank must be precharged using either the Precharge Command or the Auto-Precharge function.
When a Read or a Write Command is given to the
DDR2 SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank
to automatically begin precharge at the earliest
possible moment during the burst read or write cycle. If
A10 is LOW when the Read or Write Command is
issued, then normal Read or Write burst operation is
executed and the bank remains active at the
completion of the burst sequence. If A10 is HIGH when
the Read or Write Command is issued, then the AutoPrecharge function is enabled. During Auto-Precharge,
a Read Command will execute as normal with the
exception that the active bank will begin to precharge
3.23.1
internally on the rising edge which is CAS Latency (CL)
clock cycles before the end of the read burst. AutoPrecharge is also implemented for Write Commands.
The Precharge operation engaged by the AutoPrecharge command will not begin until the last data of
the write burst sequence is properly stored in the
memory array. This feature allows the precharge
operation to be partially or completely hidden during
burst read cycles (dependent upon CAS Latency) thus
improving system performance for random data
access. The RAS lockout circuit internally delays the
Precharge operation until the array restore operation
has been completed so that the Auto-Precharge
command may be issued with any read or write
command.
Read with Auto-Precharge
If A10 is 1 when a Read Command is issued, the Read
with Auto-Precharge function is engaged. The DDR2
SDRAM starts an Auto-Precharge operation on the
rising edge which is (AL + BL/2) cycles later from the
Read with AP command if tRAS.MIN and tRTP are
satisfied. If tRAS.MIN is not satisfied at the edge, the start
point of Auto-Precharge operation will be delayed until
tRAS.MIN is satisfied. If tRTP.MIN is not satisfied at the edge,
the start point of Auto-Precharge operation will be
delayed until tRTP.MIN is satisfied.
Auto-Precharge to the next Activate command
becomes AL + tRTP + tRP. For BL = 8 the time from Read
with Auto-Precharge to the next Activate command is
AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be
rounded up to the next integer value. In any event
internal precharge does not start earlier than two clocks
after the last 4-bit prefetch.
In case the internal precharge is pushed out by tRTP, tRP
starts at the point where the internal precharge
happens (not at the next rising clock edge after this
event). So for BL = 4 the minimum time from Read with
1. The RAS precharge time (tRP) has been satisfied
from the clock at which the Auto-Precharge begins.
2. The RAS cycle time (tRC) from the previous bank
activation has been satisfied.
Data Sheet
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
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512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
P o ste d C A S
R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank
A ctiva te
A10 ="high"
AL + BL/2
A u to -P re ch a rg e B e g in s
DQS,
DQS
AL = 2
CL = 3
tRP
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
tRAS
tRCmin.
BR-AP5231
Figure 47
Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
P o ste d C A S
R E A D w /A P
NOP
NOP
NOP
NOP
NOP
B ank
A ctiv a te
NOP
NOP
A10 ="high"
A u to -P re ch a rg e B e g in s
tRAS(min)
DQS,
DQS
AL = 2
CL = 3
tRP
RL = 5
DQ
Dout A0
Dout A1
Dout A2
Dout A3
tRC
BR-AP5232
Figure 48
Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 CKs
Data Sheet
63
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
P o ste d C A S
R E A D w /A P
CMD
NOP
NOP
NOP
A10 ="high"
NOP
NOP
NOP
AL + BL/2
NOP
B ank
A ctiva te
tRP
A u to -P re ch a rg e B e g in s
DQS,
DQS
AL = 1
CL = 3
RL = 4
DQ
Dout A0
Dout A1
Dout A2
Dout A3 Dout A4
Dout A5
Dout A6
Dout A7
>= tRTP
BR-AP413(8)2
second 4-bit prefetch
first 4-bit prefetch
Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank
RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≤ 2 CKs
T1
T2
CK, CK
Posted CAS
READ w/AP
A10 ="high"
NOP
NOP
T4
NOP
NOP
T5
T6
NOP
T7
NOP
NOP
RE
CMD
T3
LE
T0
A
Figure 49
T8
Bank
Activate
AL + tRTP + tRP
Auto-Precharge Begins
AL = 1
DQ
CL = 4
E-
DQS,
DQS
RL = 5
Dout A0
tRTP
Dout A1
Dout A2
Dout A3
PR
tRP
BR-AP4133
first 4-bit prefetch
Figure 50
Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank,
RL = 5 (AL = 1, CL = 4), BL = 4, tRTP = 3 CKs
Data Sheet
64
Rev. 1.3, 2005-01
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23.2
Write with Auto-Precharge
1. The last data-in to bank activate delay time (tDAL =
WR + tRP) has been satisfied.
2. The RAS cycle time (tRC) from the previous bank
activation has been satisfied.
If A10 is HIGH when a Write Command is issued, the
Write with Auto-Precharge function is engaged. The
DDR2 SDRAM automatically begins precharge
operation after the completion of the write burst plus the
write recovery time delay (WR), programmed in the
MRS register, as long as tRAS is satisfied. The bank
undergoing Auto-Precharge from the completion of the
write burst may be reactivated if the following two
conditions are satisfied.
T0
T1
T2
T3
In DDR2 SDRAM’s the write recovery time delay (WR)
has to be programmed into the MRS mode register. As
long as the analog tWR timing parameter is not violated,
WR can be programmed between 2 and 6 clock cycles.
Minimum Write to Activate command spacing to the
same bank = WL + BL/2 + tDAL.
T4
T5
T6
T7
CK, CK
W R IT E
w /A P
CMD
NOP
NOP
A10 ="high"
NOP
NOP
NOP
NOP
Completion of the Burst Write
NOP
B ank A
A c tiv a te
A u to -P re ch a rg e B e g in s
DQS,
DQS
WR
WL = RL-1 = 2
tRP
tDAL
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tRCmin.
>=tRASmin.
BW-AP223
Write with Auto-Precharge Example 1 (tRC Limit)
Figure 51
WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
T3
T4
T5
T6
NOP
NOP
NOP
T8
T7
T9
T12
CK, CK
P o ste d C A S
W R IT E w /A P
CMD
A10 ="high"
NOP
NOP
NOP
NOP
B ank A
A ctiva te
Completion of the Burst Write
A u to -P re ch a rg e B e g in s
DQS,
DQS
WR
WL = RL-1 = 4
tRP
tDAL
DQ
DIN A0 DIN A1 DIN A2 DIN A3
>=tRC
>=tRAS
BW-AP423
Figure 52
Write with Auto-Precharge Example 2 (WR + tRP Limit)
WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4
Data Sheet
65
Rev. 1.3, 2005-01
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23.3
Read or Write to Precharge Command Spacing Summary
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to
the Precharge commands to the same banks and Precharge-All commands.
Table 18
Minimum Command Delays
From Command
To Command
Minimum Delay between “From
Command” to “To Command”
Unit
Note
READ
PRECHARGE (to same banks as
READ)
AL + BL/2 + max(tRTP, 2) - 2×tCK
tCK
1)2)
PRECHARGE-ALL
AL + BL/2 + max(tRTP, 2) - 2×tCK
1)2)
PRECHARGE (to same banks as
READ w/AP)
AL + BL/2 + max(tRTP, 2) - 2×tCK
tCK
tCK
PRECHARGE-ALL
AL + BL/2 + max(tRTP, 2) - 2×tCK
1)2)
PRECHARGE (to same banks as
WRITE)
WL + BL/2 + tWR
tCK
tCK
PRECHARGE-ALL
WL + BL/2 + tWR
2)
PRECHARGE (to same banks as
WRITE w/AP)
WL + BL/2 + WR
tCK
tCK
PRECHARGE-ALL
WL + BL/2 + WR
2)
PRECHARGE (to same banks as
PRECHARGE)
1
tCK
tCK
PRECHARGE-ALL
1
tCK
tCK
tCK
2)
READ w/AP
WRITE
WRITE w/AP
PRECHARGE
PRECHARGE-ALL PRECHARGE
1
PRECHARGE-ALL
1
1)2)
2)
2)
2)
2)
2)
1) RU{tRTP(ns) / tCK(ns)} must be used, where RU stands for “Round Up”
2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge
or precharge-all, issued to that bank. The precharge period is satisfied after tRP,all depending on the latest precharge
command issued to that bank
Data Sheet
66
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23.4
Concurrent Auto-Precharge
DDR2 devices support the “Concurrent AutoPrecharge” feature. A Read with Auto-Precharge
enabled, or a Write with Auto-Precharge enabled, may
be followed by any command to the other bank, as long
as that command does not interrupt the read or write
data transfer, and all other related limitations (e.g.
contention between Read data and Write data must be
avoided externally and on the internal data bus).
Table 19
The minimum delay from a Read or Write command
with Auto-Precharge enabled, to a command to a
different bank, is summarized in the Command Delay
Table. As defined, the WL = RL - 1 for DDR2 devices
which allows the command gap and corresponding
data gaps to be minimized.
Command Delay Table
From Command To Command (different bank,
non-interrupting command)
Minimum Delay with Concurrent Auto- Unit
Precharge Support
WRITE w/AP
Read w/AP
Read or Read w/AP
(CL -1) + (BL/2) + tWTR
Write or Write w/AP
BL/2
Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
BL/2 + 2
Precharge or Activate
1
tCK
tCK
tCK
tCK
tCK
tCK
Note
1)
1)
1) This rule only applies to a selective Precharge command to another bank, a Precharge-All command is illegal
3.24
Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated
in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.
3.24.1
Auto-Refresh Command
Auto-Refresh is used during normal operation of the
DDR2 SDRAM’s. This command is non persistent, so it
must be issued each time a refresh is required. The
refresh addressing is generated by the internal refresh
controller. This makes the address bits ”don’t care”
during an Auto-Refresh command. The DDR2 SDRAM
requires Auto-Refresh cycles at an average periodic
interval of tREFI.MAX.
external address bus is required once this cycle has
started.
When the refresh cycle has completed, all banks of the
SDRAM will be in the precharged (idle) state. A delay
between the Auto-Refresh Command and the next
Activate Command or subsequent Auto-Refresh
Command must be greater than or equal to the AutoRefresh cycle time (tRFC).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of
eight Auto-Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum
absolute interval between any Auto-Refresh command
and the next Auto-Refresh command is 9 × tREFI.
When CS, RAS and CAS are held LOW and WE HIGH
at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be
precharged and idle for a minimum of the precharge
time (tRP) before the Auto-Refresh Command can be
applied. An internal address counter supplies the
addresses during the refresh cycle. No control of the
Data Sheet
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
CK, CK
"high"
CKE
CMD
P re ch a rg e
NOP
> = t RFC
> = t RFC
> = tRP
NOP
AUTO
REFRESH
NOP
AUTO
REFRESH
NOP
NOP
ANY
AR
Figure 53
Auto Refresh Timing
3.24.2
Self-Refresh Command
clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the
device can exit Self-Refresh operation.
The Self-Refresh command can be used to retain data,
even if the rest of the system is powered down. When
in the Self-Refresh mode, the DDR2 SDRAM retains
data without external clocking. The DDR2 SDRAM
device has a built-in timer to accommodate SelfRefresh operation. The Self-Refresh Command is
defined by having CS, RAS, CAS and CKE held LOW
with WE HIGH at the rising edge of the clock. The
device must be in idle state and ODT must be turned off
before issuing Self Refresh command, by either driving
ODT pin LOW or using EMRS(1) command. Once the
command is registered, CKE must be held LOW to
keep the device in Self-Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and
is automatically enabled upon exiting Self Refresh.
When the DDR2 SDRAM has entered Self-Refresh
mode all of the external control signals, except CKE,
are “don’t care”. The DRAM initiates a minimum of one
Auto Refresh command internally within tCKE period
once it enters Self Refresh mode. The clock is internally
disabled during Self-Refresh Operation to save power.
The minimum time that the DDR2 SDRAM must remain
in Self Refresh mode is tCKE. The user may change the
external clock frequency or halt the external clock one
Data Sheet
The procedure for exiting Self Refresh requires a
sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self-Refresh Exit
command is registered, a delay of at least tXSNR must
be satisfied before a valid command can be issued to
the device to allow for any internal refresh in progress.
CKE must remain HIGH for the entire Self-Refresh exit
period tXSRD for proper operation. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self
Refresh mode after tXSNR expires. NOP or deselect
commands must be registered on each positive clock
edge during the Self-Refresh exit interval tXSNR. ODT
should be turned off during tXSNR.
The use of Self Refresh mode introduces the possibility
that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh, the DDR2 SDRAM
requires a minimum of one extra auto refresh command
before it is put back into Self Refresh Mode.
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T4
T3
T5
Tm
Tn
Tr
CK/CK
tRP
tis
tis
tCKE
CKE
tis
tAOFD
>=tXSRD
>= tXSNR
ODT
Self Refresh
Entry
CMD
NOP
CK/CK may
be halted
Figure 54
CK/CK must
be stable
3. tXSNR has to be satisfied for any command except a
Read or a Read with Auto-Precharge command
4. Since CKE is an SSTL input, VREF must be
maintained during Self Refresh.
1. Device must be in the “All banks idle” state before
entering Self Refresh mode.
2. tXSRD (≥ 200 tCK) has to be satisfied for a Read or a
Read with Auto-Precharge command.
Power-Down
Power-down is synchronously entered when CKE is
registered LOW, along with NOP or Deselect
command. CKE is not allowed to go LOW while mode
register or extended mode register command time, or
read or write operation is in progress. CKE is allowed to
go LOW while any other operation such as row
activation, Precharge, Auto-Precharge or Auto-Refresh
is in progress, but power-down IDD specification will not
be applied until finishing those operations.
For Active Power-down two different power saving
modes can be selected within the MRS register,
address bit A12. When A12 is set to LOW this mode is
referred as “standard active power-down mode” and a
fast power-down exit timing defined by the tXARD timing
parameter can be used. When A12 is set to HIGH this
mode is referred as a power saving “low power active
power-down mode”. This mode takes longer to exit
from the power-down mode and the tXARDS timing
parameter has to be satisfied.
The DLL should be in a locked state when power-down
is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM
design guarantees it’s DLL in a locked state with any
CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
Entering power-down deactivates the input and output
buffers, excluding CK, CK, ODT and CKE. Also the DLL
is disabled upon entering Precharge Power-down or
slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In powerdown mode, CKE LOW and a stable clock signal must
be maintained at the inputs of the DDR2 SDRAM, and
all other input signals are “Don’t Care”. Power-down
duration is limited by 9 times tREFI of the device.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
Data Sheet
Read
Command
Self Refresh Timing
Note:
3.25
Non-Read
Command
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Power-Down Entry
Active Power-down mode can be entered after an
Activate command. Precharge Power-down mode can
be entered after a Precharge, Precharge-All or internal
precharge command. It is also allowed to enter powermode after an Auto-Refresh command or MRS /
EMRS(1) command when tMRD is satisfied.
Active Power-down mode entry is prohibited as long as
a Write Burst and the internal write recovery is in
progress. In case of a write command, active powerdown mode entry is allowed when WL + BL/2 + tWTR is
satisfied.
In case of a write command with Auto-Precharge,
Power-down mode entry is allowed after the internal
precharge command has been executed, which is WL
+ BL/2 + WR starting from the write with AutoPrecharge command. In this case the DDR2 SDRAM
enters the Precharge Power-down mode.
Active Power-down mode entry is prohibited as long as
a Read Burst is in progress, meaning CKE should be
kept HIGH until the burst operation is finished.
Therefore Active Power-Down mode entry after a Read
or Read with Auto-Precharge command is allowed after
RL + BL/2 is satisfied.
Power-Down Exit
applied with power-down exit latency, tXP, tXARD or
tXARDS, after CKE goes HIGH. Power-down exit
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command can be
T0
T1
latencies are defined in Chapter 7.2.
T2
Tn
Tn+1
Tn+2
CK, CK
CMD
CKE
A ctivate
NOP
NOP
NOP
NOP
NOP
V alid
C om m and
tIS
tIS
tXARD or
tXARDS *)
Act.PD 0
Active
Power-Down
Exit
Active
Power-Down
Entry
Figure 55
Active Power-Down Mode Entry and Exit after an Activate Command
Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Example : Active Power-Down Mode Entry and Exit after Read Command : RL = 4 (AL = 1, CL =3), BL = 4
Data Sheet
70
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
Tn
T8
Tn+1
Tn+2
CK, CK
READ
R E A D w /A P
NOP
NOP
NO P
NOP
NOP
NOP
NOP
NOP
NOP
PY
CMD
NOP
V a lid
C o m m an d
tIS
CKE
RL + BL/2
tIS
DQS,
DQS
CL = 3
CO
AL = 1
RL = 4
DQ
Dout A0
Dout A1
Dout A2
Dout A3
Active
Power-Down
Entry
Figure 56
tXARD or
tXARDS *)
Active
Power-Down
Exit
Act.PD 1
Active Power-Down Mode Entry and Exit Example after a Read Command
T0
T1
T2
T3
P re ch a rg e
*)
NOP
NOP
NOP
Tn+1
NOP
NOP
Tn+2
V a lid
C om m a nd
NOP
tIS
C KE
tRP
tIS
tXP
Precharge
Power-Down
Exit
RE
Precharge
Power-Down
Entry
Figure 57
NOP
-R
CMD
Tn
EL
CK, CK
EA
Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Active Power-Down Mode Entry and Exit Example after a Write Command
WL = 2, tWTR = 2, BL = 4
Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Data Sheet
71
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
Tn
T7
Tn+1
Tn+2
CK, CK
W R IT E
w /A P
NOP
NOP
NOP
NOP
CKE
NOP
NOP
WL + BL/2 + WR
NOP
tIS
WR
CO
DQ
DIN A0 DIN A1 DIN A2 DIN A3
Active
Power-Down
Entry
Figure 58
NOP
V a lid
C o m m a nd
NOP
tIS
DQS,
DQS
WL = RL - 1 = 2
NOP
PY
CMD
tXARD or
tXARDS *)
Active
Power-Down
Exit
Act.PD 3
Active Power-Down Mode Entry and Exit Example after a Write Command with AP
WL = 2, WR = 3, BL = 4
Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12. WR is the programmed value in the MRS mode register.
T0
T1
T2
T3
Tn
Tn+1
Tn+2
CK, CK
CMD
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
Valid
Command
NOP
tIS
CKE
tIS
tXP
tRP
Precharge
Power-Down
Entry
Figure 59
Precharge
Power-Down
Exit
Precharge Power Down Mode Entry and Exit
Note: "Precharge" may be an external command or an internal precharge following Write with AP.
Data Sheet
72
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
Tn
CK, CK
tRFC
Auto
Refresh
CMD
tXP
Valid
Command
CKE
tis
CKE can go low one clock after an Auto-Refresh command
When tRFC expires the DRAM is in Precharge Power-Down Mode
Figure 60
ARPD
Auto-Refresh command to Power-Down entry
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
CMD
MRS or
EMRS
t MRD
CKE
Enters Precharge Power-Down Mode
Figure 61
MRS, EMRS command to Power-Down entry
3.26
Other Commands
3.26.1
No Operation Command
The No Operation Command (NOP) should be used in
cases when the SDRAM is in a idle or a wait state. The
purpose of the No Operation Command is to prevent
the SDRAM from registering any unwanted commands
between operations. A No Operation Command is
3.26.2
registered when CS is LOW with RAS, CAS, and WE
held HIGH at the rising edge of the clock. A No
Operation Command will not terminate a previous
operation that is still executing, such as a burst read or
write cycle.
Deselect Command
The Deselect Command performs the same function as
a No Operation Command. Deselect Command occurs
Data Sheet
MRS_PD
when CS is brought HIGH, the RAS, CAS, and WE
signals become don’t care.
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.27
Input Clock Frequency Change
cycles after tRP and tAOFD have been satisfied the input
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After tXP has been
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLLre-lock period the DRAM is ready to operate with the
new clock frequency.
During operation the DRAM input clock frequency can
be changed under the following conditions:
•
•
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
In the Precharge Power-down mode the DDR2SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
T0
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+2
Ty+1
Tz
Ty+3
CK, CK
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
D LL
RESET
NOP
V alid
C om m and
CKE
tRP
tAOFD
tXP
Minimum 2 clocks
required before
changing the frequency
Frequency Change
occurs here
200 clocks
Stable new clock
before power-down exit
ODT is off during
DLL RESET
Frequ.Ch.
Figure 62
Input Frequency Change Example during Precharge Power-Down mode
3.28
Asynchronous CKE LOW Reset Event
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously LOW, immediately interrupting any
valid operation. DRAM requires CKE to be maintained
HIGH for all valid operations as defined in this data
sheet. If CKE asynchronously drops LOW during any
valid operation, the DRAM is not guaranteed to
preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay
(tDELAY) before turning off the clocks. Stable clocks must
exist at the input of DRAM before CKE is raised HIGH
again. The DRAM must be fully re-initialized as
described the initialization sequence (Power On and
Initialization, step 4 through 13). DRAM is ready for
normal operation after the initialization sequence. See
Chapter 7 for tDELAY specification.
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an
asynchronous reset event
Figure 63
Data Sheet
Clocks can be turned off after
this point
Asynchronous Low Reset Event
74
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Truth tables
4
Truth tables
Table 20
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[12:11] A10 A[9:0]
BA1
Previous Current
Cycle
Cycle
Note1)2)3)
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
4)5)
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
4)
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
4)6)
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
4)6)7)
L
H
H
H
Single Bank Precharge H
H
L
L
H
L
BA
X
L
X
4)5)
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
4)
Bank Activate
H
H
L
L
H
H
BA
Row Address
Write
H
H
L
H
L
L
BA
Column
L
Column
4)5)8)
Write with AutoPrecharge
H
H
L
H
L
L
BA
Column
H
Column
4)5)8)
Read
H
H
L
H
L
H
BA
Column
L
Column
4)5)8)
Read with AutoPrecharge
H
H
L
H
L
H
BA
Column
H
Column
4)5)8)
No Operation
H
X
L
H
H
H
X
X
X
X
4)
Device Deselect
H
X
H
X
X
X
X
X
X
X
4)
Power Down Entry
H
L
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
Power Down Exit
L
H
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
4)5)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode
Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.21 for details.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the
refresh requirements outlined in Chapter 3.24
Data Sheet
75
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Truth tables
Table 21
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Previous Cycle6) Current Cycle6)
(N-1)
(N)
Power-Down
Command (N)2) 3)
RAS, CAS, WE
Action (N)2)
Note4)5)
Maintain Power-Down
7)8)11)
L
L
X
L
H
DESELECT or NOP Power-Down Exit
7)9)10)11)
L
L
X
8)11)12)
L
H
DESELECT or NOP Self Refresh Exit
9)12)13)14)
Bank(s)
Active
H
L
DESELECT or NOP Active Power-Down Entry
7)9)10)11)15)
All Banks Idle
H
L
DESELECT or NOP Precharge Power-Down
Entry
9)10)11)15)
H
L
AUTOREFRESH
7)11)14)16)
Any State other H
than
listed above
H
Refer to the Command Truth Table
Self Refresh
Maintain Self Refresh
Self Refresh Entry
17)
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See Chapter 3.24.2.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2×tCKE + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress. See Chapter 3.25 and Chapter 3.24 for a detailed list of restrictions.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Table 22
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
Data Sheet
76
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5
AC & DC Operating Conditions
5.1
Absolute Maximum Ratings
Table 23
Absolute Maximum Ratings
Symbol
Parameter
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Rating
Unit
Note
Voltage on VDD pin relative to VSS
–1.0 to +2.3
V
1)2)
Voltage on VDDQ pin relative to VSS
–0.5 to +2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5 to +2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5 to +2.3
V
1)
Storage Temperature
–55 to +100
°C
1)3)
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2) VDD, VDDQ and VDDL must be within 300 mV of each other at all times, and VREF must not be greater than 0.6 x VDDQ.
However when VDD, VDDQ and VDDL are less than 500 mV, VREF may be equal to or less than 300 mV.
3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Table 24
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
TOPER
Operating Temperature
0 to 95
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation,
the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below
85 °C case temperature before initiating self-refresh operation.
Data Sheet
77
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.2
DC Characteristics
Table 25
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Min.
Typ.
Max.
VDD
VDDDL
VDDQ
VREF
VTT
Supply Voltage
1.7
1.8
Supply Voltage for DLL
1.7
Supply Voltage for Output
Input Reference Voltage
1)
2)
3)
4)
Rating
Unit
Note
1.9
V
1)
1.8
1.9
V
1)
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)3)
4)
Termination Voltage
VREF – 0.04
VREF
VREF + 0.04
V
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in die dc level of VREF.
Table 26
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
1)
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Rtt3(eff)
40
50
60
Ω
1)
2)
delta VM
–6.00
—
+ 6.00
%
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac)
respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load:
delta VM = ((2 x VM / VDDQ) – 1) x 100%
Deviation of VM with respect to VDDQ / 2
Table 27
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
IIL
Input Leakage Current; any input 0 V < VIN < VDD
–2
+2
µA
1)
IOL
Output Leakage Current; 0 V < VOUT < VDDQ
–5
+5
µA
2)
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Data Sheet
78
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
Table 28
Symbol
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
Table 29
relative to the rising or falling edges of DQS crossing at
VREF. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
DC & AC Logic Input Levels
Parameter
DDR2-400, DDR2-533
DDR2-667
Min.
Max.
Min.
Max.
Unit
DC input logic high
VREF + 0.125
VREF + 0.125
–0.3
–0.3
VDDQ + 0.3
VREF – 0.125
V
DC input low
VDDQ + 0.3
VREF – 0.125
AC input logic high
VREF + 0.250
—
VREF + 0.200
—
V
AC input low
—
VREF – 0.250
—
VREF – 0.200
V
V
Single-ended AC Input Test Conditions
Symbol
Condition
VREF
VSWING.MAX
Value
Unit
Note
Input reference voltage
0.5 x VDDQ
V
1)
Input signal maximum peak to peak swing
1.0
V
1)
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the
range from VREF to VIL(ac).MAX for falling edges as shown in Figure 64
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac)
SLEW
Input signal minimum Slew Rate
on the negative transitions.
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
V
DDQ
V IH (ac) .MIN
V IH (dc) .MIN
V
SWING.MAX
V REF
V IL (dc) .MAX
V
V
delta TF
Falling Slew =
Data Sheet
SS
delta TR
V REF
- V IL (ac).MAX
Rising Slew =
V IH(ac).MIN -V REF
delta TR
delta TF
Figure 64
IL (ac) .MAX
Single-ended AC Input Test Conditions Diagram
79
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
Table 30
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
DC input signal voltage
–0.3
DC differential input voltage
0.25
AC differential input voltage
0.5
AC differential cross point input
voltage
VOX(ac)
AC differential cross point output
voltage
Max.
Unit
Note
—
1)
—
2)
V
3)
0.5 × VDDQ – 0.175
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.175
V
4)
0.5 × VDDQ – 0.125
0.5 × VDDQ + 0.125
V
5)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in
VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in
VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
1)
2)
3)
4)
VDDQ
VTR
Crossing Point
VID
VIX or VOX
VCP
VSSQ
SSTL18_3
Figure 65
Data Sheet
Differential DC and AC Input and Output Logic Levels Diagram
80
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.4
Output Buffer Characteristics
Table 31
SSTL_18 Output DC Current Drive
Symbol
IOH
IOL
Parameter
SSTL_18
Output Minimum Source DC Current
–13.4
Unit
Note
mA
1)2)
2)3)
Output Minimum Sink DC Current
13.4
mA
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and
VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability
to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 32
SSTL_18 Output AC Test Conditions
Symbol
Parameter
VOH
VOL
VOTR
SSTL_18
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Unit
Note
V
1)
V
1)
Output Timing Measurement Reference Level
V
1) SSTL_18 test load for VOH and VOL is different from the referenced load described in Chapter 8.1. The SSTL_18 test load
has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that
± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an
additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput
device (13.4 mA × 45 Ohm = 603 mV).
Table 33
OCD Default Characteristics
Symbol
Description
Min.
Nominal
Max.
Unit
Note
—
Output Impedance
12.6
18
23.4
Ohms
1)2)
—
Pull-up / Pull down mismatch
0
—
4
Ohms
1)2)3)
—
Output Impedance step size
for OCD calibration
0
—
1.5
Ohms
4)
1)5)6)7)8)
Output Slew Rate
1.5
—
5.0
V / ns
1) Absolute Specifications (TOPER; VDD = 1.8 V ± 0.1 V; VDDQ = 1.8 V ± 0.1 V), altering OCD from default state no longer
SOUT
2)
3)
4)
5)
6)
7)
8)
requires DRAM to meet timing, voltage and slew rate specifications on I/O’s.
Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance
measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms
for values of VOUT between 0 V and 280 mV.
Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
± 0.75 Ohms under nominal conditions.
Slew Rates according to Chapter 8.2.1 VIL(ac) to VIH(ac) with the load specified in Figure 72.
The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and
tQHS specification.
DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
Data Sheet
81
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.5
Full Strength Output V-I Characteristics
DDR2 SDRAM output driver characteristics are defined
for full strength default operation as selected by the
EMRS(1) bits A[9:7] =’111’. Figure 66 and Figure 67
Table 34
Voltage (V)
show the driver characteristics graphically and the
tables show the same data suitable for input into
simulation tools.
Full Strength Default Pull-up Driver Characteristics
Pull-up Driver Current [mA]
Min.1)
IBIS Target low2)
IBIS Target high2)
Max.3)
0.0
0.00
0.00
0.00
0.00
0.1
–4.30
–5.55
–5.90
–7.95
0.2
–8.6
–11.10
–11.8
–15.90
0.3
–12.9
–16.0
–17.0
–23.85
0.4
–16.9
–20.3
–22.2
–31.80
0.5
–20.05
–24.0
–27.5
–39.75
0.6
–22.10
–27.2
–32.4
–47.70
0.7
–23.27
–29.8
–36.9
–55.55
0.8
–24.10
–31.9
–40.8
–62.95
0.9
–24.73
–33.4
–44.5
–69.55
1.0
–25.23
–34.6
–47.7
–75.35
1.1
–25.65
–35.5
–50.4
–80.35
1.2
–26.02
–36.2
–52.5
–84.55
1.3
–26.35
–36.8
–54.2
–87.95
1.4
–26.65
–37.2
–55.9
–90.70
1.5
–26.93
–37.7
–57.1
–93.00
1.6
–27.20
–38.0
–58.4
–95.05
1.7
–27.46
–38.4
–59.6
–97.05
1.8
—
–38.6
–60.8
–99.05
1.9
—
—
—
–101.05
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow–slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast–fast process
Data Sheet
82
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
PY
0LQLPXP
,%,67DUJHW/RZ
,%,67DUJHW+LJK
0D[LPXP
CO
3X OOXSFX UUHQ W P$
Figure 66
Full Strength Default Pull-up Driver Diagram
Table 35
Full Strength Default Pull–down Driver Characteristics
Voltage (V)
E
9''4WR9287 9
Pull-down Driver Current [mA]
Min.1)
Nominal Default low2)
Nominal Default high2)
Max.3)
0.0
0.00
0.00
0.00
0.00
0.1
4.30
5.65
5.90
7.95
0.2
8.60
11.30
11.80
15.90
0.3
12.90
16.50
16.80
23.85
0.4
16.90
21.20
22.10
31.80
0.5
20.05
25.00
27.60
39.75
0.6
22.10
28.30
32.40
47.70
0.7
23.27
30.90
36.90
55.05
0.8
24.10
33.00
40.90
62.95
0.9
24.73
34.50
44.60
69.55
1.0
25.23
35.50
47.70
75.35
1.1
25.65
36.10
50.40
80.35
1.2
26.02
36.60
52.60
84.55
1.3
26.35
36.90
54.20
87.95
1.4
26.65
37.10
55.90
90.70
1.5
26.93
37.40
57.10
93.00
1.6
27.20
37.60
58.40
95.05
1.7
27.46
37.70
59.60
97.05
1.8
—
37.90
60.90
99.05
1.9
—
—
—
101.05
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow-slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast-fast process
Data Sheet
83
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
PY
CO
3XOOGR ZQFXUUHQ W P$
0LQLPXP
,%,67DUJHW/RZ
,%,67DUJHW+LJK
0D[LPXP
E
9287WR9664 9
Figure 67
Full Strength Default Pull–down Driver Diagram
5.5.1
Calibrated Output Driver V-I Characteristics
DDR2 SDRAM output driver characteristics are defined
for full strength calibrated operation as selected by the
procedure outlined in the Off-Chip Driver (OCD)
Impedance Adjustment. The Table 36 and Table 37
show the data in tabular format suitable for input into
simulation tools. The nominal points represent a device
at exactly 18 ohms. The nominal low and nominal high
values represent the range that can be achieved with a
maximum 1.5 ohms step size with no calibration error
at the exact nominal conditions only (i.e. perfect
calibration procedure, 1.5 ohm maximum step size
guaranteed by specification). Real system calibration
error needs to be added to these values. It must be
understood that these V-I curves are represented here
or in supplier IBIS models need to be adjusted to a
wider range as a result of any system calibration error.
Since this is a system specific phenomena, it cannot be
quantified here. The values in the calibrated tables
represent just the DRAM portion of uncertainty while
Data Sheet
looking at one DQ only. If the calibration procedure is
used, it is possible to cause the device to operate
outside the bounds of the default device characteristics
tables and figure. In such a situation, the timing
parameters in the specification cannot be guaranteed.
It is solely up to the system application to ensure that
the device is calibrated between the minimum and
maximum default values at all times. If this can’t be
guaranteed by the system calibration procedure, recalibration policy and uncertainty with DQ to DQ
variation, it is recommended that only the default
values to be used. The nominal maximum and
minimum values represent the change in impedance
from nominal LOW and HIGH as a result of voltage and
temperature change from the nominal condition to the
maximum and minimum conditions. If calibrated at an
extreme condition, the amount of variation could be as
much as from the nominal minimum to the nominal
maximum or vice versa.
84
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
Table 36
Voltage (V)
Full Strength Calibrated Pull-down Driver Characteristics
Calibrated Pull-down Driver Current [mA]
Nominal Minimum1)
(21 Ohms)
Nominal Low2)
(18.75 Ohms)
Nominal3)
(18 ohms)
Nominal High2) Nominal
(17.25 Ohms)
Maximum4)
(15 Ohms)
0.2
9.5
10.7
11.5
11.8
13.3
0.3
14.3
16.0
16.6
17.4
20.0
0.4
18.7
21.0
21.6
23.0
27.0
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any
process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Table 37
Voltage (V)
Full Strength Calibrated Pull-up Driver Characteristics
Calibrated Pull-up Driver Current [mA]
Nominal
Minimum1)
(21 Ohms)
Nominal Low2)
(18.75 Ohms)
Nominal
(18 ohms)3)
Nominal High2)
(17.25 Ohms)
Nominal
Maximum4)
(15 Ohms)
0.2
–9.5
–10.7
–11.4
–11.8
–13.3
0.3
–14.3
–16.0
–16.5
–17.4
–20.0
0.4
–18.3
–21.0
–21.2
–23.0
–27.0
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any
process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Data Sheet
85
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.6
Reduced Output Drive Characteristics
A driver mode with reduced output drive characteristics can be selected by setting address bit A1 in the EMRS(1)
extended mode register to 1.
Table 38
Voltage (V)
Reduced Strength Default Pull-up Driver Characteristics
Pull-up Driver Current [mA]
Min.1)
IBIS Target low2)
IBIS Target high2)
Max.3)
0.0
0.00
0.00
0.00
0.00
0.1
–1.72
–3.20
–3.70
–4.77
0.2
–3.44
–6.20
–7.22
–9.54
0.3
–5.16
–9.04
–10.56
–14.31
0.4
–6.76
–11.69
–13.75
–19.08
0.5
–8.02
–14.11
–16.78
–23.85
0.6
–8.84
–16.27
–19.61
–28.62
0.7
–9.31
–18.16
–22.20
–33.33
0.8
–9.64
–19.77
–24.50
–37.77
0.9
–9.89
–21.10
–26.46
–41.73
1.0
–10.09
–22.15
–28.07
–45.21
1.1
–10.26
–22.96
–29.36
–48.21
1.2
–10.41
–23.61
–30.40
–50.73
1.3
–10.54
–24.61
–31.24
–52.77
1.4
–10.66
–24.64
–31.93
–54.42
1.5
–10.77
–25.07
–32.51
–55.80
1.6
–10.88
–25.47
–33.01
–57.03
1.7
–10.98
–25.85
–33.46
–58.23
1.8
—
–26.21
–33.89
–59.43
1.9
—
—
—
–60.63
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow–slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast–fast process
Data Sheet
86
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
0,00
PY
-40,00
CO
Pull-up Current (mA)
-20,00
-60,00
Minimum
IBIS Target Low
IBIS Target High
Maximum
0
0,2
0,4
0,6
0,8
1
SE
-80,00
1,2
1,4
1,6
1,8
2
VDDQ to VOUT (V)
Figure 68
Reduced Strength Default Pull-up Driver Diagram
Table 39
Reduced Strength Default Pull–down Driver Characteristics
Voltage (V)
Pull-down Driver Current [mA]
Min.1)
IBIS Target low2)
IBIS Target high2)
Max.3)
0.0
0.00
0.00
0.00
0.00
0.1
1.72
3.24
4.11
4.77
0.2
3.44
6.25
8.01
9.54
0.3
5.16
9.03
11.67
14.31
0.4
6.76
11.52
15.03
19.08
0.5
8.02
13.66
18.03
23.85
0.6
8.84
15.41
20.61
28.62
0.7
9.31
16.77
22.71
33.33
0.8
9.64
17.74
24.35
37.77
0.9
9.89
18.83
25.56
41.73
1.0
10.09
18.80
26.38
45.21
1.1
10.26
19.06
26.90
48.21
1.2
10.41
19.23
27.24
50.73
1.3
10.54
19.35
27.47
52.77
1.4
10.66
19.46
27.64
54.42
1.5
10.77
19.56
27.78
55.80
1.6
10.88
19.65
27.89
57.03
1.7
10.98
19.73
27.97
58.23
1.8
—
19.80
28.02
59.43
1.9
—
—
—
60.63
1) The driver characteristics evaluation conditions are Minimum 95 °C (TCASE), VDDQ = 1.7 V, slow-slow process
2) The driver characteristics evaluation conditions are Nominal Default 25 °C (TCASE), VDDQ = 1.8 V, typical process
3) The driver characteristics evaluation conditions are Maximum 0 °C (TCASE). VDDQ = 1.9 V, fast-fast process
Data Sheet
87
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
80
80
70
70
PY
Pull-Down Current (mA)
Pull-Down Current (mA)
60
60
Minimum
Minimum
Nominal
Default Low
NoIBIS Target Low
IBIS Target High
Maximum
Maximum
50
50
40
40
CO
30
30
20
20
10
10
0
0
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
2
0,2 0,4 0,6 0,8
1
1,2 1,4 1,6 1,8
2
SE
0
0
VOUT to VSSQ (V)
VOUT to VSSQ (V)
Figure 69
Reduced Strength Default Pull–down Driver Diagram
5.7
Input / Output Capacitance
Table 40
Input / Output Capacitance
Symbol
Parameter
DDR2-400 &
DDR-2-533
DDR2-667
Min.
Max.
Min.
Unit
Max.
CCK
Input capacitance, CK and CK
1.0
2.0
1.0
2.0
pF
CDCK
Input capacitance delta, CK and CK
—
0.25
—
0.25
pF
CI
Input capacitance, all other input-only pins
1.0
2.0
1.0
2.0
pF
CDI
Input capacitance delta, all other input-only pins
—
0.25
—
0.25
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS, RDQS, RDQS
2.5
4.0
2.5
3.5
pF
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS, RDQS, RDQS
—
0.5
—
0.5
pF
Data Sheet
88
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
5.8
Power & Ground Clamp V-I Characteristics
Power and Ground clamps are provided on address
(A[13:0], BA[11:0]), RAS, CAS, CS, WE, and ODT pins.
Table 41
The V-I characteristics for pins with clamps is shown in
Table 41.
Power & Ground Clamp V-I Characteristics
Voltage across clamp (V)
Minimum Power Clamp
Current (mA)
Minimum Ground Clamp Current (mA)
0.0
0
0
0.1
0
0
0.2
0
0
0.3
0
0
0.4
0
0
0.5
0
0
0.6
0
0
0.7
0
0
0.8
0.1
0.1
0.9
1.0
1.0
1.0
2.5
2.5
1.1
4.7
4.7
1.2
6.8
6.8
1.3
9.1
9.1
1.4
11.0
11.0
1.5
13.5
13.5
1.6
16.0
16.0
1.7
18.2
18.2
1.8
21.0
21.0
5.9
Overshoot and Undershoot Specification
Table 42
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2-400
DDR2-533
DD2-667
Unit
Maximum peak amplitude allowed for overshoot area 0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area 0.9
0.9
0.9
V
Maximum overshoot area above VDD
1.33
1.00
0.80
V.ns
Maximum undershoot area below VSS
1.33
1.00
0.80
V.ns
Data Sheet
89
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC & DC Operating Conditions
Maximum Amplitude
Volts (V)
Overshoot Area
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 70
AC Overshoot / Undershoot Diagram for Address and Control Pins
Table 43
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
DDR2-533
DD2-667
Unit
Maximum peak amplitude allowed for overshoot area 0.9
DDR2-400
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area 0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
0.38
0.28
0.23
V.ns
Maximum undershoot area below VSSQ
0.38
0.28
0.23
V.ns
Maximum Amplitude
Volts (V)
Overshoot Area
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 71
Data Sheet
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
90
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6
Currents Measurement Specifications and Conditions
Table 44
IDD Measurement Conditions
Parameter
Symbol Note
Operating Current One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are switching; Databus inputs are switching.
IDD0
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0,
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
IDD1
1)2)3)4)5)6)
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data
bus inputs are floating.
1)2)3)4)5)6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
switching, Data bus inputs are switching.
1)2)3)4)5)6)
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
1)2)3)4)5)6)
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
1)2)3)4)5)6)
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
1)2)3)4)5)6)
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands. Address inputs are switching; Data Bus inputs are switching;
IDD3N
1)2)3)4)5)6)
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD);
tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA.
IDD4R
1)2)3)4)5)6)
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD);
tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
IDD4W
1)2)3)4)5)6)
Burst Refresh Current
IDD5B
tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
1)2)3)4)5)6)
Distributed Refresh Current
IDD5D
tCK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
1)2)3)4)5)6)
Data Sheet
91
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
Table 44
IDD Measurement Conditions
Parameter
Symbol Note
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
floating, Data bus inputs are floating.
IDD6
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern:
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-533-444: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4)
5)
6)
7)
1)2)3)4)5)6)
1)2)3)4)5)6)7)
Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD: see Table 2
Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Table 45
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
defined as inputs are stable at a HIGH or LOW level
FLOATING
defined as inputs are VREF = VDDQ / 2
SWITCHING
defined as: Inputs are changing between high and low every other clock (once per two clocks)
for address and control signals, and inputs changing between high and low every other clock
(once per clock) for DQ signals not including mask or strobes
Data Sheet
92
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
Table 46
IDD Specification for DDR2–667C and DDR2-667D
Product Type Speed Code
–3
–3S
Speed Grade
DDR2–667C
DDR2–667D
Symbol
Max.
Max.
IDD0
75
71
95
90
90
85
110
104
50
50
mA
5
5
mA
40
40
mA
50
50
mA
19
19
mA
1)
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1)
2)
3)
4)
Unit
Note
mA
×4/×8
×16
mA
×4/×8
×16
×4/×8
×16
6
6
mA
2)
130
130
mA
×4/×8
150
150
mA
×16
140
140
mA
×4/×8
170
170
mA
×16
140
140
mA
3)
6
6
mA
3)
5
5
mA
3)4)
155
147
mA
×4/×8
240
228
mA
×16
MRS(12)=0
MRS(12)=1
0 ≤ TCASE ≤ 85 °C
standard products
Data Sheet
93
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
Table 47
IDD Specification for DDR2–533C and DDR2–400B
Product Type Speed Code
–3.7
–5
Speed Grade
DDR2–533C
DDR2–400B
Symbol
Max.
Max.
IDD0
65
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1)
2)
3)
4)
Unit
Note
55
mA
×4/×8
80
70
mA
×16
75
60
mA
×4/×8
90
75
mA
×16
40
32
mA
4
4
mA
30
25
mA
40
35
mA
16
13
mA
1)
×4/×8
×16
5
5
mA
2)
90
70
mA
×4/×8
100
85
mA
×16
×4/×8
95
75
mA
110
90
mA
×16
130
120
mA
3)
6
6
mA
3)
4
4
mA
3)4)
140
130
mA
×4/×8
220
210
mA
×16
MRS(12)=0
MRS(12)=1
0 ≤ TCASE ≤ 85 °C
standard products
Data Sheet
94
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
Table 48
IDD Measurement Test Conditions for DDR2–667C and DDR2–667D
Parameter
Symbol
–3
–3S
Unit
Note
CAS Latency
CL(IDD)
4
5
tCK
Clock Cycle Time
tCK(IDD)
tRCD(IDD)
tRC(IDD)
3
3
ns
12
15
ns
57
60
ns
7.5
7.5
ns
1)
10
10
ns
2)
45
45
ns
70000
70000
ns
12
15
ns
75
75
ns
105
105
ns
7.8
7.8
µs
DDR2–667C 4–4–4 DDR2–667D 5–5–5
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
tRRD(IDD)
tRRD(IDD)
Active to Precharge Command
tRAS.MIN(IDD)
tRAS.MAX(IDD)
Precharge Command Period
tRP(IDD)
Auto-Refresh to Active / Auto-Refresh tRFC(IDD)
Active bank A to Active bank B
command delay
command period
Auto-Refresh to Active / Auto-Refresh tRFC(IDD)
command period
tREFI
Average periodic Refresh interval
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size); not on 256M component
Table 49
IDD Measurement Test Condition for DDR2–533C and DDR2–400B
Parameter
Symbol
–3.7
–5
Unit
Note
DDR2–533C 4–4–4 DDR2–400B 3–3–3
CAS Latency
CL(IDD)
4
3
tCK
Clock Cycle Time
tCK(IDD)
tRCD(IDD)
tRC(IDD)
3.75
5
ns
15
15
ns
60
55
ns
Active bank A to Active bank B
command delay
tRRD(IDD)
7.5
7.5
ns
1)
10
10
ns
2)
Active to Precharge Command
tRAS.MIN(IDD)
tRAS.MAX(IDD)
tRP(IDD)
tRFC(IDD)
45
40
ns
70000
70000
ns
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
Precharge Command Period
Auto-Refresh to Active / AutoRefresh command period
Average periodic Refresh interval tREFI
15
15
ns
105
105
ns
7.8
7.8
µs
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size); not on 256M component
Data Sheet
95
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6.1.1
On Die Termination (ODT) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a
full or reduced termination can be selected. The current
Table 50
consumption for any terminated input pin depends on
whether the input pin is in tri-state or driving “0” or “1”,
as long a ODT is enabled during a given period of time..
See Table 50
ODT current per terminated input pin
ODT Current
Enabled ODT current per DQadded IDDQ
current for ODT enabled;
ODT is HIGH; Data Bus inputs are floating
IODTO
Active ODT current per DQadded IDDQ current IODTT
for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs are
stable or switching.
EMRS(1) State
Min.
Typ.
Max.
Unit
A6 = 0, A2 = 1
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
2.5
3
3.75
mA/DQ
A6 = 1, A2 = 1
7.5
9
11.25
mA/DQ
A6 = 0, A2 = 1
10
12
15
mA/DQ
A6 = 1, A2 = 0
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
15
18
22.5
mA/DQ
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
96
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
7
Electrical Characteristics
7.1
Speed Grade Defenitions
Table 51
Speed Grade Definition Speed Bins for DDR667
Speed Grade
DDR2–667C
DDR2–667D
IFX Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
1)2)3)4)
3
8
3
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57
—
60
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
Table 52
Speed Grade Definition Speed Bins for DDR533 and DDR400
Speed Grade
DDR2–533C
DDR2–400B
IFX Sort Name
–3.7
–5
CAS-RCD-RP latencies
4–4–4
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Data Sheet
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
45
70000
40
70000
ns
1)2)3)4)5)
60
—
55
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
97
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
7.2
AC Timing Parameters
Table 53
Timing Parameter by Speed Grade - DDR2-667
Parameter
Symbol
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data Sheet
98
Unit
Note
1)2)3)4)5)6)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
tDELAY
–450
+450
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tIS + tCK + tIH ––
ns
8)
tDH(base)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
tDQSS
tDS(base)
tDSH
tDSS
tHP
tHZ
tIH(base)
tIPW
175
––
ps
9)
0.35
—
tCK
–400
+400
ps
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
Address and control input setup time
DDR2-667
0.35
—
tCK
240
—
ps
– 0.25
+ 0.25
tCK
100
—
ps
0.2
—
0.2
—
tCK
tCK
7)
10)
9)
11)
MIN. (tCL, tCH)
—
tAC.MAX
ps
12)
275
—
ps
9)
0.6
—
tCK
200
—
ps
9)
2 x tAC.MIN
ps
12)
tAC.MIN
tAC.MAX
tAC.MAX
ps
12)
2
—
tCK
0
12
ns
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 53
Timing Parameter by Speed Grade - DDR2-667
Parameter
Symbol
DDR2-667
Unit
Note
1)2)3)4)5)6)
Min.
Max.
tHP – tQHS
—
340
—
ps
—
7.8
µs
13)14)
—
3.9
µs
13)15)
105
—
ns
1)
0.9
1.1
12)
0.40
0.60
tCK
tCK
7.5
—
ns
16)17)
10
—
ns
17)18)
7.5
—
ns
0.35
—
0.40
0.60
tCK
tCK
Write recovery time for write without Auto-Precharge
tRTP
tWPRE
tWPST
tWR
15
—
ns
Write recovery time for write with Auto-Precharge
WR
tWR/tCK
Internal Write to Read command delay
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
tXARDS
7 – AL
—
tCK
21)
2
—
tCK
tRFC +10
—
ns
200
—
tCK
tQH
tQHS
tREFI
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tRFC
tRPRE
tRPST
tRRD
Auto-Refresh to Active/Auto-Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command (other tXP
than NOP or Deselect)
tXSNR
tXSRD
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
12)
19)
tCK
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
3)4)5)6)
Data Sheet
99
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
14) 0 ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) x4 & x8 (1k page size)
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
18) x16 (2k page size), not on 256Mbit component
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Data Sheet
100
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 54
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C
Parameter
Symbol
DDR2–533C
DDR2–400B
Unit Note
1)2)3)4)5)
Min.
Max.
Min.
Max.
–500
+500
–600
+600
ps
CAS A to CAS B command period tCCD
2
—
2
—
tCH
CKE minimum high and low pulse tCKE
0.45
0.55
0.45
0.55
3
—
3
—
tCK
tCK
tCK
tCL
tDAL
0.45
0.55
0.45
0.55
WR + tRP
—
WR + tRP
—
tCK
tCK
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK +
tIH
––
tIS + tCK +
tIH
—
ns
8)
DQ and DM input hold time
(differential data strobe)
tDH(base) 225
––
275
––
ps
9)
DQ and DM input hold time (single tDH1(base) –25
ended data strobe)
—
25
—
ps
9)
DQ and DM input pulse width (each tDIPW
input)
0.35
—
0.35
—
tCK
DQS output access time from CK / tDQSCK
CK
–450
+450
–500
+500
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
300
—
350
ps
Write command to 1st DQS
latching transition
tDQSS
WL – 0.25
WL + 0.25 WL – 0.25
WL + 0.25 tCK
DQ and DM input setup time
(differential data strobe)
tDS(base) 100
—
150
—
ps
9)
DQ and DM input setup time
(single ended data strobe)
tDS1(base) –25
—
25
—
ps
9)
DQS falling edge hold time from
CK (write cycle)
tDSH
0.2
—
0.2
—
tCK
DQS falling edge to CK setup time tDSS
(write cycle)
0.2
—
0.2
—
tCK
DQ output access time from CK /
CK
tAC
CK, CK high-level width
6)
width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Clock half period
Data-out high-impedance time
from CK / CK
tHP
tHZ
Address and control input hold time tIH(base)
Address and control input pulse
width
(each input)
Data Sheet
tIPW
MIN. (tCL, tCH)
7)
10)
11)
MIN. (tCL, tCH)
—
tAC.MAX
—
tAC.MAX
ps
12)
375
—
475
—
ps
9)
0.6
—
0.6
—
tCK
101
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 54
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d)
Parameter
Symbol
DDR2–533C
DDR2–400B
Unit Note
1)2)3)4)5)
Min.
Max.
Min.
Max.
250
—
350
—
ps
9)
DQ low-impedance time from CK / tLZ(DQ)
CK
2 x tAC.MIN
tAC.MAX
2 x tAC.MIN
tAC.MAX
ps
12)
DQS low-impedance from CK / CK tLZ(DQS)
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
12)
Address and control input setup
time
tIS(base)
6)
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
OCD drive mode output delay
tOIT
tQH
tQHS
tREFI
0
12
0
12
ns
tHP – tQHS
—
tHPQ – tQHS —
—
400
—
450
ps
—
7.8
—
7.8
µs
13)14)
—
3.9
—
3.9
µs
13)15)
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/AutoRefresh command period
tRFC
105
—
105
—
ns
1)
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
12)
0.40
0.60
0.40
0.60
tCK
tCK
7.5
—
7.5
—
ns
16)17)
10
—
10
—
ns
18)17)
Read postamble
Active bank A to Active bank B
command period
12)
Internal Read to Precharge
command delay
tRTP
7.5
—
7.5
—
ns
Write preamble
tWPRE
tWPST
tWR
0.35xtCK
—
0.35xtCK
—
0.40
0.60
0.40
0.60
tCK
tCK
15
—
15
—
ns
Write recovery time for write with
Auto-Precharge
WR
tWR/tCK
Internal Write to Read command
delay
tWTR
7.5
—
10
—
ns
20)
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
2
—
2
—
tCK
21)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
6 – AL
—
6 – AL
—
tCK
21)
2
—
2
—
tCK
Write postamble
Write recovery time for write
without Auto-Precharge
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
tWR/tCK
tCK
Exit Self-Refresh to non-Read
command
tXSNR
tRFC +10
—
tRFC +10
—
ns
Exit Self-Refresh to Read
command
tXSRD
200
—
200
—
tCK
1)
19)
VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
Data Sheet
102
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows
as valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
14) 0 ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) x4 & x8 (1k page size)
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
18) x16 (2k page size), not on 256 Mbit component
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Data Sheet
103
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512-Mbit DDR2 SDRAM
Electrical Characteristics
7.3
ODT AC Electrical Characteristics
Table 55
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667
Symbol
Parameter / Condition
Values
Unit
Min.
Max.
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT turn-on delay
2
2
ODT turn-on
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MAX + 0.7 ns
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
ODT turn-off delay
2.5
tCK
Note
tCK
2.5
1)
ns
tAC.MIN
tAC.MAX + 0.6 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
ODT to Power Down Mode Entry Latency 3
—
tCK
ODT Power Down Exit Latency
8
—
tCK
ODT turn-off
2)
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
Table 56
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
ODT turn-on
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MAX + 1 ns
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
ns
ODT turn-off delay
2.5
tCK
2.5
tCK
ns
tAC.MIN
tAC.MAX + 0.6 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
ODT to Power Down Mode Entry Latency 3
—
tCK
ODT Power Down Exit Latency
8
—
tCK
ODT turn-off
Note
1)
2)
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
Data Sheet
104
Rev. 1.3, 2005-01
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8
AC Timing Measurement Conditions
8.1
Reference Load for Timing Measurements
Figure 72 represents the timing reference load used in
defining the relevant timing parameters of the device. It
is not intended to either a precise representation of the
typical system environment nor a depiction of the actual
load presented by a production tester. System
designers should use IBIS or other simulation tools to
correlate the timing reference load to a system
environment. Manufacturers correlate to their
production test conditions, generally a coaxial
transmission line terminated at the tester electronics.
This reference load is also used for output Slew Rate
characterization. The output timing reference voltage
level for single ended signals is the crosspoint with VTT.
The output timing reference voltage level for differential
signals is the crosspoint of the true (e.g. DQS) and the
complement (e.g. DQS) signal.
VDDQ
CK, CK
DUT
DQ
DQS
DQS
RDQS
RDQS
25 Ohm
VTT = VDDQ / 2
Timing Reference Points
Figure 72
Reference Load for Timing Measurements
8.2
Slew Rate Measurement Conditions
8.2.1
Output Slew Rate
For DQ and single ended DQS signals output Slew
Rate for falling and rising edges is measured between
VTT – 250 mV and VTT + 250 mV.
For differential signals (DQS / DQS) output Slew Rate
is measured between DQS - DQS = –500 mV and
8.2.2
Input Slew Rate - Differential signals
Input Slew Rate for differential signals (CK / CK, DQS /
DQS, RDQS / RDQS) for rising edges are measured
from CK - CK = –250 mV to CK – CK = +500 mV and
Data Sheet
DQS – DQS = + 500 mV. Output Slew Rate is defined
with the reference load according to Figure 72 and
verified by design and characterization, but not subject
to production test.
from CK – CK = +250 mV to CK – CK = –500mV for
falling edges.
105
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512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3
Input and Data Setup and Hold Time
8.3.1
Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (tIS) is referenced
from the input signal crossing at the VIH(ac) level for a
rising signal and VIL(ac) for a falling signal applied to the
device under test. Address and control input hold time
(tIH) is referenced from the input signal crossing at the
VIL(dc) level for a rising signal and VIH(dc) for a falling
signal applied to the device under test.
CK
CK
t
t
IS
t
IH
IS
t
IH
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
Figure 73
Input Setup and Hold Time
8.3.2
Definition for Data Setup (tDS) and Hold Time (tDH), differential Data Strobes
Data input setup time (tDS) with differential data strobe
enabled MR[bit10]=0, is referenced from the input
signal crossing at the VIH(ac) level to the differential data
strobe crosspoint for a rising signal, and from the input
signal crossing at the VIL(ac) level to the differential data
strobe crosspoint for a falling signal applied to the
device under test.
differential data strobe enabled MR[bit10]=0, is
referenced from the input signal crossing at the VIL(dc)
level to the differential data strobe crosspoint for a
rising signal and VIH(dc) to the differential data strobe
crosspoint for a falling signal applied to the device
under test.
DQS/DQS signals must be monotonic between
VIL(dc).MAX and VIH(dc).MIN. Data input hold time (tDH) with
VIL(dc).MAX and VIH(dc).MIN.
DQS/DQS signals must be monotonic between
DQS
DQS
t
DS
t
DH
t
t
DS DH
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc)
max
VIL(ac)
max
VSS
Figure 74
Data Sheet
Data Setup and Hold Time (Differential Data Strobes)
106
Rev. 1.3, 2005-01
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.3
Definition Data Setup (tDS1) and Hold Time (tDH1), Single-Ended Data Strobes
Data input setup time (tDS1) with single-ended data
strobe enabled MR[bit10]=1, is referenced from the
input signal crossing at the VIH(ac) level to the singleended data strobe crossing VIH/L(dc) at the start of its
transition for a rising signal, and from the input signal
crossing at the VIL(ac) level to the single-ended data
strobe crossing VIH/L(dc) at the start of its transition for a
falling signal applied to the device under test.
input signal crossing at the VIH(dc) level to the singleended data strobe crossing VIH/L(ac) at the end of its
transition for a rising signal and from the input signal
crossing at the VIL(dc) level to the single-ended data
strobe crossing VIH/L(ac) at the end of its transition for a
falling signal applied to the device under test.
The DQS signal must be monotonic between VIL(dc.MAX
and VIH(dc).MIN.
Data input hold time (tDH1) with single-ended data
strobe enabled MR[bit10]=1, is referenced from the
VDDQ
VIH(ac) min
VIH(dc) min
VREF
DQS
VIL(dc)
max
VIL(ac)
max
VSS
t
DS
t
t
DH
DS
t
DH
VDDQ
VIH(ac) min
VIH(dc) min
VREF
DQ
VIL(dc)
max
VIL(ac)
max
VSS
Figure 75
Data Sheet
Data Setup and Hold Time (Single Ended Data Strobes)
107
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09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.4
Slew Rate Definition for Input and Data Setup and Hold Times
Setup (tIS & tDS) nominal Slew Rate for a rising signal is
defined as the Slew Rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac).MIN. Setup (tIS &
tDS) nominal Slew Rate for a falling signal is defined as
the Slew Rate between the last crossing of VREF(dc) and
the first crossing of VIL(ac).MAX. If the actual signal is
always earlier than the nominal Slew Rate line between
shaded ‘VREF(dc) to ac region’, use nominal Slew Rate
for derating value (see Figure 76). If the actual signal
is later than the nominal Slew Rate line anywhere
between shaded ‘VREF(dc) to ac region’, the Slew Rate of
a tangent line to the actual signal from the ac level to dc
level is used for derating value.(see Figure 77) Hold
(tIH & tDH) nominal Slew Rate for a rising signal is
defined as the Slew Rate between the last crossing of
VIL(dc).MAX and the first crossing of VREF(dc). Hold (tIH &
tDH) nominal Slew Rate for a falling signal is defined as
the Slew Rate between the last crossing of VIH(dc).MIN
and the first crossing of VREF(dc). If the actual signal is
always later than the nominal Slew Rate line between
shaded ‘dc to VREF region’, use nominal Slew Rate for
derating value (see Figure 76). If the actual signal is
earlier than the actual signal from the dc level to VREF
level is used for derating value (see Figure 77)
#+ #+ FOR T)3 AND T)(
$13 $13 FOR T$3 AND T$(
T)3
T$3
T)(
T$(
T)3
T$3
T)(
T$(
6 $$1
6)(AC MIN
62%& TO AC
REGION
6)(DC MIN
DC TO 62%&
REGION
62%&
DC TO 62%&
REGION
62%& TO AC
REGION
6),DC
MAX
6),AC
MAX
633
$ELTA 4&3
$ELTA 42( $ELTA 423
3ETUP 3LEW 2ATE 3ETUP 3LEW 2ATE Figure 76
Data Sheet
(OLD 3LEW 2ATE
(OLD 3LEW 2ATE
62%&DC
$ELTA 4&(
6),AC MAX
$ELTA 4&3
6)(AC MIN 62%&DC
$ELTA 423
62%&DC
6),DC MAX
$ELTA 42(
6)(DC MIN 62%&DC
$ELTA 4&(
FALLING SIGNAL
RISING SIGNAL
RISING SIGNAL
FALLING SIGNAL
Slew Rate Definition Nominal
108
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09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
#+ #+ FOR T)3 AND T)(
$13 $13 FOR T$3 AND T$(
T)3
T$3
T)(
T$(
T)3 T)(
T$3 T$(
6$$1
6)(AC MIN
62%& TO AC
REGION
6)(DC MIN
DC TO 6REF
REGION
62%&
DC TO 6REF
REGION
62%& TO AC
REGION
6),DC
MAX
6),AC
MAX
633
$ELTA 4&3
$ELTA 42(
$ELTA 423
$ELTA 4&(
TANGENT LINE
NOMINAL LINE
3ETUP 3LEW 2ATE 3ETUP 3LEW 2ATE Figure 77
Data Sheet
(OLD 3LEW 2ATE
(OLD 3LEW 2ATE
TANGENT LINE ;62%&DC
6),AC MAX=
FALLING
SIGNAL
TANGENT LINE ;6)(AC MIN 62%&DC =
RISING
SIGNAL
$ELTA 4&3
$ELTA 423
6),DC MAX=
RISING
SIGNAL
TANGENT LINE ;6)(DC MIN 62%&DC =
FALLING
SIGNAL
TANGENT LINE ;62%&DC
$ELTA 42(
$ELTA 4&(
Slew Rate Definition Tangent
109
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.5
Setup (tIS) and Hold (tIH) Time Derating Tables
1. For all input signals the total input setup time and
input hold time required is calculated by adding the
data sheet value to the derating value respectively.
Example: tIS(total setup tine) = tIS(base) + ∆ tIS
2. For slow Slew Rate the total setup time might be
negative (i.e. a valid input signal will not have
reached VIH(ac) / VIL(ac) at the time of the rising clock)
Table 57
a valid input signal is still required to complete the
transition and reach VIH(ac) / VIL(ac). For Slew Rates
in between the values listed in the next tables, the
derating values may be obtained by linear
interpolation. These values are not subject to
production test. They are verified only by design
and characterization.
Derating Values for Input Setup and Hold Time (DDR2-667)
Command / Address Slew Rate
(V/ns)
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
Unit
Note
1.0 V/ns
∆ tIS
∆ tIH
∆ tIS
∆ tIH
∆ tIS
∆ tIH
4.0
+150
+94
+180
+124
+210
+154
ps
1)2)
3.5
+143
+89
+173
+119
+203
+149
ps
1)
3.0
+133
+83
+163
+113
+193
+143
ps
1)
2.5
+120
+75
+150
+105
+180
+135
ps
1)
2.0
+100
+45
+130
+75
+160
+105
ps
1)
1.5
+67
+21
+97
+51
+127
+81
ps
1)
1.0
0
0
+30
+30
+60
+60
ps
1)
0.9
–5
–14
+25
+16
+55
+46
ps
1)
0.8
–13
–31
+17
–1
+47
+29
ps
1)
0.7
–22
–54
+8
–24
+38
+6
ps
1)
0.6
–34
–83
–4
–53
+26
–23
ps
1)
0.5
–60
–125
–30
–95
0
–65
ps
1)
0.4
–100
–188
–70
–158
–40
–128
ps
1)
0.3
–168
–292
–138
–262
–108
–232
ps
1)
0.25
–200
–375
–170
–345
–140
–315
ps
1)
0.2
–325
–500
–295
–470
–265
–440
ps
1)
0.15
–517
–708
–487
–678
–457
–648
ps
1)
–940
–1065
ps
1)
0.1
–1000
–1125
–970
–1095
1) For all input signals tIS(total) = tIS(base) + ∆tIS and tIH(total) = tIH(base) + ∆tIH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
Data Sheet
110
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Table 58
Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533)
Command / Address Slew Rate
(V/ns)
CK, CK Differential Slew Rate
2.0 V/ns
1.5 V/ns
Unit
Note
1.0 V/ns
∆ tIS
∆ tIH
∆ tIS
∆ tIH
∆ tIS
∆ tIH
4.0
+187
+94
+217
+124
+247
+154
ps
1)2)
3.5
+179
+89
+209
+119
+239
+149
ps
1)
3.0
+167
+83
+197
+113
+227
+143
ps
1)
2.5
+150
+75
+180
+105
+210
+135
ps
1)
2.0
+125
+45
+155
+75
+185
+105
ps
1)
1.5
+83
+21
+113
+51
+143
+81
ps
1)
1.0
0
0
+30
+30
+60
+60
ps
1)
0.9
–11
–14
+19
+16
+49
+46
ps
1)
0.8
–25
–31
+5
–1
+35
+29
ps
1)
0.7
–43
–54
–13
–24
+17
+6
ps
1)
0.6
–67
–83
–37
–53
–7
–23
ps
1)
0.5
–110
–125
–80
–95
–50
–65
ps
1)
0.4
–175
–188
–145
–158
–115
–128
ps
1)
0.3
–285
–292
–255
–262
–225
–232
ps
1)
0.25
–350
–375
–320
–345
–290
–315
ps
1)
0.2
–525
–500
–495
–470
–465
–440
ps
1)
0.15
–800
–708
–770
–678
–740
–648
ps
1)
–1390
–1065
ps
1)
0.1
–1450
–1125
–1420
–1095
1) For all input signals tIS(total) = tIS(base) + ∆tIS and tIH(total) = tIH(base) + ∆tIH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached VIH(ac) / VIL(ac) at the
time of the rising clock) a valid signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
Data Sheet
111
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667)
DQ Slew Rate (V/ns)
Table 59
DQS, DQS Differential Slew Rate1)2)
2.0
+100 +45 +100 +45 +100 +45 —
1.5
+67
+21 +67
1.0
0
0
0.9
—
0.8
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
1.0 V/ns
0.8 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS
tDH tDS
tDH
tDS
tDH
tDS
tDH
∆
tDH tDS
∆
∆
∆
∆
∆
∆
∆
tDH tDS tDH tDS tDH tDS tDH tDS
—
—
—
—
—
—
—
—
—
—
+21 +67
+21 +97 +33 —
—
—
—
—
—
—
—
—
—
0
0
0
+12 +12 +24 +24 —
—
—
—
—
—
—
—
—
–5
–14 –5
–14 +7
–2
+19 +10 +31 +22 —
—
—
—
—
—
—
—
—
—
–13
–31 –1
–19 +11 –7
+17
—
—
—
—
0.7
—
—
—
—
—
—
–10 –42 +2
—
0.6
—
—
—
—
—
—
—
—
–10 –59 +2
0.5
—
—
—
—
—
—
—
—
—
0.4
—
—
—
—
—
—
—
—
—
0
—
+23 +5
+35
–30 +14 –18 +26
–6
+38
+6
—
–47 +14
–35
+26
–23
+538 –11
—
–24 –89 –12
–77
0
–65
+12
–53
—
—
–140 –20
–28
–28
–116
—
–52
1) All units in ps.
2) For all input signals tDS(total) = tDS(base) + ∆tDS and tDH(total) = tDH(base) + ∆tDH
Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533)
DQ Slew Rate (V/ns)
Table 60
DQS, DQS Differential Slew Rate1)2)
2.0
+125 +45 +125 +45 +125 +45 —
1.5
+83
+21 +83
1.0
0
0
0
0.9
—
—
–11
–14 –11
–14 +1
0.8
—
—
—
—
–25
–31 –13 –19 –1
0.7
—
—
—
—
—
—
–31 –42 –19 –30 –7
0.6
—
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
0.4
—
—
—
—
—
—
—
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
1.0 V/ns
0.8 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS
tDH tDS
tDH
tDS
tDH
tDS
tDH
∆
tDH tDS
∆
∆
∆
∆
∆
∆
∆
tDH tDS tDH tDS tDH tDS tDH tDS
—
—
—
—
—
—
—
—
—
—
+21 +83
+21 +95 +33 —
—
—
—
—
—
—
—
—
—
0
0
+12 +12 +24 +24 —
—
—
—
—
—
—
—
+13 +10 +25 +22 —
—
—
—
—
—
+17
—
—
—
—
–6
+17
+6
—
—
–43 –59 –31 –47 –19
–35
–7
–23
+5
–11
—
—
—
–74 –89 –62
–77
–50
–65
–38
–53
—
—
—
—
0
—
–2
–7
+11 +5
+23
–18 +5
—
–127 –140 –115 –128 –103 –116
1) All units in ps.
2) For all input signals tDS(total) = tDS(base) + ∆tDS and tDH(total) = tDH(base) + ∆tDH
Data Sheet
112
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
DQ Slew Rate (V/ns)
Table 61
Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533)
DQS, DQS Single-ended Slew Rate1)2)
2.0 V/ns
1.5 V/ns
1.0 V/ns
0.9 V/ns 0.8 V/ns 0.7 V/ns
0.6 V/ns
0.5 V/ns
0.4 V/ns
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
tDS1
tDH1
tDS1
tDH1
tDS1
tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1
2.0 +188 +188 +167 +146 +125 +63 —
∆
∆
∆
∆
∆
∆
∆
—
—
—
—
—
—
—
—
—
—
1.5 +146 +167 +125 +125 +83
+42 +81 +43 —
—
—
—
—
—
—
—
—
—
1.0 +63
+125 +42
+83
0
0
-13 —
—
—
—
—
—
—
—
0.9 —
—
+31
+69
-11
-14 -13 -13 -18 -27 -29
-45
—
—
—
—
—
—
0.8 —
—
—
—
-25
-31 -27 -30 -32 -44 -43
-62
-60
–86 —
—
—
—
0.7 —
—
—
—
—
—
-45 -53 -50 -67 -61
-85
-78
-109 -108 -152 —
—
0.6 —
—
—
—
—
—
—
—
-74 -96 -85
-114 -102 -138 -132 -181 -183 -246
0.5 —
—
—
—
—
—
—
—
—
—
-128 -156 -145 -180 -175 -223 -226 -288
0.4 —
—
—
—
—
—
—
—
—
—
—
-2
—
∆
+1
-7
—
-210 -243 -240 -286 -291 -351
1) All units in ps.
2) For all input signals tDS1(total) = tDS1(base) + ∆tDS1 and tDH1(total) = tDH1(base) + ∆tDH1
Data Sheet
113
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Package Dimensions
9
Package Dimensions
X !
X -!8
"
-!8
#
-!8
Figure 78
Data Sheet
-).
#
’ ›
X
! "
’ #
’ -
# 3%!4).' 0,!.%
$UMMY PADS WITHOUT BALL
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
"AD UNIT MARKING "5$IE SORT FIDUCIAL
Package Pinout PG-TFBGA-60 (top view)
114
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Package Dimensions
X !
X -!8
"
-!8
#
Figure 79
Data Sheet
-).
-!8
#
’ ›
X
’ ! "
#
’ -
# 3%!4).' 0,!.%
$UMMY PADS WITHOUT BALL
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
"AD UNIT MARKING "5$IE SORT FIDUCIAL
Package Pinout PG-TFBGA-84 (top view)
115
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Product Namenclature
10
Product Namenclature
Table 62
Nomenclature Fields and Examples
Example for
Field Number
DDR2 DRAM
1
2
3
4
5
HYB
18
T
512
16
6
7
8
9
10
0
A
C
–3.7
Table 63
DDR2 Memory Components
Field
Description
Values
Coding
1
INFINEON
Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL1.8
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
5+6
Number of I/Os
256
256 M
512
512 M
1G
1 Gb
40
×4
80
×8
160
×16
7
Product Variations
0 .. 9
look up table
8
Die Revision
A
First
B
Second
9
Package,
Lead-Free Status
C
FBGA,
lead-containing
F
FBGA, lead-free
10
Speed Grade
–3
DDR2–667C 4–4–4
–3S
DDR2–667D 5–5–5
–3.7
DDR2–533C 4–4–4
–5
DDR2–400B 3–3–3
11
Data Sheet
11
N/A for Components
116
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
www.infineon.com
Published by Infineon Technologies AG