Intersil ISL8201MEVAL1Z 10a, high efficiency dc/dc module Datasheet

ISL8201M
®
Data Sheet
October 21, 2010
10A, High Efficiency DC/DC Module
Features
The ISL8201M is a 20V, 10A output current, variable output
step-down power supply. Included in the 15mmx15mm
package is a high performance PWM controller switching at
600kHz, power MOSFETs, an inductor, and all the passive
components required for complete DC/DC power solution.
The ISL8201M operates over an input voltage range of 1V to
20V and supports an output voltage range of 0.6V to 5V,
which is set by a single dividing resistor. This high efficiency
power module is capable of delivering 10A (17A peak) output
with up to 95% efficiency, needing no heat sinks or airflow to
meet power specifications. Only bulk input and output
capacitors are needed to finish the design. Utilizing
voltage-mode control, the output voltage can be precisely
regulated to as low as 0.6V with up to ±1% output voltage
regulation. The ISL8201M also features internal
compensation, internal soft-start, auto-recovery overcurrent
protection, an enable option, and pre-biased output start-up
capability.
• Complete Switch Mode Power Supply
The ISL8201M is packaged in a thermally enhanced, compact
(15mmx15mm) and low profile (3.5mm) over-molded QFN
Package Module suitable for automated assembly by
standard surface mount equipment. The ISL8201M is Pb-free
(RoHS compliant).
FN6657.2
• Bias Voltage Range from +4.5 to +14.4V
- Wide Input Voltage Range from 1V up to 20V (see
“Input Voltage Considerations” on page 11)
• 10A DC Output Current, 17A Peak Output Current
• Adjustable +0.6V to +5V Output Range
• Up to 95% Efficiency
• Simple Voltage Mode Control
• Fixed 600kHz Switching Frequency
• Fast Transient Response
• Enable Function Option
• Pre-biased Output Start-up Capability
• Internal Soft-Start
• Overcurrent Protection by Low-Side MOSFET rDS(ON)
Sensing (Non-Latching, Auto-Recovery)
• Small Footprint, Low Profile Surface Mount QFN Package
(15mmx15mmx3.5mm)
• Pb-Free (RoHS Compliant)
Applications
Typical Schematic
• Servers
(+5V/+12V)
P VC C
or
C PVC C
(+6.5V to 14.4V)
• Industrial Equipment
• Point of Load Regulation
PVCC
COMP/EN
PVCC VIN
V IN
(+4.5V to +20V)
VIN ISL8201M
VO U T
PHASE
C INFB
ISL8201M
V OUT
(+5V / +12V)
1.8V
VIN
10A
CIN
• Other General Purpose Step-Down DC/DC
• Telecom and Datacom Applications
C O UT
VOUT
ISEN
RFB
VOUT
PGND
PG ND
1
FB
COUT R FB
4.87k
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8201M
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PACKAGE
(RoHS Compliant)
PART MARKING
ISL8201MIRZ
ISL8201M
15 Ld QFN
ISL8201MEVAL1Z
Evaluation Board
PKG. DWG. #
L15.15x15
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3)
termination finish. These products do contain Pb but they are RoHS compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic
components and fluorescent tubes). These Intersil RoHS compliant products are compatible with both SnPb and Pb-free soldering operations.
These Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements
of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8201M. For more information on MSL please see techbrief
TB363.
Simplified Block Diagram
PVCC
VIN
SAMPLE
AND
HOLD
PGND
POR
AND
SOFT-START
-
LDO
INHIBIT
DRIVER
+
21.5µA
VOUT
ISET
0.6V
+
FB
+
-
0.4V
+
PWM
GATE
CONTROL
LOGIC
PVCC
DIS
DRIVER
OSCILLATOR
COMP/EN
RSET-IN
PGND
PWM Controller
RFB-TI
ISET
PHASE
FIGURE 1. INTERNAL BLOCK DIAGRAM
2
FN6657.2
October 21, 2010
ISL8201M
Pinout
ISL8201M
(15 LD QFN)
TOP AND 3D VIEW
9
8 7 6 5 4 3 2 1
1
15
14
13
10
12
11
Pin Descriptions
PIN
SYMBOL
1, 2, 3, 4, 11
PGND
Power ground. Connect to ground plane directly.
5
PVCC
Supply voltage. Connect 1µF ceramic capacitor to ground plane directly.
6, 8, 15
NC
7
ISET
Overcurrent protection. Integrated internal 3.57kΩ resistor. Connect additional resistor between this
pin and PGND pin can change initial setting.
9
VIN
Power input. Connect to input.
10
PHASE
12
VOUT
13
COMP/EN
14
FB
3
DESCRIPTION
Do not connect.
Phase node. Node of high-side and low-side MOSFETs and output inductor connection.
Power output. Connect to output.
Compensation and enable.
Feedback input. Connect resistor between this pin and ground for adjusting output voltage.
FN6657.2
October 21, 2010
ISL8201M
Absolute Maximum Ratings
Thermal Information
COMP/EN to PGND . . . . . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to +6V
ISET to PGND. . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to PVCC + 0.3V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to +15V
PHASE to PGND . . . . . . . . . . . . . . . . . . . . . . . . -1.2V ~ +30V (Note 4)
VIN to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . -1.2V ~ +30V (Note 4)
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
15 Ld QFN (Notes 5, 6) . . . . . . . . . . . .
13
2
Junction Temperature TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature Range TSTG . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Ratings
Input Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . +1V to +20V
Output Voltage (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . +0.6V to +5V
PVCC
Fixed Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V or +12V
Wide Range Supply . . . . . . . . . . . . . . . . . . . . . . +6.5V to +14.4V
Ambient Temperature Range (TA) . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. VDS (Drain to Source) specification for internal high-side and low-side MOSFET.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board (i.e. 4-layer type without thermal vias
– see tech brief TB379) per JEDEC standards except that the top and bottom layers assume solid planes.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
TA = +25°C. VIN = 12V, VOUT = 1.5V. CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF (ESR = 10mΩ),
22µF/Ceramicx3.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Input Supply Bias Current
IQ(VIN)
IOUT = 0A, VOUT = 1.5V, VIN = 12V, PVCC = 12V
-
10
-
mA
Input In-rush Current
IinRush
IOUT = 0A, VOUT = 1.5V, VIN = 12V, PVCC = 12V
-
140
-
mA
Input Supply Current
IS(VIN)
IOUT = 10A, VOUT = 1.5V, VIN = 12V, PVCC = 12V
-
1.48
-
A
VIN = 12V, VOUT = 1.5V
0
-
10
A
OUTPUT CHARACTERISTICS
Output Continuous Current Range
IOUT(DC)
Line Regulation Accuracy
ΔVOUT/ΔVIN VOUT = 1.5V, IOUT = 0A, VIN =3.3V to 20V, PVCC = 12V
-
0.1
-
%
Load Regulation Accuracy
ΔVOUT/ΔIOUT IOUT = 0A to 10A, VOUT = 1.5V, VIN = 12V, PVCC = 12V
-
0.5
-
%
IOUT = 10A, VOUT = 1.5V, VIN = 12V, PVCC = 12V
-
20
-
mV
Peak-to-Peak Output Ripple Voltage
ΔVOUT
DYNAMIC CHARACTERISTICS
Voltage Change For Positive Load Step
ΔVOUT-DP
IOUT = 0A to 5A. Current slew rate = 2.5A/µs, VIN = 12V,
VOUT = 1.5V, PVCC = 12V
-
36
-
mV
Voltage Change For Negative Load Step
ΔVOUT-DN
IOUT = 0A to 5A. Current slew rate = 2.5A/µs, VIN = 12V,
VOUT = 1.5V, PVCC = 12V
-
39
-
mV
PVCC = 12V; Disabled (Note 7)
4
5.2
7
mA
Fixed 5V supply
4.5
5.0
5.5
V
Wide range supply
6.5
12.0
14.4
V
5V supply
-
22
-
mA
12V supply
-
47
-
mA
CONTROLLER
Shutdown PVCC Supply Current
IPVCC_S
Supply Voltage
PVCC
PVCC Operating Current
IPVCC
IOUT = 10A, VOUT = 1.5V VIN = 12V
Rising PVCC Threshold
VPORR
(Note 7)
3.9
4.1
4.3
V
PVCC Power-On-Reset Threshold Hysteresis
VPORH
(Note 7)
0.30
0.35
0.40
V
4
FN6657.2
October 21, 2010
ISL8201M
Electrical Specifications
TA = +25°C. VIN = 12V, VOUT = 1.5V. CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF (ESR = 10mΩ),
22µF/Ceramicx3. (Continued)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
510
600
660
kHz
9.66
9.76
9.85
kΩ
Oscillator Frequency
FOSC
Internal Resistor Between VOUT and FB Pins
RFB-TI
Disabled Threshold Voltage (COMP/EN)
VENDIS
(Note 7)
0.375
0.4
0.425
V
VREF
(Note 7)
-
0.6
-
V
0°C to +70°C (Note 7)
-1.0
-
+1.0
%
-40°C to +85°C (Note 7)
-1.5
-
+1.5
%
-
3.57
-
kΩ
18.0
21.5
23.5
µA
Reference Voltage
(Note 7)
MIN
Reference Voltage Tolerance
FAULT PROTECTION
Internal Resistor Between ISET and PGND Pins
ISET Current Source
RSET-IN
ISET
(Note 7)
NOTE:
7. Parameters are 100% tested for internal IC prior to module assembly.
Typical Performance Characteristics
Efficiency Performance TA = +25°C, VIN = PVCC (PVCC=5V for 18VIN) , CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF (ESR = 10mΩ),
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
( V OUT xI OUT )
P OUT
Power
22µF/Ceramicx3. The efficiency equation is: Efficiency = Output
- = ----------------------------------------------------------------------------- = --------------P IN
( V IN xI IN )
Input Power
70
3.3V
60
2.5V
1.5V
50
1.2V
70
5.0V
60
3.3V
2.5V
1.5V
50
1.2V
0.8V
0.8V
40
40
30
0
2
6
4
8
10
30
2
0
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (5VIN)
6
8
10
FIGURE 3. EFFICIENCY vs LOAD CURRENT (12VIN)
100
VIN = 12V
VOUT = 1.2V
IOUT = 0A to 5A
90
EFFICIENCY (%)
4
LOAD CURRENT (A)
80
5.0V
70
3.3V
60
2.5V
1.5V
50
1.2V
40
30
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 4. EFFICIENCY vs LOAD CURRENT (18VIN)
5
FIGURE 5. 1.2V TRANSIENT RESPONSE
FN6657.2
October 21, 2010
ISL8201M
Typical Performance Characteristics
(Continued)
Transient Response Performance TA = +25°C, VIN = 12V, VOUT = 1.5V, PVCC = 12V, CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF
(ESR = 10mΩ), 22µF/Ceramicx3 IOUT = 0-5A (10A), Current slew rate = 2.5A/µs
VIN = 12V
VOUT = 1.5V
IOUT = 0A to 5A
VIN = 12V
VOUT = 1.8V
IOUT = 0A to 5A
FIGURE 6. 1.5V TRANSIENT RESPONSE
FIGURE 7. 1.8V TRANSIENT RESPONSE
VIN = 12V
VOUT = 3.3V
IOUT = 0A to 5A
VIN = 12V
VOUT = 2.5V
IOUT = 0A to 5A
FIGURE 9. 3.3V TRANSIENT RESPONSE
FIGURE 8. 2.5V TRANSIENT RESPONSE
CPVCC
PVCC
VOUT
1.8V
10A
VIN
(+5V/+12V)
VIN
CIN (BULK)
220µF
CIN (CER)
10µF
25V
x2
VOUT
ISL8201M
PHASE
COMP/EN
COUT1
22µF
6.3V
x3
COUT2
330µF
FB
ISET
PGND
RFB
4.87k
FIGURE 10. TYPICAL APPLICATION
6
FN6657.2
October 21, 2010
ISL8201M
Pin Functions
PGND (Pins 1, 2, 3, 4, 11)
Power ground pin for signal, input, and output return path.
PGND needs to connect to one (or more) ground plane(s)
immediately, which is recommended to minimize the effect of
switching noise, copper losses, and maximize heat dissipation.
PVCC (Pin 5)
This pin provides the bias supply for ISL8201M, as well as
the low-side MOSFET’s gate and high-side MOSFET’s gate.
If PVCC rises above 6.5V, an internal 5V regulator will
supply to the internal logics bias (but high-side and low-side
MOSFET gate will still be sourced by PVCC). Connect a well
decoupled +5V or +12V supply to this pin.
NC (Pins 6, 8, 15)
These pins have no function; do not connect.
high-side gate and low-side gate of the MOSFETs outputs to
be held low. The external pull-down device will initially need
to overcome a maximum of 5mA of COMP/EN output
current. However, once the controller is disabled, the
COMP/EN output will also be disabled, thus only a 20µA
current source will continue to draw current.
FB (Pin 14)
The FB pin is the output voltage adjustment of the ISL8201M.
It will regulate to 0.6V at the FB pin with respect to the PGND
pin. The ISL8201M has an integrated voltage dividing resistor.
This is a precision 9.76kΩ resistor (RFB-TI) between the VOUT
and FB pins. Different output voltages can be programmed
with additional resistors between FB to PGND.
Reference Circuitry For General
Applications
Typical Application with Single Power Supply
ISET (Pin 7)
The ISET pin is the input for the overcurrent protection
(OCP) setting, which compares the rDS(ON) of the low-side
MOSFET to set the overcurrent threshold. The ISL8201M
has an initial protect overcurrent limit. It has an integrated
internal 3.57kΩ resistor (RSET-IN) between the ISET and
PGND pins, which can prevent significant overcurrent impact
to the module. One can also connect an additional resistor
RSET-EX between the ISET pin and the PGND pin in order to
reduce the current limit point by paralleling.
Figure 11 shows the ISL8201M application schematic for
input voltage +5V or +12V. The PVCC pin can connect to the
input supply directly.
C PVCC
PVCC
COMP/EN
FB
VIN (Pin 9)
Power input pin. Apply input voltage between the VIN pin
and PGND pin. It is recommended to place an input
decoupling capacitor directly between the VIN pin and the
PGND pin. The input capacitor should be placed as closely
as possible to the module.
PHASE (Pin 10)
The PHASE pin is the switching node between the high and
low side MOSFET. It also returns the current path for the
high side MOSFET driver and detects the low-side MOSFET
drain voltage for the overcurrent limits point.
R SET-EX
PGND
VOUT
C OUT
FIGURE 11. TYPICAL APPLICATION SCHEMATIC
Typical Application with Separated Power Supply
Figure 12 shows the ISL8201M application schematic for
wide input voltages from +1V to +20V. The PVCC supply can
source +5V/+12V or +6.5V to 14.4V.
(+5V/+12V)
P VCC
or
(+6.5V to 14.4V) C PVCC
Power output pin. Apply output load between this pin and the
PGND pin. It is recommended to place a high frequency
output decoupling capacitor directly between the VOUT pin
and the PGND pin. The output capacitor should be placed as
closely as possible to the module.
PVCC
(+1V to +20V)
COMP/EN
COMP/EN (Pin 13)
7
ISL8201M
PHASE
(+5V/+12V)
V IN
C IN
V OUT
ISET
R FB
VOUT (Pin 12)
This is the multiplexed pin of the ISL8201M. During soft-start
and normal converter operation, this pin represents the
output of the error amplifier. Use COMP/EN in combination
with the FB pin to compensate for the voltage control
feedback loop of the converter. Pulling COMP/EN low
(VENDIS = 0.4V nominal) will disable (shut-down) the
controller, which causes the oscillator to stop, and the
VIN
FB
VIN
ISL8201M
PHASE
V IN
C IN
V OUT
ISET
R FB
R SET-EX
PGND
VOUT
C OUT
FIGURE 12. WIDE INPUT VOLTAGE APPLICATION SCHEMATIC
FN6657.2
October 21, 2010
ISL8201M
Applications Information
The typical ISL8201M application schematic for input voltage
+5V or +12V is shown in Figure 11. External component
selection is primarily determined by the maximum load
current and input/output voltage.
Programming the Output Voltage
The ISL8201M has an internal 0.6V ±1.5% reference
voltage. Programming the output voltage requires a dividing
resistor (RFB). The output voltage can be calculated as
shown in Equation 1:
9.76k
V OUT = 0.6 × ⎛ 1 + ---------------⎞
⎝
⎠
R
(EQ. 1)
FB
Note: ISL8201M has integrated 9.76kΩ resistance into the
module (dividing resistor for top side). The resistance
corresponding to different output voltages is as shown in
Table 1:
TABLE 1. RESISTANCE TO OUTPUT VOLTAGES
VOUT
0.6V
1.05V
1.2V
1.5V
RFB
open
13k
9.76k
6.49k
VOUT
1.8V
2.5V
3.3V
5V
RFB
4.87k
3.09k
2.16k
1.33k
Initialization (POR and OCP Sampling)
Figure 13 shows a start-up waveform of ISL8201M. The
power-on-reset (POR) function continually monitors the bias
voltage at the PVCC pin. Once the rising POR threshold has
exceeded 4V (VPORR nominal), the POR function initiates
the overcurrent protection (OCP) sample and hold operation
(while COMP/EN is ~1V). When the sampling is complete,
VOUT begins the soft-start ramp.
If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is released
and its voltage rises above the VENDIS trip point.
Figure 14 and Figure 15 show a typical power-up sequence
in more detail. The initialization starts at T0, when either
PVCC rises above VPORR, or the COMP/EN pin is released
(after POR). The COMP/EN will be pulled up by an internal
20µA current source, however, the timing will not begin until
the COMP/EN exceeds the VENDIS trip point (at T1). The
external capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.
From T1, there is a nominal 6.8ms delay, which allows the
PVCC pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
time, the ISET pin is initialized by disabling the low-side gate
driver and drawing ISET (nominal 21.5µA) through RSETI.
This sets up a voltage that will represent the ISET trip point.
At T2, there is a variable time period for the OCP sample and
hold operation (0.0ms to 3.4ms nominal; the longer time
occurs with the higher overcurrent setting). The sample and
hold uses a digital counter and DAC to save the voltage, so
the stored value does not degrade, as long as the PVCC is
above VPORR (See “Overcurrent Protection (OCP)” on
page 10 for more details on the equations and variables).
Upon the completion of sample and hold at T3, the soft-start
operation is initiated, and the output voltage ramps up
between T4 and T5.
COMP/EN
T0
T1
ISET
VOUT
FIGURE 14. ISET AND SOFT-START OPERATION
FIGURE 13. POR AND SOFT-START OPERATION
8
FN6657.2
October 21, 2010
ISL8201M
If the output is pre-biased to a voltage above the expected
value (as shown Figure 18), neither MOSFET will turn on until
the end of the soft-start, at which time it will pull the output
voltage down to the final value. Any resistive load connected
to the output will help pull down the voltage (at the RC rate of
the R of the load and the C of the output capacitance).
ISET
FIGURE 15. ISET AND SOFT-START OPERATION
Soft-Start and Pre-Biased Outputs
The soft-start internally ramps the reference on the
non-inverting terminal of the error amp from 0V to 0.6V in a
nominal 6.8ms. The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the VOUT will be less than the nominal time), due to
some initialization timing, between T3 and T4.
FIGURE 16. NORMAL START-UP
The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally.
After an initialization period (T3 to T4), the error amplifier
(COMP/EN pin) is enabled and begins to regulate the
converter's output voltage during soft-start. The oscillator's
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the softstart is complete and the output should be in regulation at the
expected voltage. This method provides a rapid and controlled
output voltage rise; there is no large inrush current charging the
output capacitors. The entire start-up sequence from POR
typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample and 6.8ms for the soft-start ramp.
Figure 16 shows the normal curve for start-up; initialization
begins at T0, and the output ramps between T1 and T2. If the
output is pre-biased to a voltage less than the expected
value (as shown Figure 17), the ISL8201M will detect that
condition. Neither internal MOSFET will turn on until the
soft-start ramp voltage exceeds the output; VOUT starts
seamlessly ramping from there.
9
FIGURE 17. PRE-BIASED START-UP
FN6657.2
October 21, 2010
ISL8201M
VOUT
Following POR (and 6.8ms delay), the ISL8201M initiates
the overcurrent protection sample and hold operation. The
low side gate driver is disabled to allow an internal 21.5µA
current source to develop a voltage across RSET. The
ISL8201M samples this voltage (which is referenced to the
PGND pin) at the ISET pin, and holds it in a counter and
DAC combination. This sampled voltage is held internally as
the overcurrent set point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.
The actual monitoring of the low side MOSFET
ON-resistance starts 200ns (nominal) after the edge of the
internal PWM logic signal (that creates the rising external
low side gate signal). This is done to allow the gate transition
noise and ringing on the PHASE pin to settle out before
monitoring. The monitoring ends when the internal PWM
edge (and thus low side gate signal) goes low. The OCP can
be detected anywhere within the above window.
500mV/ diV
FIGURE 18. PRE-BIASED START-UP - OVERCHARGED
If the VIN for the synchronous buck converter is from a
different supply that comes up after PVCC, the soft-start will
go through its cycle, but with no output voltage ramp. When
VIN turns on, the output will follow the ramp of the VIN from
zero up to the final expected voltage (at close to 100% duty
cycle, with COMP/EN pin >4V). If VIN is too fast, there may
be excessive inrush current charging the output capacitors
(only the beginning of the ramp, from zero to VOUT matters
here). If this is not acceptable, then consider changing the
sequencing of the power supplies, sharing the same supply,
or adding sequencing logic to the COMP/EN pin to delay the
soft-start until the VIN supply is ready (see “Input Voltage
Considerations” on page 11).
If ISL8201M is disabled after soft-start (by pulling COMP/EN
pin low), and afterwards enabled (by releasing the
COMP/EN pin), then the full initialization (including OCP
sample) will take place. However, there is no new OCP
sampling during overcurrent retries. If the output is shorted
to GND during soft-start, the OCP will handle it, as described
in the next section.
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a
shorted output by using the low side MOSFET
ON-resistance, rDS(ON), to monitor the current. A resistor
(RSET) programs the overcurrent trip level.
This method enhances the converter's efficiency and
reduces cost by eliminating a current sensing resistor. If
overcurrent is detected, the output immediately shuts off. It
cycles the soft-start function in a hiccup mode (2 dummy
soft-start time-outs, then up to one real one) to provide fault
protection. If the shorted condition is not removed, this cycle
will continue indefinitely.
10
If the converter is running at high duty cycles around 75% for
600kHz operation, then the low side gate pulse width may
not be wide enough for the OCP to properly sample the
rDS(ON). For those cases, if the low side gate signal is too
narrow (or not there at all) for 3 consecutive pulses, then the
third pulse will be stretched and/or inserted to the 425ns
minimum width. This allows for OCP monitoring every third
pulse under this condition. This can introduce a small
pulse-width error on the output voltage, which will be
corrected on the next pulse; and the output ripple voltage will
have an unusual 3-clock pattern, which may look like jitter.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by Equation 2:
2 × I SET × R SET
I PEAK = -------------------------------------------r DS ( ON )
(EQ. 2)
where:
ISET is the internal ISET current source (21.5µA typical).
RSET is equivalent resistance between ISET and PGND
pins.
rDS(ON) is typically 6.1mΩ @ (VPVCC = VGS = 10V, IDS = 30A)
and 9mΩ @ (VPVCC = VGS = 4.5V, IDS = 30A).
Note: ISL8201M has integrated 3.57kΩ resistance (RSET-IN).
Therefore, the equivalent resistance of RSET can be
expressed in Equation 3:
R SET-EX × R SET-IN
R SET = ------------------------------------------------------R SET-EX + R SET-IN
(EQ. 3)
The scale factor of 2 doubles the trip point of the MOSFET
voltage drop, compared to the setting on the RSET resistor.
The OC trip point varies in a system mainly due to the
MOSFET rDS(ON) variations (i.e. over process, current and
temperature). To avoid overcurrent tripping in the normal
operating load range, find the RSET resistor from Equation 4,
and with Steps 1 to 3:
FN6657.2
October 21, 2010
ISL8201M
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum ISET from the “Electrical Specifications”
table on page 3.
3. Determine IPEAK for:
( ΔI L )
I PEAK > I OUT ( MAX ) + ------------2
(EQ. 4)
where ΔIL is the output inductor ripple current. In a high input
voltage, high output voltage application, such as 20V input to
5V output, the inductor ripple becomes excessive due to the
fixed internal inductor value. In such applications, the output
current will be limited from the rating to approximately 70%
of the module’s rated current.
The relationships between the external RSET values and the
typical output current IOUT(MAX) OCP levels are as follows:
TABLE 2.
RSET
(Ω)
OCP (A) @ VIN = 12V,
PVCC = 5V
OCP (A) @ VIN = 12V
PVCC = 12V
OPEN
13.3
17.3
50k
12.6
16.6
20k
11.4
14.9
10k
10.2
13.3
5k
7.6
10.3
3k
6.3
8.3
2k
4.9
6.7
The range of allowable voltages detected (2 x ISET x RSET) is
0mV to 475mV. If the voltage drop across RSET is set too
low, then this can cause almost continuous OCP tripping and
retry. It will also be very sensitive to system noise and inrush
current spikes, so it should be avoided. The maximum
usable setting is around 0.2V across RSET (0.4V across the
MOSFET); values above this might disable the protection.
Any voltage drop across RSET that is greater than 0.3V (0.6V
MOSFET trip point) will disable the OCP. Note that
conditions during power-up or during a retry may look
different than normal operation. During power-up in a 12V
system, the ISL8201M starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. Therefore, with low side gate drive
voltages, the rDS(ON) of the MOSFET will be higher during
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at a lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect, a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled, however, it
is affected by the step size of the output and the value of the
output capacitors, as well as the internal error amp
compensation. Therefore, it is possible to trip the overcurrent
with inrush current, in addition to the normal load and ripple
considerations.
11
Figure 19 shows the output response during a retry of an
output shorted to PGND. At time T0, the output has been
turned off due to sensing an overcurrent condition. There are
two internal soft-start delay cycles (T1 and T2) to allow the
MOSFETs to cool down in order to keep the average power
dissipation in retry at an acceptable level. At time T2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied and the current reaches the
ISET trip point any time during the soft-start ramp period, the
output will shut off and return to time T0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 19 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next T2 cycle.
FIGURE 19. OVERCURRENT RETRY OPERATION
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff. At that point, the
logic immediately starts a new two dummy cycle time-out.
Input Voltage Considerations
Figure 12 shows a standard configuration where PVCC is
either 5V (±10%) or 12V (±20%). In each case, the gate
drivers use the PVCC voltage for low side gate and high side
gate driver. In addition, PVCC is allowed to work anywhere
from 6.5V up to the 14.4V maximum. The PVCC range
between 5.5V and 6.5V is not allowed for long-term reliability
reasons, but transitions through it to voltages above 6.5V are
acceptable.
There is an internal 5V regulator for bias, which turns on
between 5.5V and 6.5V. Some of the delay after POR is there
to allow a typical power supply to ramp-up past 6.5V before
FN6657.2
October 21, 2010
ISL8201M
the soft-start ramps begins. This prevents a disturbance on
the output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. Thus, while the recommendation is to not have
the output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application to see if there is any problem. If PVCC powers
up first and the VIN is not present by the time the initialization
is done, then the soft-start will not be able to ramp the output,
and the output will later follow part of the VIN ramp when it is
applied. If this is not desired, then change the sequencing of
the supplies, or use the COMP/EN pin to disable VOUT until
both supplies are ready.
Figure 20 shows a simple sequencer for this situation. If
PVCC powers up first, Q1 will be off, and R3 pulling to PVCC
will turn Q2 on, keeping the ISL8201M in shut-down. When
VIN turns on, the resistor divider R1 and R2 determines when
Q1 turns on, which will turn off Q2 and release the
shut-down. If VIN powers up first, Q1 will be on, turning Q2
off; so the ISL8201M will start-up as soon as PVCC comes
up. The VENDIS trip point is 0.4V nominal, so a wide variety
of N-MOSFET or NPN BJT or even some logic IC's can be
used as Q1 or Q2. However, Q2 must be low leakage when
off (open-drain or open-collector) so as not to interfere with
the COMP output. Q2 should also be placed near the
COMP/EN pin.
VIN
R1
PVCC
R3
TO COMP/EN
R2
Q1
Q2
the capacitor, the less ripple expected but consideration
should be taken for the higher surge current during
power-up. The ISL8201M provides the soft-start function that
controls and limits the current surge. The value of the input
capacitor can be calculated by Equation 5:
I IN × Δt
C IN = ------------------ΔV
(EQ. 5)
Where:
CIN is the input capacitance (µF)
IIN is the input current (A)
Δt is the turn on time of the high-side switch (µs)
ΔV is the allowable peak-to-peak voltage (V)
In addition to the bulk capacitance, some low Equivalent
Series Inductance (ESL) ceramic capacitance is
recommended to decouple between the drain terminal of the
high side MOSFET and the source terminal of the low side
MOSFET. This is used to reduce the voltage ringing created
by the switching current across parasitic circuit elements.
Output Capacitors
The ISL8201M is designed for low output voltage ripple. The
output voltage ripple and transient requirements can be met
with bulk output capacitors (COUT) with low enough
Equivalent Series Resistance (ESR). COUT can be a low
ESR tantalum capacitor, a low ESR polymer capacitor or a
ceramic capacitor. The typical capacitance is 330µF and
decoupled ceramic output capacitors are used. The
internally optimized loop compensation provides sufficient
stability margins for all ceramic capacitor applications with a
recommended total value of 400µF. Additional output filtering
may be needed if further reduction of output ripple or
dynamic transient spike is required.
Layout Guide
To achieve stable operation, low losses, and good thermal
performance some layout considerations are necessary.
FIGURE 20. SEQUENCE CIRCUIT
CPVCC
The VIN range can be as low as ~1V (for VOUT as low as the
0.6V reference) and as high as 20V. There are some
restrictions for running high VIN voltage. The maximum
PHASE voltage is 30V. The VIN + PVCC + any ringing or
other transients on the PHASE pin must be less than 30V. If
VIN is 20V, it is recommended to limit PVCC to 5V.
VIN
PGND
RFB
VOUT
Switching Frequency
The switching frequency is a fixed 600kHz clock, which is
determined by the internal oscillator. However, all of the other
timing mentioned (POR delay, OCP sample, soft-start, etc.) is
independent of the clock frequency (unless otherwise noted).
Selection of the Input Capacitor
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The larger
12
CIN
COUT1
(DECOUPLE)
PGND
FIGURE 21. RECOMMENDED LAYOUT
FN6657.2
October 21, 2010
ISL8201M
• The ground connection between pin 11 and pin 1 to 4
should be a solid ground plane under the module.
• Place a high frequency ceramic capacitor between (1) VIN
and PGND (pin 11) and (2) PVCC and PGND (pin 1 to 4)
as close to the module as possible to minimize high
frequency noise
• Use large copper areas for power path (VIN, PGND,
VOUT) to minimize conduction loss and thermal stress.
Also, use multiple vias to connect the power planes in
different layers.
Thermal Considerations
Experimental power loss curves along with θJA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are
derived from the maximum power allowed while maintaining
the temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
• Keep the trace connection to the feedback resistor short
• Avoid routing any sensitive signal traces near the PHASE
node
12
3.5
MAX. LOAD CURRENT (A)
3.0
3.3V
1.5V
LOSS (W)
2.5
2.0
0.6V
1.5
1.0
0.5
0.0 0
2
4
6
LOAD CURRENT (A)
8
10
8
3.3V
2
80
90
100
110
FIGURE 23. DERATING CURVE (5VIN)
4.0
12
1.5V
MAX. LOAD CURRENT (A)
5.0V
3.5
3.3V
3.0
LOSS (W)
70
AMBIENT TEMPERATURE (°C)
FIGURE 22. POWER LOSS vs LOAD CURRENT (5VIN)
2.5V
2.5
1.5V
2.0
0.6V
1.5
1.0
0.5
0.0
0.6V
4
0
60
10
1.5V
6
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 24. POWER LOSS vs LOAD CURRENT (12VIN)
13
10
0.6V
8
5.0V
6
2.5V
4
3.3V
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 25. DERATING CURVE (12VIN)
FN6657.2
October 21, 2010
ISL8201M
Package Description
Stencil Pattern Design
The structure of ISL8201M belongs to the Quad Flat-pack
No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical conductivity,
low weight and small size. The QFN package is applicable for
surface mounting technology and is being more readily used
in the industry. The ISL8201M contains several types of
devices, including resistors, capacitors, inductors and control
ICs. The ISL8201M is a copper lead-frame based package
with exposed copper thermal pads, which have good electrical
and thermal conductivity. The copper lead frame and multi
component assembly is overmolded with polymer mold
compound to protect these devices.
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio
should typically be 1:1. The aperture width may be reduced
slightly to help prevent solder bridging between adjacent I/O
lands. To reduce solder paste volume on the larger thermal
lands, it is recommended that an array of smaller apertures be
used instead of one large aperture. It is recommended that the
stencil printing area cover 50% to 80% of the PCB layout
pattern. A typical solder stencil pattern is shown in the Package
Outline Drawing L15.15x15 on page 15. The gap width
between pad to pad is 0.6mm. The user should consider the
symmetry of the whole stencil pattern when designing its pads.
A lazer cut, stainless steel stencil with electropolished
trapezoidal walls is recommended. Electropolishing "smoothes"
the aperture walls resulting in reduced surface friction and
better paste release which reduces voids. Using a trapezoidal
section aperture (TSA) also promotes paste release and forms
a "brick like" paste deposit that assists in firm component
placement. A 0.1mm to 0.15mm stencil thickness is
recommended for this large pitch (1.3mm) QFN.
The package outline and typical PCB layout pattern design
and typical stencil pattern design are shown in the package
outline drawing L15.15x15 on page 15. The module has a
small size of 15mmx15mm x 3.5mm. Figure 25 shows typical
reflow profile parameters. These guidelines are general
design rules. Users could modify parameters according to
their application.
PCB Layout Pattern Design
The bottom of ISL8201M is lead-frame footprint, which is
attached to PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing
L15.15x15 on page 15. The PCB layout pattern is essentially
1:1 with the QFN exposed pad and I/O termination
dimensions, except for the PCB lands being a slightly
extended distance of 0.2mm (0.4mm max) longer than the
QFN terminations, which allows for solder filleting around the
periphery of the package. This ensures a more complete and
inspectable solder joint. The thermal lands on the PCB
layout should match 1:1 with the package exposed die pads.
Reflow Parameters
Due to the low mount height of the QFN, "No Clean" Type 3
solder paste per ANSI/J-STD-005 is recommended.
Nitrogen purge is also recommended during reflow. A
system board reflow profile depends on the thermal mass of
the entire populated board, so it is not practical to define a
specific soldering profile just for the QFN. The profile given
in Figure 26 is provided as a guideline, to be customized for
varying manufacturing practices and applications.
300
Thermal Vias
PEAK TEMPERATURE +230°C~+245°C;
TYPICALLY 60s-70s ABOVE +220°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
TEMPERATURE (°C)
250
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops
down and connects to buried copper plane(s), should be
placed under the thermal land. The vias should be about
0.3mm to 0.33mm in diameter with the barrel plated to about
1.0 ounce copper. Although adding more vias (by decreasing
via pitch) will improve the thermal performance, diminishing
returns will be seen as more and more vias are added.
Simply use as many vias as practical for the thermal land
size and your board design rules allow.
200 SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +180°C FOR 90s~120s
150
100
RAMP RATE ≤1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 26. TYPICAL REFLOW PROFILE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6657.2
October 21, 2010
Package Outline Drawing
L15.15x15
15 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 3, 8/10
23X 1.30
2X 7.70
7x 1.70
4X 1.90
1.80
5.90
15
PIN 1
INDEX AREA
1 1514 13
X4
12
2
3
4
5
6
7
8
1.30
0.2 S AB
12
13 14 15 1
2
3
4
5
6
7
8
3.80
3.10
11
15.0±0.2 15.8±0.2
11
2.10
13.80
9.0
5.0
9
9
11X 0.80
0.90
2.10
0.30
6.90
5.10
1.90
6.0000
2.90
45°
(33x0.4)
10
0.05 M S AB 33x 0.5
21X 1.0
15.8±0.2
2X 1.125
5.80
15.0±0.2
3.0
4.80
4.60
2.20
TOP VIEW
4X 7.90
BOTTOM VIEW
5° ALL AROUND
0.2 S
3.5±0.2
0.5
0.05 S
S
SIDE VIEW
NOTES:
1.
Dimensions are in millimeters.
2.
Unless otherwise specified, tolerance : Decimal ± 0.05;
Body Tolerance ±0.1mm
3.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
FN6657.2
October 21, 2010
either a mold or mark feature.
ISL8201M
10
4.12
3.48
2.82
2.18
1.52
0.88
2.38
0.42
0.00
0.22
4.98
4.32
3.68
3.02
8.29
8.30
6.92
6.28
5.62
8.30
5.60
4.60
1.30
2.30
3.10
3.60
4.40
4.90
5.70
6.20
7.00
8.30
6.10
6.18
5.60
4.80
4.30
3.50
3.00
Package Boundary
2.20
8.30
1.70
6.00
0.90
5.10
3.10
0.0
0.40
2.10
0.90
8.29
5.52
6.99
5.52
4.22
4.87
4.22
3.57
2.92
2.27
1.62
0.97
0.32
0.00
0.33
3.58
2.92
2.28
1.62
0.98
0.32
0.00
0.32
0.98
1.63
2.28
2.93
3.58
4.23
0.98
1.70
2.20
0.90
1.90
1.63
2.28
3.00
4.00
8.30
2.93
4.88
8.30
8.30
6.60
5.90
4.30
2.18
0.00
1.35
1.00
1.60
2.80
4.90
STENCIL PATTERN WITH SQUARE PADS-2
6.60
6.60
4.80
3.75
3.40
3.15
1.80
0.30
0.00
0.00
0.60
0.30
3.15
1.20
3.60
2.20
3.75
3.70
4.30
2.00
1.40
0.00
0.90
2.50
4.30
6.60
4.90
4.20
6.60
6.70
FN6657.2
October 21, 2010
4.30
STENCIL PATTERN WITH SQUARE PADS-1
8.30
6.72
7.00
1.52
2.18
2.82
3.48
4.12
6.07
0.22
0.88
0.42
0.00
3.02
2.38
3.50
TYPICAL RECOMMENDED LAND PATTERN
5.27
4.63
4.15
8.31
8.30
5.60
4.60
0.0
1.20
2.20
3.10
5.20
4.88
5.53
7.01
ISL8201M
8.30
5.53
7.00
16
0.40
0.0
6.08