Maxim MAX794ESE 3.0v/3.3v adjustable microprocessor supervisory circuit Datasheet

19-0366; Rev 6; 3/10
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
The MAX793/MAX794/MAX795 microprocessor (µP)
supervisory circuits monitor and control the activities of
+3.0V/+3.3V µPs by providing backup-battery switchover,
among other features such as low-line indication, µP
reset, write protection for CMOS RAM, and a watchdog
(see the Selector Guide below). The backup-battery voltage can exceed VCC, permitting the use of 3.6V lithium
batteries in systems using 3.0V to 3.3V for VCC.
The MAX793/MAX795 offer a choice of reset threshold
voltage range (denoted by suffix letter): 3.00V to 3.15V
(T), 2.85V to 3.00V (S), and 2.55V to 2.70V (R). The
MAX794’s reset threshold is set externally with a resistor
divider. The MAX793/MAX794 are available in 16-pin
DIP and narrow SO packages, and the MAX795 comes
in 8-pin DIP and SO packages.
____________________________Features
MAX793/MAX794/MAX795
o Precision Supply-Voltage Monitor:
Fixed Reset Trip Voltage (MAX793/MAX795)
Adjustable Reset Trip Voltage (MAX794)
o Guaranteed Reset Assertion to VCC = 1V
o Backup-Battery Power Switching—Battery
Voltage Can Exceed VCC
o On-Board Gating of Chip-Enable Signals—7ns
Max Propagation Delay
MAX793/MAX794 Only
o Battery Freshness Seal
o Battery OK Output (MAX793)
o Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning
o Independent Watchdog Timer (1.6s timeout)
o Manual Reset Input
Ordering Information
_____________________Selector Guide
FEATURE
Active-Low Reset
MAX793
MAX794
MAX795
Active-High Reset
MAX793_CPE
0°C to +70°C
16 Plastic DIP
MAX793_CSE
0°C to +70°C
16 Narrow SO
Programmable Reset
Threshold
Low-Line Early Warning
Output
Backup-Battery
Switchover
External Switch Driver
Power-Fail Comparator
Battery OK Output
Watchdog Input
Battery Freshness Seal
Manual Reset Input
Chip-Enable Gating
Pin-Package
16-DIP/SO 16-DIP/SO 8-DIP/SO
PART*
PINPACKAGE
Ordering Information continued on last page.
*The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R =
2.55V to 2.70V) and insert it into the blank to complete the part
number. The MAX794’s reset threshold is adjustable.
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
__________Typical Operating Circuit
(OPTIONAL)
Si9433DY
SILICONIX
3.0V OR 3.3V
0.1µF
0.1µF
________________________Applications
Battery-Powered Computers and Controllers
Embedded Controllers
Intelligent Controllers
Critical µP Power Monitoring
Portable Equipment
TEMP RANGE
0.1µF
3.6V
PMOS
VCC BATT ON OUT
BATT
CE OUT
VCC
MAX793
WDO
+5V SUPPLY
FAILURE
+5V
CE IN
MR
WDI
PFO
LOWLINE
PFI
CMOS
RAM
ADDRESS
DECODER
I/O
NMI
VCC
RESET
BATT OK
GND
A0-A15
µP
RESET
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX793/MAX794/MAX795
General Description
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
VCC ......................................................................-0.3V to +6.0V
VBATT ...................................................................-0.3V to +6.0V
All Other Inputs ..................-0.3V to the higher of VCC or VBATT
Continuous Input Current
VCC .................................................................................200mA
VBATT ................................................................................50mA
GND ..................................................................................20mA
Output Current
VOUT................................................................................200mA
All Other Outputs ..............................................................20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) .842mW
16-Pin Narrow SO (derate 9.52mW/°C above +70°C) ...696mW
Operating Temperature Ranges
MAX793_C_ _/MAX794C_ _/MAX795_C_ _ ......... 0°C to +70°C
MAX793_E_ _/MAX794E_ _/MAX795_E_ _ ........-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Operating Voltage Range,
VCC, VBATT (Note 1)
VCC Supply Current
(excluding IOUT, ICE OUT)
VCC Supply Current in
Battery-Backup Mode
(excluding IOUT)
ISUPPLY
CONDITIONS
TYP
5.5
MAX79_E
1.1
5.5
MAX793/MAX794,
MR = VCC
VCC = 2.1V,
VBATT = 2.3V
VCC < 3.6V
46
60
VCC < 5.5V
62
80
VCC < 3.6V
35
50
VCC < 5.5V
49
70
MAX793/MAX794
32
45
MAX795
24
35
VCC = 0V, VOUT = 0V
Battery Leakage Current
(Note 3)
OUT Output Voltage in
Normal Mode
VOUT
IOUT = 75mA
IOUT = 30mA (Note 4)
IOUT = 250µA (Note 4)
OUT Output Voltage in
Battery-Backup Mode
VOUT
VBATT = 2.3V
VCC VBATT
VSW > VCC > 1.75V (Note 5)
Battery Switch Threshold
(VCC falling)
Battery Switch Threshold
(VCC rising) (Note 7)
2
VSW
VCC VBATT
IOUT = 250µA
VBATT < VRST
VCC - 0.3
VCC - 0.12
VCC - 0.001
VCC - 0.125
VCC - 0.050
VCC - 0.5mV
VBATT - 0.1
VBATT - 0.034
IOUT = 1mA
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R/
MAX794
This value is identical to the reset threshold,
VCC rising for VBATT > VRST
VBATT > VCC
(Note 6)
UNITS
V
µA
µA
µA
BATT Supply Current
(excluding IOUT) (Note 2)
BATT Leakage Current,
Freshness Seal Enabled
MAX
1.0
MAX795
ISUPPLY
MIN
MAX79_C
1
µA
1
µA
0.5
µA
V
V
VBATT - 0.14
20
65
2.69
2.55
2.82
2.68
2.95
2.80
2.30
2.41
2.52
25
65
_______________________________________________________________________________________
mV
V
mV
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MAX793T/MAX795T
3.00
3.075
3.15
MAX793S/MAX795S
2.85
2.925
3.00
MAX793R/MAX795R
2.55
2.625
2.70
MAX793T/MAX795T
3.00
3.085
3.17
MAX793S/MAX795S
2.85
2.935
3.02
MAX793R/MAX795R
2.55
2.635
2.72
1.212
1.212
1.240
1.250
1.262
1.282
V
-25
2
25
nA
VCC < 3.6V
140
200
280
ms
MAX793
30
45
60
MAX794
5
15
25
VCC falling
Reset Threshold (Note 8)
VRST
VCC rising
RESET IN Threshold
(MAX794 only)
VRST IN
VCC falling
VCC rising
RESET IN Leakage Current
(MAX794 only)
Reset Timeout Period
tRP
LOWLINE-to-Reset
Threshold, (V LOWLINE VRST), VCC Falling
VLR
MAX793
MAX794
Low-Line Comparator
Hysteresis
LOWLINE Threshold,
VCC Rising
VLL
10
10
3.23
MAX793S/MAX795S
3.08
MAX793R/MAX795R
2.78
PFI Input Threshold
VTH
VPFI falling
VPFI rising
PFI Input Current
-25
VBOK
mV
V
1.317
1.212
1.212
1.240
1.250
1.262
1.287
V
2
25
nA
10
20
mV
2.00
2.25
2.50
V
PFI Hysteresis, PFI Rising
BATT OK Threshold
(MAX793)
V
mV
mV
MAX793T/MAX795T
MAX794
UNITS
INPUT AND OUTPUT LEVELS
RESET Output-Voltage High
VOH
ISOURCE = 300µA, VCC = VRST min
0.8VCC
0.86VCC
V
BATT OK, BATT ON, WDO,
LOWLINE Output-Voltage
High
VOH
ISOURCE = 300µA, VCC = VRST max
0.8VCC
0.86VCC
V
PFO Output-Voltage High
VOH
ISOURCE = 65µA, VCC = VRST max
0.8VCC
V
BATT ON OutputVoltage High
VOH
ISOURCE = 100µA, VCC = 2.3V, VBATT = 3V
0.8VBATT
V
RESET Output Leakage
Current (Note 9)
ILEAK
VCC = VRST max
-1
-1
µA
PFO Output Short to GND
Current
ISC
VCC = 3.3V, V PFO = 0V
180
500
µA
PFO, RESET, RESET, WDO,
LOWLINE Output-Voltage
Low
VOL
ISINK = 1.2mA; RESET, LOWLINE tested
with VCC = VRST min; RESET, BATTOK,
WDO tested with VCC = VRST max
0.08
0.2VCC
V
_______________________________________________________________________________________
3
MAX793/MAX794/MAX795
ELECTRICAL CHARACTERISTICS (continued)
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
RESET Output-Voltage Low
VOL
MAX79_C, VBATT = VCC = 1.0V, ISINK = 40µA
MAX79_E, VBATT = VCC = 1.2V, ISINK = 200µA
BATT ON OutputVoltage Low
VOL
ISINK = 3.2mA, VCC = VRST max
All Inputs Including PFO
(Note 10)
VIH
VIL
VRST max < VCC < 5.5V
MR Pulse Width
tMR
MAX793/MAX794 only
MR-to-Reset Delay
tMD
MAX793/MAX794 only
MIN
TYP
MAX
UNITS
0.13
0.17
0.3
0.3
V
0.2VCC
V
0.7VCC
0.3VCC
V
MANUAL RESET INPUT
MR Pullup Current
MAX793/MAX794 only, MR = 0V
100
25
ns
75
250
ns
70
250
µA
CHIP-ENABLE GATING
CE IN Leakage Current
ILEAK
Disable mode
±10
nA
Ω
CE IN-to-CE OUT
Resistance
Enable mode, VCC = VRST max
46
CE IN-to-CE OUT
Propagation Delay
VCC = VRST max, Figure 9
2
VOH
VCC = VRST max, IOUT = -1mA,
V CE IN = VCC
VOL
VCC = VRST max, IOUT = 1.6mA,
V CE IN = 0V
CE OUT Drive from CE IN
V
0.2VCC
10
VOH
IOH = 500µA, VCC < 2.3V
ns
0.8VCC
Reset to CE OUT High Delay
CE OUT Output-Voltage
High (reset active)
7
µs
0.8VBATT
V
WATCHDOG (MAX793/MAX794 only)
WDI Input Current
Watchdog Timeout Period
WDI Pulse Width
0V < VCC < 5.5V
tWD
-1
0.01
1
1.00
1.60
2.25
100
µA
s
ns
Note 1: VCC supply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at VBATT = 3.6V and VCC =
5.5V. The state of RESET is tested at VCC = VCC min.
Note 2: Tested at VBATT = 3.6V, VCC = 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around VCC
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at VCC = 5.5V, VBATT = 1.8V and VCC = 1.5V,
VBATT = 1.0V.
Note 4: Guaranteed by design.
Note 5: When VSW > VCC > VBATT, OUT remains connected to VCC until VCC drops below VBATT. The VCC-to-VBATT comparator
has a small 15mV typical hysteresis to prevent oscillation. For VCC < 1.75V (typical), OUT switches to BATT regardless of
VBATT.
Note 6: When VBATT > VCC > VSW, OUT remains connected to VCC until VCC drops below the battery switch threshold (VSW).
Note 7: OUT switches from BATT to VCC when VCC rises above the reset threshold, if VBATT > VRST. In this case, switchover back
to VCC occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If
VBATT < VRST, OUT switches from BATT to VCC when VCC exceeds VBATT.
Note 8: The reset threshold tolerance is wider for VCC rising than for VCC falling to accommodate the 10mV typical hysteresis,
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
4
_______________________________________________________________________________________
3.0V/3.3V/Adjustable Microprocessor
Supervisory Circuits
2.2
VCC = 3.0V
2.0
VCC = 3.3V
1.8
1.6
VCC = 5V
1.4
140
VBATT = 3.0V
120
VBATT = 3.6V
100
80
60
1.2
-40
-20
0
20
40
60
80
MAX793/4, VCC = 3.3V
MAX795, VCC = 3.3V
30
20
VBATT = VCC = VOUT
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
RESET TIMEOUT PERIOD
vs. TEMPERATURE
RESET COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE (VCC FALLING)
0.04
0.02
200
150
100
50
-20
0
20
40
60
80
100
15
10
0
0
-40
-20
0
20
40
60
80
-40
100
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX793
LOWLINE-TO-RESET THRESHOLD
vs. TEMPERATURE
MAX793/MAX794
LOWLINE COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE
MAX793/MAX794
PFI THRESHOLD vs. TEMPERATURE
PROPAGATION DELAY (µs)
80
40mV OVERDRIVE
70
60
50
40
30
20
8
100
1.250
VCC RISING
MAX793 TOC9
10
1.245
PFI THRESHOLD (V)
VCC FALLING
90
MAX793 TOC8
100
MAX793 TOC7
-40
20
5
VCC RISING FROM
OV TO VRST MAX
0
MAX793 TOC6
25
PROPAGATION DELAY (µs)
RESET TIMEOUT PERIOD (ms)
0.06
30
MAX793 TOC5
250
MAX793 TOC4
VCC = 0V
VBATT = 3.6V
0.08
SUPPLY CURRENT (µA)
40
TEMPERATURE (°C)
0.10
LOWLINE-TO-RESET THRESHOLD (mV)
MAX795, VCC = 5V
50
10
40
100
MAX793/4, VCC = 5V
60
IOUT = 250µA
VCC = 0V
VBATT = 5V
1.0
70
VCC SUPPLY CURRENT (µA)
2.4
VCC SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
MAX793 TOC2
VCC-TO-OUT ON-RESISTANCE (Ω)
2.6
160
BATT-TO-OUT ON-RESISTANCE (Ω)
IOUT = 30mA
2.8
MAX793 TOC1
3.0
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793 TOC3
VCC-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
6
4
VCC FALLING
1.240
1.235
2
10
0
1.230
0
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX793/MAX794/MAX795
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX794
RESET IN THRESHOLD AND LOWLINE-TO-RESET IN
THRESHOLD vs. TEMPERATURE
1.239
15
VLOWLINE - VRST
1.238
10
1.237
5
VCC FALLING
1.236
-20
0
20
40
60
80
1.5
1.0
0.5
VBATT FALLING
-40
100
-20
0
20
40
60
80
MAX793 TOC12
50
40
30
20
10
VCC = VRST MAX
0
0
0
100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX793/MAX794
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAX793/MAX794
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
RESET THRESHOLD
vs. TEMPERATURE (NORMALIZED)
1.60
15
1.002
1.001
VRST (NORMALIZED)
LEAKAGE CURRENT (nA)
1.65
VBATT = 5.5V
VCC = 0V
VOUT = 0V
10
100
MAX793 TOC15
20
MAX793 TOC13
1.70
MAX793 TOC14
-40
2.0
60
CE IN-TO-CE OUT ON-RESISTANCE (Ω)
20
CE IN-TO-CE OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793 TOC11
25
VRESET IN
1.240
2.5
30
BATT OK THRESHOLD (V)
RESET IN THRESHOLD (V)
1.241
MAX793
BATT OK THRESHOLD vs. TEMPERATURE
LOWLINE-TO-RESET IN THRESHOLD (mV)
MAX793 TOC10
1.242
WATCHDOG TIMEOUT PERIOD (sec)
1.000
0.999
0.998
5
1.55
0.997
VCC FALLING
0.996
0
1.50
-40
-20
0
20
40
60
80
-40
100
-20
0
20
40
60
80
100
-40
-20
0
20
MAX793/MAX794
PFI TO PFO PROPAGATION DELAY
vs. TEMPERATURE
MAX793 TOC16
10
8
6
4
2
VPFI FALLING
20mV OVERDRIVE
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
6
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________
80
100
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
PIN
MAX793/
MAX794
MAX795
1
1
2
2
3
NAME
FUNCTION
OUT
Supply Output for CMOS RAM. When VCC rises above the reset threshold or above
VBATT, OUT is connected to VCC through an internal p-channel MOSFET switch. When
VCC falls below VSW and VBATT, BATT connects to OUT.
VCC
Main Supply Input
BATT OK
(MAX793)
Battery Status Output. High in normal operating mode when VBATT exceeds VBOK, otherwise low. VBATT is checked continuously. Disabled and logic low while VCC is below VSW.
RESET IN
(MAX794)
Reset Input. Connect to an external resistor-divider to select the reset threshold. The
reset threshold can be programmed anywhere in the VSW to 5.5V range.
—
4
—
PFI
Power-Fail Comparator Input. When PFI is less than VPFT or when VCC falls below VSW,
PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).
Connect to VCC if unused.
5
3
BATT ON
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to VCC. Connect the base/gate of PNP/PMOS transistor to
BATT ON for IOUT requirements exceeding 75mA.
6
4
GND
Ground
7
—
PFO
Power-Fail Comparator Output. When PFI is less than VPFT or when VCC falls below
VSW, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the battery freshness seal (see Battery Freshness Seal, and Power-Fail Comparator sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pullup current. It can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
8
—
MR
9
—
WDO
10
—
WDI
11
5
CE IN
12
6
CE OUT
13
—
RESET
14
—
LOWLINE
15
7
RESET
16
8
BATT
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for VSW < VCC < VRST, and low when VCC is below VSW.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused.
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT remains low for 10µs or until CE IN goes
high, whichever occurs first. CE OUT is pulled up to OUT.
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
Early Power-Fail Warning Output. Low when VCC falls to VLR. This output can be used to
generate an NMI to provide early warning of imminent power failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever VCC is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either VCC rises above the reset threshold, the watchdog triggers a reset
(WDO connected to MR), or MR goes low to high.
Backup-Battery Input. When VCC falls below VSW and VBATT, OUT switches from VCC to
BATT. When VCC rises above the reset threshold or above VBATT, OUT reconnects to
VCC. VBATT can exceed VCC. Connect VCC, OUT, and BATT together if no battery is
used.
_______________________________________________________________________________________
7
MAX793/MAX794/MAX795
______________________________________________________________Pin Description
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
out period (tRP), the state of MR is ignored if PFO is externally forced low to facilitate enabling the battery freshness seal. MR has an internal 70µA pullup current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.
_______________Detailed Description
General Timing Characteristics
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the Selector Guide on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical VCC rise and fall times.
Manual Reset Input (MAX793/MAX794)
Many microprocessor-based products require manualreset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
remains asserted while MR is low, and for tRP (200ms)
after it returns high. During the first half of the reset timeVRST
Reset Outputs
A microprocessor’s (µP’s) reset input starts the µP in a
known state. These MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code execution errors during power-up, power-down, and
VLL
VSW
VCC
5µs
VLOWLINE (MAX793/MAX794)
tRP
VRESET (PULLED UP TO VCC)
tRP
VRESET (MAX793/MAX794)
VCE OUT
VBATT
tRP/2
VWDO
(MAX793/MAX794)
25µs
VBOK
(MAX793)
25µs
PFO
(MAX793/MAX794)
tRP/2
25µs
(PFO FOLLOWS PFI)
BATT ON
25µs
SHOWN FOR VCC = 0V to 3.3V, VBATT = 3.6V, CE IN = GND.
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
MAX794: VRESET IN = VCC (VRST IN / VRST)
Figure 1. Timing Diagram, VCC Rising
8
_______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
VLL
If a brownout condition occurs (VCC dips below the
reset threshold), RESET goes low. Each time RESET is
asserted, it stays low for the reset timeout period. Any
time VCC goes below the reset threshold, the internal
timer restarts.
The watchdog output (WDO) can also be used to initiate a reset. See the Watchdog Output section.
The RESET output is the inverse of the RESET output,
and it can both source and sink current.
VRST
VCC
VSW
VLOWLINE
(MAX793/MAX794)
4µs
VRESET
(RESET PULLED UP TO VCC)
20µs
VRESET
(MAX793/MAX794)
20µs
25µs
VCE OUT
VBATT
10µs
VWDO
(MAX793/MAX794)
25µs
VBOK
(MAX793)
25µs
VPFO
(MAX793/MAX794)
25µs
25µs
VBATT ON
VBATT
SHOWN FOR VCC = 3.3V to 0V, VBATT = 3.6V, CE IN = GND, PFI = VCC.
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE
MAX794: VRESET IN = VCC (VRST IN / VRST)
Figure 2. Timing Diagram, VCC Falling
_______________________________________________________________________________________
9
MAX793/MAX794/MAX795
brownout conditions. RESET is guaranteed to be a
logic low for 0V < V CC < V RST , provided V BATT is
greater than 1V. Without a backup battery (VBATT =
VCC = VOUT), RESET is guaranteed valid for VCC ≥ 1V.
Once V CC exceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period
(tRP); after this interval, RESET becomes high impedance (Figure 2). RESET is an open-drain output, and
requires a pullup resistor to V CC (Figure 3). Use a
4.7kΩ to 1MΩ pullup resistor that provides sufficient
current to assure the proper logic levels to the µP.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
(OPTIONAL)
Si9433DY
SILICONIX
3.3V
D
0.1µF
VRST
S
0.1µF
PMOS
VCC BATT ON OUT
R1
RESET IN
VCC
CMOS
RAM
CE OUT
tRP
R2
VCC
MAX794
3.6V
0.1µF
CE IN
BATT
ADDRESS
DECODER
LOWLINE
MR
+5V SUPPLY
+5V FAILURE
NMI
VCC
RESET
RESET
PFI
GND
VRST = VRST IN
(R1R2 + 1)
Figure 3. MAX794 Standard Application Circuit
Reset Threshold
The MAX793T/MAX795T are intended for 3.3V systems
with a ±5% power-supply tolerance and a 10% systems
tolerance. Except when MR is asserted, reset does not
assert as long as the power supply remains above
3.15V (3.3V - 5%). Reset is guaranteed to assert before
the power supply falls below 3.0V (3.3V - 10%).
The MAX793S/MAX795S are designed for 3.3V ±10%
power supplies. Except when MR is asserted, they are
guaranteed not to assert reset as long as the supply
remains above 3.0V (3.0V is just above 3.3V - 10%).
Reset is guaranteed to assert before the power supply
falls below 2.85V (3.3V - 14%).
The MAX793R/MAX795R are optimized to monitor 3.0V
±10% power supplies. Reset does not occur until VCC
falls below 2.7V (3.0V - 10%), but is guaranteed to
occur before the supply falls below 2.55V (3.0V - 15%).
Program the MAX794’s reset threshold with an external
voltage divider to RESET IN. The reset-threshold tolerance is a combination of the RESET IN tolerance and
the tolerance of the resistors used to make the external
voltage divider. Calculate the reset threshold as follows:
VRST = VRST IN (R1 / R2 + 1)
10
PFO
(EXTERNALLY HELD AT 0V)
PFO STATE LATCHED,
FRESHNESS SEAL ENABLED.
RESET PULLED UP TO VCC
4.7kΩ
PFO
RESET
A0-A15
I/O
WDI
WDO
VRST
Figure 4. Battery Freshness Seal Enable Timing
Using the standard application circuit (Figure 3), the
reset threshold can be programmed anywhere in the
range of VSW (the battery switch threshold) to 5.5V.
Reset is asserted when VCC falls below VSW.
Battery Freshness Seal
The MAX793/MAX794’s battery freshness seal disconnects the backup battery from internal circuitry until it is
needed. This allows an OEM to ensure that the backup
battery connected to BATT is fresh when the final product is put to use. To enable the freshness seal, connect
a battery to BATT, ground PFO, bring VCC above the
reset threshold, and hold it there until reset is deasserted following the reset timeout period, then bring VCC
back down again (Figure 4). Once the battery freshness seal is enabled (disconnecting the backup battery
from the internal circuitry and anything connected to
OUT), it remains enabled until VCC is brought above
VRST. Note that connecting PFO to MR does not interfere with battery freshness seal operation.
BATT OK Output (MAX793)
BATT OK indicates the status of the backup battery.
When reset is not asserted, the MAX793 checks the
battery voltage continuously. If VBATT is below VBOK
(2.0V min), BATT OK goes low; otherwise, it remains
pulled up to VCC. BATT OK also goes low when VCC
goes below VSW.
Watchdog Input (MAX793/MAX794)
In the MAX793/MAX794, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within 1.6s, WDO goes low. The internal
1.6s timer is cleared and WDO returns high either when
______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
4.7kΩ
MAX793/MAX794
VCC
WDO
RESET
MAX793/MAX794/MAX795
VCC
VRST
tRP
RESET
TO µP
MR
WDO
VCC
tWD
∼10µs
WDO
WDI
RESET
WDO CONNECTED TO µP INTERRUPT
RESET PULLED UP TO VCC
Figure 5. Watchdog Timing Relationship
a reset occurs or when a transition (low-to-high or highto-low) takes place at WDI. As long as reset is asserted, the timer remains cleared and does not count. As
soon as reset is released or WDI changes state, the
timer starts counting (Figure 5). WDI can detect pulses
as short as 100ns. Unlike the 5V MAX690 family, the
watchdog function cannot be disabled.
Watchdog Output (MAX793/MAX794)
In the MAX793/MAX794, WDO remains high (WDO is
pulled up to VCC) if there is a transition or pulse at WDI
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if VCC is above VSW.
WDO is a logic low when VCC is below VSW.
If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
circuitry to capture a watchdog fault indication. A continuous high or low on WDI causes 200ms reset pulses
to be issued every 1.6s.
tRP
tWP
tRP
WDI
Figure 6. Generating a Reset on Each Watchdog Fault
Chip-Enable Signal Gating
Internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate disables at the moment CE IN
goes high, or 10µs after reset asserts, whichever
occurs first (Figure 8). This permits the current write
cycle to complete during power-down.
______________________________________________________________________________________
11
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
MAX793
MAX794
MAX795
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
drive connected to CE IN, and the loading on CE OUT.
The CE propagation delay is production tested from the
50% point on CE IN to the 50% point on CE OUT using
a 50Ω driver and 50pF of load capacitance (Figure 9).
For minimum propagation delay, minimize the capacitive load at CE OUT and use a low-output-impedance
driver.
OUT
CHIP-ENABLE
OUTPUT
CONTROL
P
RESET
GENERATOR
P
CE IN
CE OUT
N
Chip-Enable Output
When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to a 46Ω resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pullup connects CE OUT to OUT (Figure 8). This pullup turns off
when the transmission gate is enabled.
Early Power-Fail Warning
(MAX793/MAX794)
Figure 7. Chip-Enable Transmission Gate
The CE transmission gate remains disabled and CE IN
remains high impedance (regardless of CE IN activity)
for the first half of the reset timeout period (tRP / 2), any
time a reset is generated. While disabled, CE IN is high
impedance. When the CE transmission gate is enabled,
the impedance of CE IN appears as a 46Ω resistor in
series with the load at CE OUT.
VRST
Critical systems often require an early warning indicating that power is failing. This warning provides time for
the µP to store vital data and take care of any additional
“housekeeping” functions, before the power supply
gets too far out of tolerance for the µP to operate reliably. The MAX793/MAX794 offer two methods of
achieving this early warning. If access to the unregulated supply is feasible, the power-fail comparator input
(PFI) can be connected to the unregulated supply
through a voltage divider, with the power-fail comparator output (PFO) providing the NMI to the µP (Figure
VRST
VRST
VRST
VCC
VSW
VSW
CE OUT
VBATT
10µs
tRP/2
VBATT
VCC
tRP
RESET
(PULLED TO VCC)
CE IN
VBATT = 3.6V
RESET PULLED UP TO VCC
Figure 8. Chip-Enable Timing
12
______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
VCC
BATT
3.6V
MAX793
MAX794
MAX795
25Ω EQUIVALENT
SOURCE IMPEDANCE
50Ω CABLE
CE OUT
CE IN
50Ω
50pF
CL*
50Ω
GND
*CL INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
Figure 9. CE Propagation Delay Test Circuit
10). If there is no easy access to the unregulated supply, the LOWLINE output can be used to generate an
NMI to the µP (see LOWLINE Output section).
LOWLINE Output (MAX793/MAX794)
The low-line comparator monitors VCC with a threshold
voltage typically 45mV above the reset threshold (10mV
of hysteresis) for the MAX793, and 15mV above RESET
IN (4mV of hysteresis) for the MAX794. For normal
operation (VCC above the reset threshold), LOWLINE is
pulled to VCC. Use LOWLINE to provide an NMI to the
µP when power begins to fall.
UNREGULATED
SUPPLY
First, calculate the worst-case time required for the system to perform its shutdown routine. Then, with the worstcase shutdown time, the worst-case load current, and the
minimum low-line to reset threshold (VLR min), calculate
the amount of capacitance required to allow the shutdown routine to complete before reset is asserted:
CHOLD > ILOAD x tSHDN / VLR
where I LOAD is the current being drained from the
capacitor, VLR is the low-line to reset threshold difference (VLL - VRST), and tSHDN is the time required for
the system to complete an orderly shutdown routine.
Power-Fail Comparator (MAX793/MAX794)
The MAX793/MAX794’s PFI input is compared to an
internal reference. If PFI is less than the power-fail
threshold (VPFT), PFO goes low. The power-fail comparator is intended for use as an undervoltage detector
to signal a failing power supply (Figure 12). However,
the comparator does not need to be dedicated to this
function because it is completely separate from the rest
of the circuitry.
3.0V OR 3.3V
REGULATOR
3.0V OR 3.3V
REGULATOR
VCC
VCC
MAX793
MAX794
R1
TO µP NMI
MAX793
MAX794
PFO
PFI
LOWLINE
CHOLD
TO µP NMI
CHOLD > ILOAD x tSHDN
VLR
R2
GND
GND
Figure 10. Using the Power-Fail Comparator to Generate
Power-Fail Warning
Figure 11. Using LOWLINE to Provide Power-Fail Warning
to the µP
______________________________________________________________________________________
13
MAX793/MAX794/MAX795
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered and before reset asserts. If the system
must also contend with a more rapid VCC fall time, such
as when the main battery is disconnected or a highside switch is opened during normal operation, use
capacitance on the VCC line to provide time to execute
the shutdown routine (Figure 11).
VCC
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
VIN
3.0V OR 3.3V
VCC
R1
MAX793
MAX794
PFI
3.0V OR 3.3V
VCC
R1
PFO
PFI
R2
MAX793
MAX794
PFO
R2
MR
GND
GND
VIN
VCC
VCC
PFO
PFO
VL
VTRIP = R2 (VPFT + VPFH)
VL = R2 (VPFT)
1
1
1
( R1 + R2 ) –
1
( R1 + R2 ) –
VCC
R1
VTRIP
VCC
R1
0V
VIN
VTRIP
VTRIP = VPFT
WHERE VPFT = 1.237V
VPFH = 10mV
R1 + R2
R2
VH = (VPFT + VPFH)
NOTE: VTRIP, VL ARE NEGATIVE
(a)
(
(
VH
VIN
)
R1 + R2
R2
)
(b)
Figure 12. Using the Power-Fail Comparator to Monitor an Additional Power Supply: (a) VIN Is Negative, (b) VIN Is Positive
The power-fail comparator turns off and PFO goes low
when VCC falls below VSW on power-down. During the
first half of the reset timeout period (tRP), PFO is forced
high, irrespective of VPFI. At the beginning of the second half of tRP, the power-fail comparator is enabled
and PFO follows PFI. If the comparator is unused, connect PFI to VCC and leave PFO unconnected. PFO can
be connected to MR so that a low voltage on PFI generates a reset (Figure 12b). In this configuration, when
the monitored voltage causes PFI to fall below VPFT,
PFO pulls MR low, causing a reset to be asserted.
Reset remains asserted as long as PFO holds MR low,
and for 200ms after PFO pulls MR high when the monitored supply is above the programmed threshold.
Backup-Battery Switchover
VBATT is greater than VCC, or when VCC falls below
1.75V (typ) regardless of the BATT voltage.
Switchover at VSW ensures that battery-backup mode is
entered before VOUT gets too close to the 2.0V minimum required to reliably retain data in most CMOS
RAM, (switchover at higher V CC voltages would
decrease backup-battery life). When V CC recovers,
switchover is deferred either until VCC crosses VBATT if
V BATT is below VRST, or when VCC rises above the
reset threshold (V RST) if V BATT is above V RST. This
power-up switchover technique prevents V CC from
charging the backup battery through OUT when using
an external transistor driven by BATT ON. OUT connects to VCC through a 4Ω (max) PMOS power switch
when VCC crosses the reset threshold (Figure 13).
In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a
backup battery installed at BATT, the devices automatically switch RAM to backup power when VCC falls. In
order to allow the backup battery (e.g., a 3.6V lithium
cell) to have a higher voltage than VCC, this family of µP
supervisors (designed for 3.3V and 3V systems) does
not always connect BATT to OUT when V BATT is
greater than VCC. BATT connects to OUT (through a
140Ω switch) either when VCC falls below VSW and
BATT ON is high when OUT is connected to BATT.
Although BATT ON can be used as a logic output to
indicate the battery switchover status, it is most often
used as a gate or base drive for an external pass transistor for high-current applications (see Driving an
External Switch with BATT ON in the Applications
Information section). When V CC exceeds V RST on
power-up, BATT ON sinks 3.2mA at 0.4V. In batterybackup mode, this terminal sources 100µA from BATT.
14
BATT ON (MAX793/MAX794)
______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
VRST
VCC
VSW
3.6V
3.6V
3.3V
VOUT
VBATT = 3.6V
Figure 13. Battery Switchover Timing
Table 1. Input and Output Status in
Battery-Backup Mode
PIN NAME
STATUS
OUT
Connected to BATT through an internal
140Ω switch
VCC
Disconnected from OUT
BATT ON
Pulled up to BATT
BATT OK
Logic low
PFI
Disabled
PFO
Logic low
MR
Disabled, but still pulled up to VCC
WDO
Logic low
WDI
Disabled
RESET
Logic low
RESET
Pulled up to VCC
BATT
LOWLINE
CE IN
CE OUT
Connected to OUT
Logic low
High impedance
Pulled to BATT
to VCC, the collector to OUT, and the base to BATT ON
(Figure 14a). No current-limiting resistor is required, but
a resistor connecting the base of the PNP to BATT ON
can be used to limit the current drawn from VCC, prolonging battery life in portable equipment.
If you are using a PMOS transistor, however, it must be
connected backwards from the traditional method.
Connect the gate to BATT ON, the drain to VCC, and
the source to OUT (Figure 14b). This method orients
the body diode from V CC to OUT and prevents the
backup battery from discharging through the FET when
its gate is high. Two PMOS transistors in the Siliconix
LITTLE FOOT® series are specified with VGS down to
-2.7V. The Si9433DY has a maximum 100mΩ drainsource on-resistance with 2.7V of gate drive and a 2A
drain-source current. The Si9434DY specifies a 60mΩ
drain-source on-resistance with 2.7V of gate drive and
a 5.1A drain-source current.
Using a Super Cap as a Backup
Power Source
Super caps are capacitors with extremely high capacitance values (e.g., order of 0.47F) for their size. Figure
15 shows two ways to use a super cap as a backup
power source. The super cap can be connected
through a diode to the 3V input (Figure 15a); or, if a 5V
supply is also available, the super cap can be charged
up to the 5V supply (Figure 15b), allowing a longer
backup period. Since VBATT can exceed VCC while
VCC is above the reset threshold, there are no special
precautions when using these µP supervisors with a
super cap.
Operation without a
Backup Power Source
These µP supervisors were designed for batterybacked applications. If a backup battery is not used,
connect BATT, OUT, and VCC together, or use a different µP supervisor. See the µP Supervisory Circuits table
at the end of this data sheet.
__________Applications Information
Replacing the Backup Battery
These µP supervisory circuits are not short-circuit protected. Shorting VOUT to ground, excluding power-up
transients such as charging a decoupling capacitor,
destroys the device. Decouple both V CC and BATT
pins to ground by placing 0.1µF ceramic capacitors as
close to the device as possible.
The backup power source can be removed while VCC
remains valid, without danger of triggering a reset
pulse, provided that BATT is decoupled with a 0.1µF
capacitor to ground. As long as VCC stays above the
reset threshold, battery-backup mode cannot be
entered.
Driving an External Switch with BATT ON
BATT ON can be directly connected to the base of a
PNP transistor or the gate of a PMOS transistor. The
PNP connection is straightforward: connect the emitter
LITTLE FOOT is a registered trademark of Siliconix Inc.
______________________________________________________________________________________
15
MAX793/MAX794/MAX795
3.3V
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
PMOS FET
BODY DIODE
TO CMOS RAM
3.0V OR 3.3V
S
D
G
VCC
BATT ON
OUT
VCC
BATT ON
OUT
MAX793
MAX794
MAX795
MAX793
MAX794
MAX795
GND
GND
(a)
(b)
Figure 14. Driving an External Transistor with BATT ON
3.0V OR 3.3V
+5V
VCC
MAX793
MAX794
OUT
VCC
3.0V OR
3.3V
TO STATIC
RAM
RESET
MAX793
MAX794
OUT
VCC
TO STATIC
RAM
1N4148
1N4148
BATT
VCC
TO µP
RESET
BATT
TO µP
0.47F
0.47F
GND
GND
(a)
(b)
Figure 15. Using a Super Cap as a Backup Source
Adding Hysteresis to the Power-Fail
Comparator (MAX793/MAX794)
The power-fail comparator has a typical input hysteresis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section Monitoring
an Additional Power Supply).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees VPFT when
VIN falls to its trip point (VTRIP). R3 adds the additional
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends
16
both above (VH) and below (VL) the original trip point
(VTRIP).
Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (VL)
to coincide with the trip point without hysteresis (VTRIP),
so the entire hysteresis window occurs above VTRIP.
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a threshold. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82kΩ so it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.
______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
MAX793/MAX794/MAX795
VIN
VIN
R1
VCC
R1
MAX793
MAX794
PFI
R2
VCC
R2
R3
PFI
MAX793
MAX794
PFO
GND
R3
C1*
C1*
PFO
GND
*OPTIONAL
*OPTIONAL
TO µP
TO µP
PFO
PFO
0V
VL
0V
VTRIP = VPFT
VH
VTRIP
(R1 R2+ R2)
VL = R1 VPFT
(
(
)
)
1
R3
VCC
R3
WHERE VPFT = 1.237V
VPFH = 10mV
(a)
VTRIP
0V
VTRIP = VPFT
1
1
+
+
R1 R2
1
1
1
+
+
–
R1 R2 R3
VH = (VPFT + VPFH) (R1)
0V
VIN
(R1 +R2R2 )
VH = R1 (VPFT + VPFH)
(b)
VIN
VH
( R11 + R21 + R31 ) –
VD
R3
WHERE VPFT = 1.237V
VPFH = 10mV
VD = DIODE FORWARD VOLTAGE DROP
VL = VTRIP
Figure 16. Adding Hysteresis to the Power-Fail Comparator: (a) Symmetrical Hysteresis, (b) Hysteresis Only on Rising VIN
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage divider to
PFI. PFO can be used to generate an interrupt to the µP
or to cause reset to assert (Figure 12).
Interfacing to µPs with
Bidirectional Reset Pins
Since the RESET output is open drain, the MAX793/
MAX794/MAX795 interface easily with µPs that have
bidirectional reset pins, such as the Motorola 68HC11.
Connecting the RESET output of the µP supervisor
directly to the RESET input of the microcontroller with a
single pullup resistor allows either device to assert
reset (Figure 17).
Negative-Going VCC Transients
These supervisors are relatively immune to short-duration negative-going VCC transients (glitches) while issuing resets to the µP during power-up, power-down, and
brownout conditions. Therefore, resetting the µP when
VCC experiences only small glitches is usually not recommended.
VCC
VCC
VCC
RESET
RESET
RESET
GENERATOR
N
µP
MAX793
MAX794
MAX795
GND
GND
Figure 17. Interfacing to µPs with Bidirectional Reset I/O
______________________________________________________________________________________
17
Figure 18 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not
generated. The graph was produced using negativegoing VCC pulses, starting at 3.3V and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient can typically
have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that
goes 40mV below the reset threshold and lasts for 10µs
or less does not cause a reset pulse to be issued.
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
MAX793-FIG 18
100
90
MAXIMUM PULSE DURATION (µs)
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Watchdog Software Considerations
There is a way to help the watchdog timer monitor software execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than pulsing the watchdog input
high-low-high or low-high-low. This technique avoids a
stuck loop, in which the watchdog timer would continue
to be reset within the loop, keeping the watchdog from
timing out. Figure 19 shows an example of a flow diagram where the I/O driving the watchdog input is set
high at the beginning of the program, set low at the
beginning of every subroutine or loop, then set high
again when the program returns to the beginning. If the
program should hang in any subroutine, the problem
would quickly be corrected, since the I/O is continually
set low and the watchdog timer is allowed to time out,
causing a reset or interrupt to be issued.
START
80
70
60
SET WDI
HIGH
50
40
30
PROGRAM
CODE
20
10
0
10 20
30
40
50
60 70
80
90 100
RESET COMPARATOR OVERDRIVE, VRST - VCC (mV)
Subroutine or
Program Loop
SET WDI LOW
Figure 18. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
RETURN
Figure 19. Watchdog Flow Diagram
18
______________________________________________________________________________________
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
TEMP RANGE
PINPACKAGE
MAX793_EPE
-40°C to +85°C
16 Plastic DIP
MAX793_ESE
-40°C to +85°C
16 Narrow SO
PART*
_________________Pin Configurations
TOP VIEW
OUT 1
16 BATT
15 RESET
MAX794CPE
0°C to +70°C
16 Plastic DIP
VCC 2
MAX794CSE
0°C to +70°C
16 Narrow SO
(RESET IN) BATT OK 3
MAX794EPE
-40°C to +85°C
16 Plastic DIP
PFI 4
MAX794ESE
-40°C to +85°C
16 Narrow SO
BATT ON 5
MAX795_CPA
0°C to +70°C
8 Plastic DIP
MAX795_CSA
0°C to +70°C
8 SO
MAX795_EPA
-40°C to +85°C
8 Plastic DIP
MAX795_ESA
-40°C to +85°C
8 SO
14 LOWLINE
MAX793
MAX794
13 RESET
12 CE OUT
GND 6
11 CE IN
PFO 7
10 WDI
MR 8
9
WDO
8
BATT
DIP/Narrow SO
*The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R =
2.55V to 2.70V) and insert it into the blank to complete the part
number. The MAX794’s reset threshold is adjustable.
OUT 1
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
VCC 2
BATT ON 3
7 RESET
MAX795
GND 4
6 CE OUT
5 CE IN
DIP/SO
Chip Information
( ) ARE FOR MAX794
TRANSISTOR COUNT: 1271
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 SO
S8-2
21-0041
8 Plastic Dip
R8-1
21-0043
16 Plastic Dip
P16-1
21-0043
16 Narrow SO
S16-1
21-0041
______________________________________________________________________________________
19
MAX793/MAX794/MAX795
_Ordering Information (continued)
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
2/95
Initial release
5
2/07
Revised Electrical Characteristics.
6
3/10
Revised Absolute Maximum Ratings and Chip-Enable Input section.
PAGES
CHANGED
—
4
1, 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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