Cherry CS3845BGDR14 Current mode pwm control circuit with 50% max duty cycle Datasheet

CS3845B
CS3845B
Current Mode PWM Control Circuit
with 50% Max Duty Cycle
Description
Features
exceeds 50%. The undervoltage lockout feature ensures that VREF is stabilized within specification before the
output stage is enabled. The CS3845B
has been optimized for lower start up
current (500µA max).
The CS3845B provides all the necessary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components.
The CS3845B incorporates a precision
temperature-controlled oscillator to
minimize variations in frequency. An
internal toggle flip-flop, which blanks
the output off every other clock cycle,
ensures that the duty-cycle never
Other features include 1% trimmed
band gap reference, pulse-by-pulse
current limiting, and a high-current
totem pole output for driving capacitive loads.
Absolute Maximum Ratings
Supply Voltage (ICC<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (VFB, VSENSE)...........................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ..........10 sec. max, 260°C peak
Reflow (SMD styles only) ...........60 sec. max above 183°C, 230°C peak
■ Optimized for Off-line Use
■ Temperature
Compensated Oscillator
■ 50% Maximum Duty-cycle
Clamp
■ Low Start-up Current
(500µA max)
■ Pulse-by-pulse Current
Limiting
■ Undervoltage Active Pull
Down
■ Double Pulse Suppression
■ 1% Trimmed Bandgap
Reference
■ High Current Totem Pole
Output
Package Options
Block Diagram
8 Lead PDIP & SO
V CC Undervoltage Lock-out
V CC
34V
V CC Pwr
Set/
5.0 Volt
Reset Reference
Gnd
V REF
8.4V/7.6V
V FB
OSC
R
+
2.50V
Oscillator
R
Toggle
Flip-Flop
NOR
VREF
7
VCC
Sense
3
6
VOUT
OSC
4
5
Gnd
COMP 1
14
VREF
NC 2
13
NC
VFB 3
12
VCC
NC 4
11
VCC Pwr
Sense 5
10
VOUT
NC 6
9
Gnd
OSC 7
8
Pwr Gnd
V OUT
Pwr Gnd
R
Sense
8
2
14 Lead SO Narrow
V REF
Undervoltage
Lockout
S
2 R
R
1
VFB
Internal
Bias
Error
Amplifier
COMP
COMP
1V
Current PWM
Sensing Latch
Comparator
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 11/19/98
1
A
®
Company
CS3845B
Electrical Characteristics: 0≤TA≤70˚C, VCC=15V; RT=10kΩ, CT=3.3nF for sawtooth mode, unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.90
5.00
5.10
V
6
20
mV
■ Reference Section
Output Voltage
TJ=25˚C, IREF=1mA
Line Regulation
12≤VCC≤25V
Load Regulation
1≤IREF≤20mA
Temperature Stability
(Note 1)
Total Output Variation
Line, Load, Temp. (Note 1)
6
25
mV
0.2
0.4
mV/˚C
5.18
V
4.82
Output Noise Voltage
10Hz≤f≤10kHz, TJ=25˚C (Note 1)
50
Long Term Stability
TA=125˚C, 1000 Hrs. (Note 1)
5
25
mV
µV
Output Short Circuit
TA=25˚C
-30
-100
-180
mA
Initial Accuracy
Sawtooth Mode, TJ=25˚C
47
52
57
kHz
Voltage Stability
12≤VCC≤25V
0.2
1.0
%
Temperature Stability
Sawtooth Mode TMIN≤TA≤TMAX
(Note 1)
VOSC (peak to peak)(Note 1)
5
17
■ Oscillator Section
Amplitude
%
V
TJ=25°C; (Note 1)
TMIN≤TA≤TMAX (Note 1)
7.5
7.2
8.3
9.3
9.5
mA
mA
Input Voltage
VCOMP=2.5V
2.42
2.50
2.58
V
Input Bias Current
VFB=0V
-0.3
-2.0
µA
AVOL
2≤VOUT≤4V
65
90
dB
Unity Gain Bandwidth
(Note 1)
0.7
1.0
MHz
Discharge
■ Error Amp Section
PSRR
12≤VCC≤25V
60
70
dB
Output Sink Current
VFB=2.7V, VCOMP=1.1V
2
6
mA
Output Source Current
VFB=2.3V, VCOMP=5V
-0.5
-0.8
mA
VOUT HIGH
VFB=2.3V, RL15kΩ to Gnd
5
6
V
VOUT LOW
VFB=2.7V, RL=15kΩ to VREF
0.7
1.1
V
■ Current Sense Section
Gain
(Notes 2&3)
2.85
3.00
3.15
V/V
Maximum Input Signal
VCOMP=5V (Note 2)
0.9
1.0
1.1
V
PSRR
12≤VCC≤25V (Note 2)
70
dB
Input Bias Current
VSense=0V
-2
-10
µA
Delay to Output
TJ=25˚C (Note 1)
150
300
ns
Output Low Level
ISINK=20mA
ISINK=200mA
0.1
1.5
0.4
2.2
V
V
Output High Level
ISOURCE=20mA
ISOURCE=200mA
■ Output Section
13.0
12.0
13.5
13.5
V
V
Rise Time
TJ=25˚C, CL=1nF (Note 1)
50
150
ns
Fall Time
TJ=25˚C, CL=1nF (Note 1)
50
150
ns
2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
300
500
µA
17
mA
■ Total Standby Current
Start-Up Current
Operating Supply Current
VFB=VSense=0V RT=10kΩ, CT=3.3nF
11
VCC Zener Voltage
ICC=25mA
34
V
■ PWM Section
Maximum Duty Cycle
46
48
Minimum Duty Cycle
50
%
0
%
■ Under-Voltage Lockout Section
Start Threshold
Min. Operating Voltage
Notes:
After Turn On
1. These parameters, although guaranteed, are not 100% tested in production.
7.8
8.4
9.0
V
7.0
7.6
8.2
V
3. Gain defined as: A =
2. Parameter measured at trip point of latch with VFB=0
∆VCOMP
∆VSense
; 0 ≤ VSense ≤ 0.8V.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
8L PDIP & SO
14L SO
1
1
COMP
2
3
VFB
3
5
Sense
Noninverting input in Current Sense Comparator
4
7
OSC
Oscillator timing network with Capacitor to Gnd, resistor
to VREF
5
9
Gnd
Ground
6
10
VOUT
Output drive pin
7
12
VCC
Positive power supply
8
14
VREF
Output of 5V internal reference
8
Pwr Gnd
Output driver Gnd
11
VCC Pwr
Output driver positive supply
2, 4, 6, 13
NC
Error amp output, used to compensate error amplifier
Error amp inverting input
No Connection
3
CS3845B
Electrical Characteristics: continued
CS3845B
Test Circuit
V REF
RT
2N2222
V CC
A
100kΩ
COMP
4.7kΩ
1kΩ
Error Amp
Adjust
V REF
V FB
V CC
CS-3845B
0.1µF
5kΩ
4.7kΩ
V OUT
Sense
Sense
Adjust
0.1µF
OSC
1kΩ
1W
V OUT
Gnd
Gnd
CT
Circuit Description
V CC
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driver is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage currents.
ON/OFF Command
to reset of IC
CSX845B
V ON
V OFF
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
2). An increase in VCC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.
When the power supply sees a sudden large output current increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
cycle tends to exceed the maximum allowed to prevent
transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of OSC components.
8.4V
7.6V
I CC
<15mA
<1mA
V CC
V ON
V OFF
Figure 1: Startup voltage for CS3845B.
4
Setting the Oscillator
The parameters Tc and Td can be determined as follows:
VOSC
OSC
RESET
t c = RTCT ln
Toggle
F/F Output
t d = RTCT ln
EA Output
Switch
Current
(
(
VREF - Vlower
VREF - Vupper
)
VREF - IdRT - Vlower
VREF - IdRT - Vupper
)
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA,
then
tc ≈ 0.5534RTCT
VCC
IO
VO
td = RTCT ln
Figure 2: Timing Diagram
(
2.3 - 0.0083 RT
4.0 - 0.0083 RT
)
For better accuracy RT should be ≥10kΩ.
Vupper
Grounding
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Vlower
ton
toff
td
tC
ton = tC
toff = tC+2td
Figure 3: Timing Parameters.
5
CS3845B
Circuit Description: continued
CS3845B
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
Metric
8 Lead PDIP
8 Lead SO Narrow
14 Lead SO Narrow
Max
10.16
5.00
8.75
Thermal Data
8L
PDIP
52
100
English
Min
9.02
4.80
8.55
Max
.400
.197
.344
RQJC
RQJA
Min
.355
.189
.337
typ
typ
8L
SO
45
165
14 L
SO
30
125
˚C/W
˚C/W
PDIP: 300 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
D
SO Narrow; 150 mil wide
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
1.75 (.069) MAX
1.57 (.062)
1.37 (.054)
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
D
0.25 (0.10)
0.10 (.004)
REF: JEDEC MS-012
Ordering Information
Part Number
CS3845BGN8
CS3845BGD8
CS3845BGDR8
CS3845BGD14
CS3845BGDR14
Rev.11/19/98
0˚C to 70°C
•
•
•
•
•
Description
8L PDIP
8L SO
8L SO (tape & reel)
14L SO
14L SO (tape & reel)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
6
© 1999 Cherry Semiconductor Corporation
Similar pages