ON MC74VHC132DR2G Quad 2-input nand schmitt trigger Datasheet

MC74VHC132
Quad 2-Input NAND Schmitt
Trigger
The MC74VHC132 is an advanced high speed CMOS Schmitt
NAND trigger fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHC00,
but the inputs have hysteresis and, with its Schmitt trigger function,
the VHC132 can be used as a line receiver which will receive slow
input signals.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
1
14
Features
•
•
•
•
•
•
•
•
•
•
•
•
VHC132G
AWLYWW
High Speed: tPD = 4.9 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
1
VHC
132
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
(Top View)
Figure 1. Pinout: 14−Lead Packages
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 6
1
Publication Order Number:
MC74VHC132/D
MC74VHC132
A1
1
A3
3
B1
A2
B2
8
Y1
2
B3
4
A4
6
9
12
11
Y2
5
B4
Y3
10
Y4
13
Figure 2. Logic Diagram
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎ
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MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
Value
Unit
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
$20
mA
Iout
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to +150
°C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−55
+ 125
°C
TA
Operating Temperature, All Package Types
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74VHC132
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
TA = 25°C
Min
VT+
Positive Threshold Voltage
(Figure 5)
3.0
4.5
5.5
VT−
Negative Threshold Voltage
(Figure 5)
3.0
4.5
5.5
0.9
1.35
1.65
VH
Hysteresis Voltage (Figure 5)
3.0
4.5
5.5
0.30
0.40
0.50
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
IOH = − 50 mA
2.0
3.0
4.5
1.9
2.9
4.4
Vin = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
3.0
4.5
2.58
3.94
Vin = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
VOL
Maximum Low−Level Output
Voltage
Typ
TA = −55 to +125°C
Max
Min
2.20
3.15
3.85
Max
Unit
2.20
3.15
3.85
V
0.90
1.35
1.65
1.20
1.40
1.60
V
0.30
0.40
0.50
2.0
3.0
4.5
1.20
1.40
1.60
V
V
1.9
2.9
4.4
2.48
3.80
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND
0 to
5.5
± 0.1
± 1.0
mA
ICC
Maximum Quiescent Supply
Current
Vin = VCC or GND
5.5
2.0
20.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Test Conditions
tPLH,
tPHL
Maximum Propagation Delay,
A or B to Y
Cin
Min
TA = −55 to +125°C
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.6
10.1
11.9
15.4
1.0
1.0
14.0
17.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
4.9
6.4
7.7
9.7
1.0
1.0
9.0
11.0
4
10
Maximum Input Capacitance
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
16
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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3
MC74VHC132
ORDERING INFORMATION
Package
Shipping†
MC74VHC132DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74VHC132DR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
M74VHC132DTR2G
TSSOP−14*
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC132
TEST POINT
VCC
A
50%
OUTPUT
GND
tPLH
Y
DEVICE
UNDER
TEST
tPHL
CL*
50% VCC
*Includes all probe and jig capacitance
VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
Figure 3. Switching Waveforms
Figure 4. Test Circuit
4
3
(VT+)
VHtyp
2
(VT-)
1
2
3
4
5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT+ typ) - (VT- typ)
6
Figure 5. Typical Input Threshold, VT+, VT− versus Power Supply Voltage
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
VCC
VH
VT+
Vin
VT-
(b) A Schmitt-Trigger Offers Maximum Noise Immunity
VH
Vin
VCC
VT+
VT-
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
Figure 6. Typical Schmitt−Trigger Applications
INPUT
Figure 7. Input Equivalent Circuit
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5
MC74VHC132
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
0.25
M
C A
S
B
S
DETAIL A
h
A
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
b
X 45 _
M
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74VHC132
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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MC74VHC132/D
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