Holtek HT83R074 Q-voice Datasheet

HT83R074
Q-VoiceTM
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.4V~5.2V
· Two 8-bit programmable timer counter with 8-stage
prescaler and one time base counter
· Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
· Watchdog Timer
system clock
· System clock: 4MHz~8MHz (2.4V)
· 4-level subroutine nesting
· Crystal or RC oscillator for system clock
· HALT function and wake-up feature reduce power
consumption
· 12 I/O pins
· PWM circuit direct drive speaker or output by
· 2K´15 program ROM
transistor
· 80´8 RAM
· 28-pin SOP package
· 1536K voice ROM size
· 72 sec voice length
Applications
· Intelligent educational leisure products
· Sound effect generators
· Alert and warning systems
General Description
The HT83R074 is excellent for versatile voice and
sound effect product applications. The efficient MCU instructions allow users to program the powerful custom
applications. The system frequency of HT83R074 can
be up to 8MHz under 2.4V and include a HALT function
to reduce power consumption.
The HT83R074 is 8-bit high performance microcontroller
with voice synthesizer and tone generator. The
HT83R074 is designed for applications on multiple I/Os
with sound effects, such as voice and melody. It can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator.
Rev. 1.00
1
May 17, 2007
HT83R074
Block Diagram
S T A C K 0
In te rru p t
C ir c u it
S T A C K 1
S T A C K 2
P ro g ra m
C o u n te r
P ro g ra m
R O M
T M R 0
8 - s ta g e P r e s c a le r
T M R 0 C
S T A C K 3
8 - b it
IN T C
T M R 1
In s tr u c tio n
R e g is te r
M P 0
M
U
X
8 - s ta g e P r e s c a le r
T M R 1 C
D a ta
M e m o ry
M U X
P A C
O S
R E
V D
V S
P O R T A
C 1
S
D
S
S Y S C L K /4
P A 0 ~ P A 7
S T A T U S
A L U
O S C 2
S Y S C L K /1 0 2 4
P A
T im in g
G e n e r a tio n
S Y S C L K
8 - b it
T im e B a s e
In s tr u c tio n
D e c o d e r
S Y S C L K
P B C
S h ifte r
P O R T B
P B 0 ~ P B 3
P B
W D T S
A C C
M
W D T P r e s c a le r
¸ 2 5 6
U
X
W D T R C
O S C
S Y S C L K /4
S Y S C L K
P W M
P W M 1
P W M 2
Pin Assignment
N C
1
2 8
N C
N C
2
2 7
N C
N C
3
2 6
N C
P A 0
4
2 5
P W M 2
P A 1
5
2 4
P W M 1
P A 2
6
2 3
V D D P
P A 3
7
2 2
V D D
P A 4
8
2 1
V S S
P A 5
9
2 0
V S S P
P A 6
1 0
1 9
O S C 1
P A 7
1 1
1 8
O S C 2
P B 0
1 2
1 7
R E S
P B 1
1 3
1 6
N C
P B 2
1 4
1 5
P B 3
H T 8 3 R 0 7 4
2 8 S O P -A
Rev. 1.00
2
May 17, 2007
HT83R074
Pad Assignment
(0 ,0 )
P A 0
P A 1
P A 2
1
3
P A 3
4
P A 4
P A 5
5
6
1 0
1 1 1 2
P B 2
P B 3
P B 1
P B 0
P A 7
1 3
1 4
1 5
1 6
1 7
1 8
O S C 1
9
O S C 2
8
T R IM 1
T R IM 2
T R IM 3
7
R E S
P A 6
2 4
P W M 2
2 3
P W M 1
2 2
V D D P
2
2 1
V D D
2 0
V S S
1 9
V S S P
Chip size: 2440 ´ 4390 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
3
May 17, 2007
HT83R074
Pad Coordinates
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
-1070.900
-1070.900
-1070.900
-1070.900
-1070.900
-1070.900
-1070.900
-869.350
-766.350
-671.350
-568.350
-473.350
-1459.100
-1554.100
-1657.100
-1752.100
-1855.100
-1950.100
-2053.100
-2045.900
-2045.900
-2045.900
-2045.900
-2045.900
13
14
15
16
17
18
19
20
21
22
23
24
-328.550
-109.963
-19.960
70.043
794.300
889.300
1044.974
1062.200
1048.625
1035.400
1035.400
1035.400
-2039.750
-2052.049
-2052.049
-2052.049
-2045.900
-2045.900
-2089.750
-1994.724
-1899.700
-1792.026
-1661.176
-1450.676
Pad Description
Pad Name
I/O
Option
Description
PA0~PA7
I/O
Wake-up,
Pull-high
or None
Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input by
configuration option. Software instructions determine the CMOS output or
Schmitt trigger input with or without pull-high resistor (configuration option).
PB0~PB3
I/O
Pull-high
or None
Bidirectional 4-bit I/O port. Software instructions determine the CMOS output or
Schmitt trigger input (pull-high resistor depending on configuration option).
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
VSSP
¾
¾
PWM negative power supply, ground
VDDP
¾
¾
PWM positive power supply
I
¾
Schmitt trigger reset input, active low
OSC1,
OSC2
¾
RC or
Crystal
PWM1,
PWM2
O
¾
RES
OSC1 and OSC2 are connected to an RC network or crystal (by configuration
option) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock. The system clock may came form the crystal, the two pins cannot be floating.
PWM output for driving a external transistor or speaker.
Absolute Maximum Ratings
Supply Voltage ..........................VSS+2.4V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
4
May 17, 2007
HT83R074
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
ISTB1
Standby Current (Watchdog Off)
ISTB2
Test Conditions
Min.
Typ.
Max.
Unit
2.4
¾
5.2
V
¾
¾
1
mA
5V
¾
¾
2
mA
3V
¾
¾
2
mA
¾
¾
4
mA
¾
¾
2
mA
¾
¾
5
mA
7
¾
¾
mA
15
¾
¾
mA
-3.5
¾
¾
mA
-8
¾
¾
mA
50
¾
¾
mA
100
¾
¾
mA
-14.5
¾
¾
mA
26
¾
¾
mA
¾
1
¾
V
¾
2
¾
V
¾
2
¾
V
¾
3.2
¾
V
¾
1.5
¾
V
¾
2.5
¾
V
¾
2.1
¾
V
¾
3.5
¾
V
RTYPICAL=275kW
¾
4.0
¾
MHz
RTYPICAL=144kW
¾
8.0
¾
MHz
20
60
100
kW
10
30
50
kW
Conditions
VDD
¾
fSYS=4MHz/8MHz
3V
No load, system HALT
Standby Current (Watchdog On)
No load, system HALT
5V
IDD
3V
Operating Current
No load, fSYS=4MHz
5V
IOL1
3V
I/O Port Sink Current
VOL=0.1V
5V
IOH1
3V
I/O Port Source Current
VOH=0.9V
5V
IOL2
3V
PWM1/PWM2 Sink Current
VOL=0.1V
5V
IOH2
3V
PWM1/PWM2 Source Current
VOH=0.9V
5V
VIL1
3V
¾
Input Low Voltage (RES)
5V
VIH1
3V
¾
Input High Voltage (RES)
5V
VIL2
3V
¾
Input Low Voltage (RES)
5V
VIH2
3V
¾
Input High Voltage (RES)
5V
fSYS
RPH
System Frequency
3V
3V
¾
Pull-high Resistance
5V
Rev. 1.00
5
May 17, 2007
HT83R074
A.C. Characteristics
Symbol
Test Conditions
Parameter
Conditions
VDD
Min.
Typ.
Max.
Unit
fSYS
System Clock
(Crystal OSC, RC OSC)
¾
2.4V~5.2V
4
¾
8
MHz
fTIMER
Timer Input Frequency
3V
2.4V~5.2V
0
¾
8
MHz
tWDTOSC
50
100
200
Watchdog Oscillator
ms
37
74
148
ms
12
23
45
ms
8
17
33
ms
¾
1024
¾
ms
1
¾
¾
ms
¾
1024
¾
tSYS
3V
¾
5V
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V
tWDT2
Watchdog Time-out Period
(System OSC)
¾
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tDRT
Data ROM Access Timer
¾
¾
5
¾
¾
ms
tDRR
Data ROM Enable Read
¾
Read after data ROM enable
30
¾
¾
ms
Without WDT prescaler
5V
Without WDT prescaler
¾
Power-up or wake-up from
HALT
Characteristics Curves
R vs. F Characteristics Curve
H T 8 3 R 0 7 4
R v s . F C h a rt
1 0
8
3 V
4 .5 V
F re q u e n c y (M H z )
6
4
2
0
1 4 4
R
1 8 8
Rev. 1.00
2 7 5
5 6 0
(k W )
6
May 17, 2007
HT83R074
V vs. F Characteristics Curve
H T 8 3 R 0 7 4
V v s . F C h a r t (F o r 3 .0 V )
1 0
8
F re q u e n c y (4 M H z )
8 M H z /1 4 4 k W
6
6 M H z /1 8 8 k W
4
4 M H z /2 7 5 k W
2
2 .5
2 .7
3 .0
3 .5
V
H T 8 3 R 0 7 4
4 .0
4 .5
5 .2
5 .5
(V )
D D
V v s . F C h a r t (F o r 4 .5 V )
1 0
8 M H z /1 3 9 k W
F re q u e n c y (M H z )
8
6 M H z /1 8 4 k W
6
4 M H z /2 7 4 k W
4
2
2 .5
2 .7
3 .0
3 .5
V
Rev. 1.00
4 .0
4 .5
5 .2
5 .5
(V )
D D
7
May 17, 2007
HT83R074
Functional Description
Execution Flow
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
The system clock for the HT83R074 is derived from either a crystal or RC oscillator. It is internally divided into
four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt or return from subroutine, the PC
manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the Program Counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is obtained.
Program Counter - PC
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed.
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256
locations.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
P C
P C
T 2
T 3
T 4
T 1
T 2
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 3
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
Time Base Overflow
0
0
0
0
0
0
0
0
1
0
0
Timer Counter 0 Overflow
0
0
0
0
0
0
0
1
0
0
0
Timer Counter 1 Overflow
0
0
0
0
0
0
0
1
1
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.00
@7~@0: PCL bits
8
May 17, 2007
HT83R074
Program Memory - ROM
Table Location
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the program counter
along with the table pointer. The program memory size
for HT83R074 is 2048´15 bits. Certain locations in the
program memory are reserved for special usage:
Any location in the ROM space can be used as look up
tables. The instructions ²TABRDC [m]² (used for any
bank) and ²TABRDL [m]² (only used for last page of program ROM) transfer the contents of the lower-order byte
to the specified data memory [m], and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined. The
higher-order bytes of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only.
· Location 000H
This area is reserved for program initialization. The
program always begins execution at location 000H
each time the system is reset.
The table pointer (TBLP) is a read/write register, which
indicates the table location.
· Location 004H
This area is reserved for the time base interrupt service program. If the ETBI (intc.1) is activated, and the
interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
Stack Register - Stack
The stack register is a special part of the memory used
to save the contents of the Program Counter. This stack
is organized into four levels. It is neither part of the data
nor part of the program space, and cannot be read or
written to. Its activated level is indexed by a Stack
Pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of
the program counter are pushed onto the stack.
· Location 008H
This area is reserved for the 8-bit Timer Counter 0 interrupt service program. If a timer interrupt results
from a Timer Counter 0 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump
to location 008H and begins execution.
· Location 00CH
The program counter is restored to its previous value
from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or
RETI). After a chip resets, SP will point to the top of the
stack.
This area is reserved for the 8-bit Timer Counter 1 interrupt service program. If a timer interrupt results
from a Timer Counter 1 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump
to location 00CH and begins execution.
0 0 0 0 H
The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and
a non-masked interrupt takes place. After the stack
pointer is decremented (by RET or RETI), the interrupt
request will be serviced. This feature prevents stack
overflow and allows programmers to use the structure
more easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, stack overflow occurs and the first entry is lost.
In itia l A d d r e s s
0 0 0 4 H
T im e B a s e In te r r u p t S u b r o u tin e
0 0 0 8 H
T im e r 0 In te r r u p t S u b r o u tin e
0 0 0 C H
P ro g ra m
R O M
T im e r 1 In te r r u p t S u b r o u tin e
0 0 1 5 H
0 7 F F H
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Current program ROM table
@7~@0: Write @7~@0 to TBLP pointer register
P10~P8: Bits of current program counter
Rev. 1.00
9
May 17, 2007
HT83R074
Data Memory - RAM
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
The data memory is designed with 80´8 bits. The data
memory is further divided into two functional groups,
namely, special function registers (00H~2AH) and general
purpose user data memory (30H~7FH). Although most of
them can be read or be written to, some are read only.
The general purpose data memory, addressed from
30H~7FH, is used for data and control information under instruction commands.
0 0 H
IA R 0
0 1 H
M P 0
0 2 H
The areas in the RAM can directly handle the arithmetic,
logic, increment, decrement and rotate operations. Except some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through the Memory Pointer
register 0 (MP0:01H).
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
Indirect Addressing Register
0 B H
Location 00H is indirect addressing registers that are not
physically implemented. Any read/write operation of
[00H] accesses the RAM pointed to by MP0 (01H) respectively. Reading location 00H indirectly returns the result 00H. While, writing it indirectly leads to no operation.
0 D H
Accumulator - ACC (05H)
1 1 H
0 C H
0 E H
0 F H
1 0 H
1 2 H
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
1 3 H
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
1 4 H
P A C
P B
1 5 H
P B C
1 6 H
1 7 H
1 8 H
L A T C H 0 H
1 9 H
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
L A T C H 0 M
1 A H
L A T C H 0 L
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
1 C H
· Logic operations (AND, OR, XOR, CPL)
1 D H
Arithmetic and Logic Unit - ALU
1 B H
1 E H
· Rotation (RL, RR, RLC, RRC)
1 F H
2 0 H
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc)
2 1 H
2 2 H
Status Register - STATUS (0AH)
2 3 H
This 8-bit STATUS register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
2 4 H
2 5 H
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those intended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the
latest operations.
Rev. 1.00
S p e c ia l P u r p o s e
D a ta M e m o ry
2 6 H
P W M C R
2 7 H
2 8 H
P W M L
P W M H
2 9 H
V o lu m e C o n tr o l R e g is te r ( V O L )
2 A H
L A T C H D
2 B H
: U n u s e d ,
re a d a s "0 "
2 F H
3 0 H
G e n e ra l P u rp o s e D a ta M e m o ry
7 F H
RAM Mapping
10
May 17, 2007
HT83R074
Address
RAM Mapping
Read/Write
Description
00H
IAR0
R/W
Indirect Addressing Register 0
01H
MP0
R/W
Memory Pointer 0
05H
ACC
R/W
Accumulator
06H
PCL
R/W
Program counter lower-order byte address
07H
TBLP
R/W
Table pointer lower-order byte register
08H
TBLH
R
Table higher-order byte content register
09H
WDTS
R/W
Watchdog Timer option setting register
0AH
STATUS
R/W
Status register
0BH
INTC
R/W
Interrupt control register 0
0DH
TMR0
R/W
Timer Counter 0 register
0EH
TMR0C
R/W
Timer Counter 0 control register
10H
TMR1
R/W
Timer Counter 1 register
11H
TMR1C
R/W
Timer Counter 1 control register
12H
PA
R/W
Port A I/O data register
13H
PAC
R/W
Port A I/O control register
14H
PB
R/W
Port B I/O data register
15H
PBC
R/W
Port B I/O control register
18H
LATCH0H
R/W
Voice ROM address latch 0 [A17, A16]
19H
LATCH0M
R/W
Voice ROM address latch 0 [A15~A8]
1AH
LATCH0L
R/W
Voice ROM address latch 0 [A7~A0]
26H
PWMCR
R/W
PWM control register
27H
PWML
28H
PWMH
29H
VOL
2AH
LATCHD
R/W, higher-nibble
PWM output data P3~P0 to PWML7~PWML4
available only
R/W
PWM output data P11~P4 to PWMH7~PWMH0
R/W, higher-nibble
Volume control register and volume controlled by VOL8~VOL4
available only
R
Voice ROM data register
2BH~2FH Unused
30H~7FH User data RAM
Note:
R/W
User data RAM
R: Read only
W: Write only
R/W: Read/Write
low interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related
interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must
be prevented from becoming full.
Interrupts
The HT83R074 provides two 8-bit programmable timer
interrupts, and a time base interrupt. The Interrupt Control registers (INTC:0BH) contain the interrupt control
bits to set to enable/disable and the interrupt request
flags.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at the specified location(s) in
the program memory. Only the program counter is
pushed onto the stack. The programmer must save the
contents of the register or status register (STATUS) in
advance if they are altered by an interrupt service program which corrupts the desired control sequence.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the
EMI bit and the corresponding INTC bit may be set to alRev. 1.00
11
May 17, 2007
HT83R074
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
ET1I), the time base interrupt request flag (TBF) which
enables time base control bit (ETBI) from the interrupt
control register (INTC:0BH) EMI, ETBI, ET0I, ET1I are
used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt begin serviced. Once the interrupt request flags (T0F, T1F, TBF)
are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
The Internal Timer Counter 0 Interrupt is initialized by
setting the Timer Counter 0 interrupt request flag (T0F:bit
5 of INTC), caused by a Timer Counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The Internal Timer Counter 1 Interrupt is initialized by
setting the Timer Counter 1 interrupt request flag (T1F:bit
6 of INTC), caused by a Timer Counter 1 overflow. When
the interrupt is enabled, and the stack is not full and the
T1F bit is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt
subroutine will corrupt the original control sequence.
Time Base Interrupt is triggered by set INTC.1 (ETBI)
which sets the related interrupt request flag (TBF:bit 4 of
INTC). When the interrupt is enabled, and the stack is not
full and the external interrupt is active, a subroutine call to
location 04H will occur. The interrupt request flag (TBF)
and EMI bits will be cleared to disable other interrupts.
Bit No. Label
During the execution of an interrupt subroutine, other interrupt acknowledgment are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (of course, if the stack
is not full). To return from the interrupt subroutine, the
²RET² or ²RETI² instruction may be invoked. RETI will
set the EMI bit to enable an interrupt service, but RET
will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
ETBI
Controls the time base interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer 1 interrupt
(1= enabled; 0= disabled)
4
TBF
Time base interrupt request flag
(1= active; 0= inactive)
5
T0F
Timer 0 request flag
(1= active; 0= inactive)
6
T1F
Timer 1 request flag
(1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
The Timer Counter 0/1 interrupt request flag (T0F/T1F)
which enables Timer Counter 0/1 control bit (ET0I/
Rev. 1.00
12
May 17, 2007
HT83R074
Priority
Vector
Time Base Interrupt
Interrupt Source
1
04H
Timer Counter 0 Overflow
2
08H
Timer Counter 1 Overflow
3
0CH
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by option. If
the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
Oscillator Configuration
The HT83R074 provides two oscillator circuits for system clock, i.e., RC oscillator and Crystal oscillator. No
matter what type of oscillator.. The signal is used for the
system clock. The HALT mode stops the system oscillator to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and
the range of the resistance should be from 144kW to
275kW. The system clock, divided by 4. The RC oscillator provides the most cost effective solution. However,
the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It
is therefore not suitable for timing sensitive operations
where accurate oscillator frequency is desired.
Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
If WS2, WS1, WS0 all equal to 1, the division ratio is up to
1:128, and the maximum time-out period is 2.6 seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
O S C 1
V
fS
O S C 2
Y S
O S C 1
D D
/4
O S C 2
R C
C r y s ta l O s c illa to r
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re set² only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instructions, or a ²HALT² instruction. The software instruction
is ²CLR WDT² and execution of the ²CLR WDT² instruction will clear the WDT.
O s c illa to r
System Oscillator
WS7
WS6
WS5
WS4
WS3
WS2
WS1
WS0
Division Ratio
¾
¾
¾
¾
¾
0
0
0
1:1
¾
¾
¾
¾
¾
0
0
1
1:2
¾
¾
¾
¾
¾
0
1
0
1:4
¾
¾
¾
¾
¾
0
1
1
1:8
¾
¾
¾
¾
¾
1
0
0
1:16
¾
¾
¾
¾
¾
1
0
1
1:32
¾
¾
¾
¾
¾
1
1
0
1:64
¾
¾
¾
¾
¾
1
1
1
1:128
WDTS (09H) Register
Rev. 1.00
13
May 17, 2007
HT83R074
S y s te m
C lo c k /4
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Power Down - HALT
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
The HALT mode is initialized by a ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
Reset
oscillator keeps running (if the WDT oscillator is selected).
There are 3 ways in which a reset can occur:
· RES reset during normal operation
· The contents of the on chip RAM and registers remain
· RES reset during HALT
unchanged.
· WDT time-out reset during normal operation
· WDT and WDT prescaler will be cleared and recount
again.
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset
conditions. Most registers are reset to their ²initial condition² when the reset conditions are met. By examining
the PDF flag and TO flag, the program can distinguish
between different ²chip resets².
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer. The
other maintain their original status.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If awakening from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled by the stack is full, the program will resume
execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place.
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
V
D D
R E S
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
Rev. 1.00
TO
Reset Circuit
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
14
May 17, 2007
HT83R074
The functional unit chip reset status are shown below.
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
When a system power up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
H A L T
W D T
W a rm
W D T
R e s e t
T im e - o u t
R e s e t
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
R E S
C o ld
R e s e t
S S T
1 0 -s ta g e
R ip p le C o u n te r
O S C I
P o w e r - o n D e te c tin g
Reset Configuration
Timer Counter 0/1
The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0) = (0, 1). There is a 3-bit prescaler (TMRS2, TMRS1,
TMRS0) which defines different division ratio of TMR0/TMR1¢s clock source.
Bit No.
0~2
Label
TMRS2,
TMRS1,
TMRS0
Function
Defines the operating clock source (TMRS2, TMRS1, TMRS0)
000: clock source/2
001: clock source/4
010: clock source/8
011: clock source/16
100: clock source/32
101: clock source/64
110: clock source/128
111: clock source/256
3
TE
Defines the TMR0/TMR1 active edge of Timer Counter
4
TON
Enable/disable timer counting (0=disabled; 1=enabled)
5
¾
6
7
TM0,
TM1
Unused bit, read as ²0²
Defines the operating mode (TM1, TM0)
TMR0C (0EH)/TMR1C (11H) Register
Note:
TMR0C/TMR1C bit 3 always write ²0²
TMR0C/TMR1C bit 5 always write ²0²
TMR0C/TMR1C bit 6 always write ²1²
TMR0C/TMR1C bit 7 always write ²0²
(T M R S 2 , T M R S 1 , T M R S 0 )
S y s te m
C lo c k
D a ta B u s
8 -S ta g e
P r e s c a le r
T im e r C o u n te r 0 /1
P r e lo a d R e g is te r
R e lo a d
T O N
T im e r C o u n te r 0 /1
O v e r flo w
to In te rru p t
Timer Counter 0/1
Rev. 1.00
15
May 17, 2007
HT83R074
Time Base
The TMR0C is the Timer Counter 0 control register,
which defines the Timer Counter 0 options. The Timer
Counter 1 has the same options as the Timer Counter 0
and is defined by TMR1C.
The time base enables the counting operation by
INTC.1 (ETBI) bit. The overflow to interrupt as set
INTC.4. The time base is internal clock source only.
Time base of 1ms to overflow as system clock is 4MHz.
Time base of 0.5ms to overflow as system clock is
8MHz.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to ²1². The
overflow of the timer counter is one of the wake-up
sources. No matter what the operation mode is, writing a
0 to ET0I/ET1I can disable the corresponding interrupt
service.
S y s te m
C lo c k /4
¸
1 0 2 4
O v e r flo w
to In te rru p t
Time Base
The TMR0/1 is internal clock source only. There is a
3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/1¢s clock source.
The registers states are summarized in the following table.
Register Reset (Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
TBLP
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR0C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
LATCH0H
---- --xx
---- --uu
---- --uu
---- --uu
---- --uu
LATCH0M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PWMCR
0--- 00-0
u--- uu-u
u--- uu-u
u--- uu-u
u--- uu-u
PWML
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
PWMH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu
uuuu uuuu
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
LATCHD
Note:
²u² means ²unchanged²
²x² means ²unknown²
²-² means ²undefined²
Rev. 1.00
16
May 17, 2007
HT83R074
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13Hm
15H.
Input/Output Ports
There are 12 bidirectional input/output lines in the
microcontroller, labeled from PA to PB, which are
mapped to the data memory of [12H], [14H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A, [m]² (m=12H, 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an input, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
D a ta B u s
Each line of port A has the capability of waking-up the
device. The wake-up capability of port A is determined
by options. There is a pull-high option available for all
I/O lines. Once the pull-high option is selected, all I/O
lines have pull-high resistors. Otherwise, the pull-high
resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
V
D
W r ite C o n tr o l R e g is te r
Q
C K
Q
S
V
C h ip R e s e t
D
P A 0 ~ P A 7
P B 0 ~ P B 3
Q
C K
S
Q
M
R e a d I/O
S y s te m
W e a k
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/Output Ports
Rev. 1.00
17
May 17, 2007
HT83R074
Pulse Width Modulation Output - PWML/PWMH (27H/28H)
The HT83R074 provide one 12-bit PWM interface for driving an external 8W speaker. The programmer must write the
voice data to register PWML/PWMH (27H/28H)
Pulse Width Modulation Control Register - PWMCR (26H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1
Bit 0 (R/W)
MSB_SIGN
¾
¾
¾
Single_PWM
VROMC
¾
PWMC
PWMC: Start bit of PWM output
Voice ROM Data Address Latch Counter
· PWM start counter: 0 to 1
The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM,
where the voice codes are stored. One 8-bit of voice
ROM data will be addressed by setting 18-bit address
latch counter LATCH0H/LATCH0M/LATCH0L. After the
8-bit voice ROM data is addressed, a few instruction cycles (4ms at least) will be generated to latch the voice
ROM data, then the microcontroller can read the voice
data from LATCHD (2AH).
· PWM stop counter: 1 to 0
After waiting one cycle end , stop the PWM counter and
keep in low signal
VROMC: Enable voice ROM power circuit
(1=enable; 0=disable)
Single_PWM: Driving PWM single by PWM1 output
(1=PWM1 output; 0=PWM1/PWM2 output)
Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0
The HT83R074 provide an 12-bit (bit 7 is a sign bit, if
Single_PWM = 0) PWM interface. The PWM provides
two pad outputs: PWM1, PWM2 which can directly drive
a piezo or an 8W speaker without adding any external element (green mode), or using only port PWM1 (Set Single_PWM=1) to drive piezo or an 8W speaker with
external element.
When Setting Single_PWM= 1, choose voice data7~
data1 as the output data (no sign bit on it).
If the sign bit is 0, then the signal is output to PWM1and
the PWM2 will get a GND level voltage after setting start
bit to 1. If the sign bit is 1, then the signal is output to
PWM2 and the PWM1 will get a GND level voltage after
setting start bit to 1.
set
[26H].2
; Enable voice ROM circuit
mov
A, 07H
;
mov
LATCH0L, A ; Set LATCH0L to 07H
mov
A, 00H
mov
LATCH0M, A ; Set LATCH0M to 00H
mov
A, 00H
mov
LATCH0H, A ; Set LATCH0H to 00H
call
Delay Time
; Delay a short period of time
mov
A, LATCHD
; Get voice data at 000007H
;
;
PWM output Initial low level , and stop in low level
If PWMC from low to high then start PWM output latch
new data , if no update then keep the old value.
If PWMC from high to low, in duty end, stop PWM output
and stop the counter.
D a ta B u s
S y s te m
C lo c k
F 0
S ta r t b it
2 6 H .0
P W M I
P W M D a ta
B u ffe r (2 8 H )
P r e s c a le r
D iv .
F 2
F 1
C K
P E
B it7 ( s ig n b it)
7 B its C o u n te r
( B it6 ~ B it0 )
O v e r flo w
V
D D
D
Q
Q
C K
R
P W M 1 fo r S p e a k e r
P W M 2 fo r S p e a k e r
PWM
Rev. 1.00
18
May 17, 2007
HT83R074
Option
Option
Description
PA Wake-up
Enable or disable PA wake-up function
Watchdog Timer (WDT)
Enable or disable WDT function.
WDT clock source is from WDTOSC or T1
PA Pull-high
Enable or disable PA pull-high
PB Pull-high
Enable or disable PB pull-high
OSC Option
Crystal or Resistor type
fOSC - ROSC Table (VDD=3V)
fOSC
RTYPICAL
4MHz±10%
6MHz±10%
8MHz±10%
275kW
188kW
144kW
Application Circuits
V
D D
V D D
O S C 2
V S S
O S C 1
R
V
V
D D
O S C
D D
V D D P
1 0 0 k W
4 7 m F
V S S P
R E S
0 .1 m F
C
P A 0 ~ P A 7
S p e a k e r
P W M 1
P W M 2
P B 0 ~ P B 3
(8 W /1 6 W )
H T 8 3 R 0 7 4
Single PWM Mode
V
D D
O S C 2
V D D
4 M H z ~ 8 M H z
V S S
V
O S C 1
V
D D
D D
V D D P
1 0 0 k W
0 .1 m F
C
4 7 m F
V S S P
R E S
P A 0 ~ P A 7
P W M 1
P W M 2
P B 0 ~ P B 3
V
D D
S p e a k e r
(8 W /1 6 W )
Q 2
N P N
B C E
H T 8 3 R 0 7 4
Rev. 1.00
19
May 17, 2007
HT83R074
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
20
May 17, 2007
HT83R074
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
21
May 17, 2007
HT83R074
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
22
May 17, 2007
HT83R074
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
23
May 17, 2007
HT83R074
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
24
May 17, 2007
HT83R074
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
25
May 17, 2007
HT83R074
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
May 17, 2007
HT83R074
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
May 17, 2007
HT83R074
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
May 17, 2007
HT83R074
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
29
May 17, 2007
HT83R074
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
May 17, 2007
HT83R074
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
May 17, 2007
HT83R074
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
May 17, 2007
HT83R074
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
May 17, 2007
HT83R074
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
May 17, 2007
HT83R074
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
35
May 17, 2007
HT83R074
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
C
Spindle Hole Diameter
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.00
36
May 17, 2007
HT83R074
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.00
21.3
37
May 17, 2007
HT83R074
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
38
May 17, 2007